projects: linux: io: updates up to W47

5 files changed, 50 insertions, 24 deletions

diff --git a/projects/linux/io/SDHI-refactor-SDHn.yaml b/projects/linux/io/SDHI-refactor-SDHn.yaml
deleted file mode 100644
index 0f47e9d..0000000
--- a/projects/linux/io/SDHI-refactor-SDHn.yaml
+++ /dev/null
@@ -1,21 +0,0 @@
-title: "SDHI; refactor SDHn to be a seperate clock"
-team: IO
-key: 008d3362-4055-11eb-9620-cb34de96bb07
-status: Active
-assignee: Wolfram
-
-bsp41x:
- - 7a967a750a3409554d72d9bc3842722e86703125 # clk: Add support parent clock in set_phase
- - 5e0b119a284593bbe5966da6049e2b5272830954 # clk: rcar-gen3: Add set_phase to set SDnCKCR in HS400
- - a91a23d1d738335d5a92af0e2a18b1ddbcf3d602 # mmc: renesas_sdhi: Fix SDnCKCR setting in 4TAP SoC
-
-upstream:
-
-comments:
- - "check mail thread 'SDnCKCR setting for HS200 #297087'"
- - "BSP will use a workaround, but we should model SDHn as a seperate clock"
- - "This allows us to handle proper frequency settings from the SDHI driver"
- - "Wolfram has a sketch with two clocks using generic divider and gate combined"
- - "rfc v1: https://lore.kernel.org/r/20210928200804.50922-1-wsa+renesas@sang-engineering.com"
- - "rfc v2 in progress; working out details for the DT binding scheme"
- - "rfc v2: https://lore.kernel.org/r/20211110191610.5664-1-wsa+renesas@sang-engineering.com"
diff --git a/projects/linux/io/SDHI-refactor-abort-tuning.yaml b/projects/linux/io/SDHI-refactor-abort-tuning.yaml
index 765483e..184a85e 100644
--- a/projects/linux/io/SDHI-refactor-abort-tuning.yaml
+++ b/projects/linux/io/SDHI-refactor-abort-tuning.yaml
@@ -4,6 +4,9 @@ key: 2df07932-117d-11ec-bc26-4ffb07de7674
 assignee: Wolfram
 status: Active
 
+bsp51x:
+ - 2d7c017355ce83b26ef739183f28a8e0da5ea233 # mmc: core: mmc_ops: Enable stop command
+
 upstream:
 
 comments:
diff --git a/projects/linux/io/BSP41-upport-unsorted-patches.yaml b/projects/linux/io/done/BSP41-upport-unsorted-patches.yaml
index 904adf5..26111ce 100644
--- a/projects/linux/io/BSP41-upport-unsorted-patches.yaml
+++ b/projects/linux/io/done/BSP41-upport-unsorted-patches.yaml
@@ -1,7 +1,7 @@
 title: upport minor patches from BSP4.1x
 team: IO
 key: 58564d54-9c3a-11eb-8bce-db35e785a1f7
-status: Active
+status: Done
 
 bsp41x:
  - 86293fe9951d83eb6db6be8db54d5ff88bf89cab # i2c: rcar: Tidy up the register order for hardware specification ver1.00.
@@ -15,6 +15,8 @@ upstream:
  - torvalds: e7f4264821a4ee07775f3775f8530cfa9a6d4b5d # i2c: rcar: enable interrupts before starting transfer
  - torvalds: 7464779fa8551b90d5797d4020b0bdb7e6422eb9 # serial: sh-sci: suppress warning for ports without dma channels
  - torvalds: c58a3ae58bce99d20fdbc5d97beecf31cc19f3dd # serial: sh-sci: do not warn if DMA transfers are not supported
+ - torvalds: 540cffbab8b8e6c52a4121666ca18d6e94586ed2 # gpio: pca953x: do not ignore i2c errors
+ - torvalds: 94e290b0e9a6c360a5660c480c1ba996d892c650 # i2c: rcar: wait for data empty before starting DMA
 
 comments:
  - 86293fe9951d83eb6db6be8db54d5ff88bf89cab:
@@ -26,12 +28,14 @@ comments:
    - merged
  - b6dde4a58f547e0c52ff4c797b9d378419833eb7:
    - double check and upport
+   - already upstream
  - f3670a6aa2bd5f47d79fb0360c0a7a3eb629d1a0:
    - double check and upport
+   - alternative solution already upstream since 2019-03
  - 9915223f41c7d680aaaed12971601dc038ce76a3:
    - double check and upport
    - v1 sent by Geert
    - merged
  - 12ef3158400ee43d9fb662f8dae804bc89aa5799:
    - double check and upport
-   - alternative solutions are upstream
+   - alternative solutions are upstream since 2017-09
diff --git a/projects/linux/io/done/SDHI-refactor-SDHn.yaml b/projects/linux/io/done/SDHI-refactor-SDHn.yaml
new file mode 100644
index 0000000..402ef61
--- /dev/null
+++ b/projects/linux/io/done/SDHI-refactor-SDHn.yaml
@@ -0,0 +1,33 @@
+title: "SDHI; refactor SDHn to be a seperate clock"
+team: IO
+key: 008d3362-4055-11eb-9620-cb34de96bb07
+status: Done
+assignee: Wolfram
+
+bsp41x:
+ - 7a967a750a3409554d72d9bc3842722e86703125 # clk: Add support parent clock in set_phase
+ - 5e0b119a284593bbe5966da6049e2b5272830954 # clk: rcar-gen3: Add set_phase to set SDnCKCR in HS400
+ - a91a23d1d738335d5a92af0e2a18b1ddbcf3d602 # mmc: renesas_sdhi: Fix SDnCKCR setting in 4TAP SoC
+
+upstream:
+ - next: a31cf51bf6b4bf78ccb1c9fb40ea6231cf3df433 # clk: renesas: rcar-gen3: Add dummy SDnH clock
+ - next: 1abd04480866cead7b4129bd03246315b4575334 # clk: renesas: rcar-gen3: Add SDnH clock
+ - next: 63494b6f98f26f45e0e7929654dd67d6715cc495 # clk: renesas: r8a779a0: Add SDnH clock to V3U
+ - next: 627151b4966fe68029cd14aa5fd81f5f0c67fa26 # mmc: renesas_sdhi: Flag non-standard SDnH handling for V3M
+ - next: bb6d3fa98a418b071c5f735e75558604f5f4af66 # clk: renesas: rcar-gen3: Switch to new SD clock handling
+ - next: d3a52bc41da0e4f7abd2df866a52b1e27c25aef5 # clk: renesas: rcar-gen3: Remove outdated SD_SKIP_FIRST
+ - next: 079e83b958a3c3d9c84e24b28478d57adc1cd7fe # mmc: renesas_sdhi: Use dev_err_probe when getting clock fails
+ - next: e5f7e81ee430acb6d1fa9a6323fe645bd52e0b9c # mmc: renesas_sdhi: Parse DT for SDnH
+ - next: eca6ab6e362e3ae22b6c2769c4b6911bd0fb8ab1 # arm64: dts: reneas: rcar-gen3: Add SDnH clocks
+ - next: 52e844ee9a6f460e6160736a43ef13317a91ca74 # arm64: dts: reneas: rzg2: Add SDnH clocks
+ - next: e051025efac3929ca7e3e2f2c8860d3447366ebc # dt-bindings: mmc: renesas,sdhi: Add optional SDnH clock
+
+comments:
+ - "check mail thread 'SDnCKCR setting for HS200 #297087'"
+ - "BSP will use a workaround, but we should model SDHn as a seperate clock"
+ - "This allows us to handle proper frequency settings from the SDHI driver"
+ - "Wolfram has a sketch with two clocks using generic divider and gate combined"
+ - "rfc v1: https://lore.kernel.org/r/20210928200804.50922-1-wsa+renesas@sang-engineering.com"
+ - "rfc v2 in progress; working out details for the DT binding scheme"
+ - "rfc v2: https://lore.kernel.org/r/20211110191610.5664-1-wsa+renesas@sang-engineering.com"
+ - "merged"
diff --git a/projects/linux/io/V3U-enable_RPC.yaml b/projects/linux/io/done/V3U-enable_RPC.yaml
index 50febf3..9aa37ac 100644
--- a/projects/linux/io/V3U-enable_RPC.yaml
+++ b/projects/linux/io/done/V3U-enable_RPC.yaml
@@ -1,7 +1,7 @@
 title: V3U; upport RPC fixes and enable for V3U
 team: IO
 key: af952030-922c-11eb-a0e9-17a4402ca5c4
-status: Active
+status: Done
 assignee: Wolfram
 
 bsp41x:
@@ -18,6 +18,8 @@ upstream:
  - torvalds: 27c9d7635d23416f5e791508882f34157dde23f5 # clk: renesas: r8a779a0: Add RPC support
  - torvalds: 5de968a25a30302c7714ae1c80b0eaff6834e2ed # arm64: dts: renesas: r8a779a0: Add RPC node
  - torvalds: f28daeedd7f920e172d60a97341be42430175a42 # arm64: dts: renesas: falcon-cpu: Add SPI flash via RPC
+ - next: 57ea9daad51f7707f61a602a743decf10cf9fea9 # memory: renesas-rpc-if: avoid use of undocumented bits
+ - next: 3542de6a5b159fac0e7ca84d77a57ea99125d6b1 # memory: renesas-rpc-if: refactor MOIIO and IOFV macros
 
 comments:
  - because HW access to V3U is still very limited, it is suggested to upport/refactor the driver fixes using locally available boards first
@@ -32,6 +34,11 @@ comments:
    - Renesas Europe upstreamed G2L support providing additional information
    - BSP team responded, all information complete now
    - patch will be created on top of G2L support. We wait for the new version
+   - v1; https://lore.kernel.org/r/20211117093710.14430-1-wsa+renesas@sang-engineering.com
+   - merged
+   - cleanup patch followed
+   - https://lore.kernel.org/r/20211119110442.4946-1-wsa+renesas@sang-engineering.com
+   - merged
  - 0d37f69cacb3343514380ff4a9c271b746959190
    - must be upported before enabling V3U. Otherwise flash memory might get broken, i.e. wrongly fused
    - very likely must be refactored. The mixture of regmap and direct register writes does not look good