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Diffstat (limited to 'projects/linux/io/SDHI-refactor-SDHn.yaml')
| -rw-r--r-- | projects/linux/io/SDHI-refactor-SDHn.yaml | 21 |
1 files changed, 0 insertions, 21 deletions
diff --git a/projects/linux/io/SDHI-refactor-SDHn.yaml b/projects/linux/io/SDHI-refactor-SDHn.yaml deleted file mode 100644 index 0f47e9d..0000000 --- a/projects/linux/io/SDHI-refactor-SDHn.yaml +++ /dev/null @@ -1,21 +0,0 @@ -title: "SDHI; refactor SDHn to be a seperate clock" -team: IO -key: 008d3362-4055-11eb-9620-cb34de96bb07 -status: Active -assignee: Wolfram - -bsp41x: - - 7a967a750a3409554d72d9bc3842722e86703125 # clk: Add support parent clock in set_phase - - 5e0b119a284593bbe5966da6049e2b5272830954 # clk: rcar-gen3: Add set_phase to set SDnCKCR in HS400 - - a91a23d1d738335d5a92af0e2a18b1ddbcf3d602 # mmc: renesas_sdhi: Fix SDnCKCR setting in 4TAP SoC - -upstream: - -comments: - - "check mail thread 'SDnCKCR setting for HS200 #297087'" - - "BSP will use a workaround, but we should model SDHn as a seperate clock" - - "This allows us to handle proper frequency settings from the SDHI driver" - - "Wolfram has a sketch with two clocks using generic divider and gate combined" - - "rfc v1: https://lore.kernel.org/r/20210928200804.50922-1-wsa+renesas@sang-engineering.com" - - "rfc v2 in progress; working out details for the DT binding scheme" - - "rfc v2: https://lore.kernel.org/r/20211110191610.5664-1-wsa+renesas@sang-engineering.com" |