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+title: V3U; upport RPC fixes and enable for V3U
+team: IO
+key: af952030-922c-11eb-a0e9-17a4402ca5c4
+status: Done
+assignee: Wolfram
+
+bsp41x:
+ - f817442ce56d351a2c69515570ca750edb54622b # memory: renesas-rpc-if: Do not write to reserved bits
+ - 0d37f69cacb3343514380ff4a9c271b746959190 # memory: renesas-rpc-if: Correct QSPI data transfer in Manual mode
+ - b587ed1d5e129cc32ab3c69b9489377bf158b9b6 # dt-bindings: rpc: renesas-rpc-if: Add support for the R8A779A0 RPC-IF
+ - e05ce4b3ba724c77bd19f138476dc97d27eba824 # arm64: dts: renesas: r8a779a0: Add RPC-IF node
+ - 44c210c0fa36a53c3fb08e95e5a6dad8ad9b345d # arm64: dts: renesas: falcon: Add QSPI flash support
+
+upstream:
+ - torvalds: fff53a551db50f5edecaa0b29a64056ab8d2bbca # memory: renesas-rpc-if: Correct QSPI data transfer in Manual mode
+ - torvalds: 797f082738b10ff397c8d3b7804b747d766e62e6 # dt-bindings: rpc: renesas-rpc-if: Add support for the R8A779A0 RPC-IF
+ - torvalds: 6f21d145b90f3f5769eb6615af601a973e365a64 # clk: renesas: cpg-lib: Move RPC clock registration to the library
+ - torvalds: 27c9d7635d23416f5e791508882f34157dde23f5 # clk: renesas: r8a779a0: Add RPC support
+ - torvalds: 5de968a25a30302c7714ae1c80b0eaff6834e2ed # arm64: dts: renesas: r8a779a0: Add RPC node
+ - torvalds: f28daeedd7f920e172d60a97341be42430175a42 # arm64: dts: renesas: falcon-cpu: Add SPI flash via RPC
+ - next: 57ea9daad51f7707f61a602a743decf10cf9fea9 # memory: renesas-rpc-if: avoid use of undocumented bits
+ - next: 3542de6a5b159fac0e7ca84d77a57ea99125d6b1 # memory: renesas-rpc-if: refactor MOIIO and IOFV macros
+
+comments:
+ - because HW access to V3U is still very limited, it is suggested to upport/refactor the driver fixes using locally available boards first
+ - for that, RPC must be enabled in TFA, see github.com/ARM-software/arm-trusted-firmware/commit/6e93392b7a761c43c1f4b5b564fe57c51d806388
+ - another option is to use Eagle/Condor boards remotely with JFFS2 and check for CRC failures
+ - using the user-partition on an Eagle board turned out to be sufficient
+
+ - f817442ce56d351a2c69515570ca750edb54622b
+   - needs more information why the undocumented bits were needed previously
+   - further investigation showed that the patch is okay, but maybe one bitfield was accidently removed
+   - asked BSP team for clarification
+   - Renesas Europe upstreamed G2L support providing additional information
+   - BSP team responded, all information complete now
+   - patch will be created on top of G2L support. We wait for the new version
+   - v1; https://lore.kernel.org/r/20211117093710.14430-1-wsa+renesas@sang-engineering.com
+   - merged
+   - cleanup patch followed
+   - https://lore.kernel.org/r/20211119110442.4946-1-wsa+renesas@sang-engineering.com
+   - merged
+ - 0d37f69cacb3343514380ff4a9c271b746959190
+   - must be upported before enabling V3U. Otherwise flash memory might get broken, i.e. wrongly fused
+   - very likely must be refactored. The mixture of regmap and direct register writes does not look good
+   - RFC v1 sent to an internal mailing list
+   - v1; https://lore.kernel.org/r/20210922091007.5516-1-wsa+renesas@sang-engineering.com
+   - merged
+ - e05ce4b3ba724c77bd19f138476dc97d27eba824, 44c210c0fa36a53c3fb08e95e5a6dad8ad9b345d
+   - upstream needs also to refactor RPC clock handling into CPG lib
+   - rfc v1; https://lore.kernel.org/r/20210913065317.2297-1-wsa+renesas@sang-engineering.com
+   - v1; https://lore.kernel.org/r/20210929064924.1997-1-wsa+renesas@sang-engineering.com
+   - v2; https://lore.kernel.org/r/20211006085836.42155-1-wsa+renesas@sang-engineering.com
+   - merged
+ - b587ed1d5e129cc32ab3c69b9489377bf158b9b6
+   - v1; https://lore.kernel.org/r/20210922085831.5375-1-wsa+renesas@sang-engineering.com
+   - merged