diff options
author | Wolfram Sang <wsa+renesas@sang-engineering.com> | 2021-11-16 10:25:55 +0100 |
---|---|---|
committer | Wolfram Sang <wsa+renesas@sang-engineering.com> | 2021-11-26 12:16:56 +0100 |
commit | 88c014ee835275b0710a08bc47d3641d8bdbad07 (patch) | |
tree | edef72f7a7445062f19b94db850281ebd03da5c6 /projects/linux/io/done/SDHI-refactor-SDHn.yaml | |
parent | 85f830063cfb8f388c5199eeb34fe3df3d8b5225 (diff) |
projects: linux: io: updates up to W47
Diffstat (limited to 'projects/linux/io/done/SDHI-refactor-SDHn.yaml')
-rw-r--r-- | projects/linux/io/done/SDHI-refactor-SDHn.yaml | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/projects/linux/io/done/SDHI-refactor-SDHn.yaml b/projects/linux/io/done/SDHI-refactor-SDHn.yaml new file mode 100644 index 0000000..402ef61 --- /dev/null +++ b/projects/linux/io/done/SDHI-refactor-SDHn.yaml @@ -0,0 +1,33 @@ +title: "SDHI; refactor SDHn to be a seperate clock" +team: IO +key: 008d3362-4055-11eb-9620-cb34de96bb07 +status: Done +assignee: Wolfram + +bsp41x: + - 7a967a750a3409554d72d9bc3842722e86703125 # clk: Add support parent clock in set_phase + - 5e0b119a284593bbe5966da6049e2b5272830954 # clk: rcar-gen3: Add set_phase to set SDnCKCR in HS400 + - a91a23d1d738335d5a92af0e2a18b1ddbcf3d602 # mmc: renesas_sdhi: Fix SDnCKCR setting in 4TAP SoC + +upstream: + - next: a31cf51bf6b4bf78ccb1c9fb40ea6231cf3df433 # clk: renesas: rcar-gen3: Add dummy SDnH clock + - next: 1abd04480866cead7b4129bd03246315b4575334 # clk: renesas: rcar-gen3: Add SDnH clock + - next: 63494b6f98f26f45e0e7929654dd67d6715cc495 # clk: renesas: r8a779a0: Add SDnH clock to V3U + - next: 627151b4966fe68029cd14aa5fd81f5f0c67fa26 # mmc: renesas_sdhi: Flag non-standard SDnH handling for V3M + - next: bb6d3fa98a418b071c5f735e75558604f5f4af66 # clk: renesas: rcar-gen3: Switch to new SD clock handling + - next: d3a52bc41da0e4f7abd2df866a52b1e27c25aef5 # clk: renesas: rcar-gen3: Remove outdated SD_SKIP_FIRST + - next: 079e83b958a3c3d9c84e24b28478d57adc1cd7fe # mmc: renesas_sdhi: Use dev_err_probe when getting clock fails + - next: e5f7e81ee430acb6d1fa9a6323fe645bd52e0b9c # mmc: renesas_sdhi: Parse DT for SDnH + - next: eca6ab6e362e3ae22b6c2769c4b6911bd0fb8ab1 # arm64: dts: reneas: rcar-gen3: Add SDnH clocks + - next: 52e844ee9a6f460e6160736a43ef13317a91ca74 # arm64: dts: reneas: rzg2: Add SDnH clocks + - next: e051025efac3929ca7e3e2f2c8860d3447366ebc # dt-bindings: mmc: renesas,sdhi: Add optional SDnH clock + +comments: + - "check mail thread 'SDnCKCR setting for HS200 #297087'" + - "BSP will use a workaround, but we should model SDHn as a seperate clock" + - "This allows us to handle proper frequency settings from the SDHI driver" + - "Wolfram has a sketch with two clocks using generic divider and gate combined" + - "rfc v1: https://lore.kernel.org/r/20210928200804.50922-1-wsa+renesas@sang-engineering.com" + - "rfc v2 in progress; working out details for the DT binding scheme" + - "rfc v2: https://lore.kernel.org/r/20211110191610.5664-1-wsa+renesas@sang-engineering.com" + - "merged" |