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author | Wolfram Sang <wsa+renesas@sang-engineering.com> | 2021-04-30 15:05:47 +0200 |
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committer | Wolfram Sang <wsa+renesas@sang-engineering.com> | 2021-04-30 15:43:14 +0200 |
commit | bd3a546d6e75ae33064e5d61a9b1df868d586ff6 (patch) | |
tree | 6b35d32760bbc3cee401c46baf03d7259fca0130 /projects/linux/io/SDHI-refactor-SDHn.yaml | |
parent | 70d8067606ee2713e84cfaf0417312192ebd3827 (diff) |
linux: bsp-41x: move SDHI items to proper places
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Diffstat (limited to 'projects/linux/io/SDHI-refactor-SDHn.yaml')
-rw-r--r-- | projects/linux/io/SDHI-refactor-SDHn.yaml | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/projects/linux/io/SDHI-refactor-SDHn.yaml b/projects/linux/io/SDHI-refactor-SDHn.yaml index ebffbf8..e9dbe0f 100644 --- a/projects/linux/io/SDHI-refactor-SDHn.yaml +++ b/projects/linux/io/SDHI-refactor-SDHn.yaml @@ -4,6 +4,11 @@ key: 008d3362-4055-11eb-9620-cb34de96bb07 status: New assignee: Wolfram +bsp41x: + - 7a967a750a3409554d72d9bc3842722e86703125 # clk: Add support parent clock in set_phase + - 5e0b119a284593bbe5966da6049e2b5272830954 # clk: rcar-gen3: Add set_phase to set SDnCKCR in HS400 + - a91a23d1d738335d5a92af0e2a18b1ddbcf3d602 # mmc: renesas_sdhi: Fix SDnCKCR setting in 4TAP SoC + upstream: comments: |