diff options
| author | Wolfram Sang <wsa+renesas@sang-engineering.com> | 2021-04-30 15:05:47 +0200 |
|---|---|---|
| committer | Wolfram Sang <wsa+renesas@sang-engineering.com> | 2021-04-30 15:43:14 +0200 |
| commit | bd3a546d6e75ae33064e5d61a9b1df868d586ff6 (patch) | |
| tree | 6b35d32760bbc3cee401c46baf03d7259fca0130 /projects/linux/io | |
| parent | 70d8067606ee2713e84cfaf0417312192ebd3827 (diff) | |
linux: bsp-41x: move SDHI items to proper places
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Diffstat (limited to 'projects/linux/io')
| -rw-r--r-- | projects/linux/io/SDHI-refactor-SDHn.yaml | 5 | ||||
| -rw-r--r-- | projects/linux/io/SDHI-upport-BSP-fixes.yaml | 26 |
2 files changed, 31 insertions, 0 deletions
diff --git a/projects/linux/io/SDHI-refactor-SDHn.yaml b/projects/linux/io/SDHI-refactor-SDHn.yaml index ebffbf8..e9dbe0f 100644 --- a/projects/linux/io/SDHI-refactor-SDHn.yaml +++ b/projects/linux/io/SDHI-refactor-SDHn.yaml @@ -4,6 +4,11 @@ key: 008d3362-4055-11eb-9620-cb34de96bb07 status: New assignee: Wolfram +bsp41x: + - 7a967a750a3409554d72d9bc3842722e86703125 # clk: Add support parent clock in set_phase + - 5e0b119a284593bbe5966da6049e2b5272830954 # clk: rcar-gen3: Add set_phase to set SDnCKCR in HS400 + - a91a23d1d738335d5a92af0e2a18b1ddbcf3d602 # mmc: renesas_sdhi: Fix SDnCKCR setting in 4TAP SoC + upstream: comments: diff --git a/projects/linux/io/SDHI-upport-BSP-fixes.yaml b/projects/linux/io/SDHI-upport-BSP-fixes.yaml new file mode 100644 index 0000000..3027d9a --- /dev/null +++ b/projects/linux/io/SDHI-upport-BSP-fixes.yaml @@ -0,0 +1,26 @@ +title: SDHI; upport BSP patches +team: IO +key: fe6714da-a9b4-11eb-a028-6bbd20fa8e8a +status: New +assignee: Wolfram + +bsp41x: + - 0237478dc67b71ff92082e06323c015631098b71 # arm64: dts: r8a77980-v3hsk: Enable onboard eMMC + - c2ca1ccb83afd7c790ae361c720d257e050483f2 # mmc: core: Issue power off notification in mmc_remove() + - 5d60e36aaa96fa39d1a524cc4ff373c0f36616e0 # mmc: renesas_sdhi: reset calibration register + - 73405fef502d43737be9a50d29935bee133fe7ab # mmc: renesas_sdhi: Add internal DMA transfer end + - 20e5623df1aaa74301675122b910f063cdcabe7e # mmc: tmio: Add internal DMA transfer end + +upstream: + +comments: + - 0237478dc67b71ff92082e06323c015631098b71 + - do we have V3H hardware in Magnus lab? + - c2ca1ccb83afd7c790ae361c720d257e050483f2 + - https://patchwork.kernel.org/project/linux-mmc/patch/1605005330-7178-1-git-send-email-yoshihiro.shimoda.uh@renesas.com/ + - 5d60e36aaa96fa39d1a524cc4ff373c0f36616e0 + - before calling 'renesas_sdhi_adjust_hs400_mode_disable()', change the if to 'if (gen3)'? + - 73405fef502d43737be9a50d29935bee133fe7ab + - Only for H3/M3-W ES1.0, but why does mainline work? + - 20e5623df1aaa74301675122b910f063cdcabe7e + - Why does mainline work without it? |