diff options
| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-03-02 17:41:22 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-03-04 09:31:01 +0100 |
| commit | e8f6c633f5eaad4363b89809676d973066bbc7a1 (patch) | |
| tree | f2d3d588cfc1e4f56d95d545b62bde054a46c54f | |
| parent | 1c2426c6bb61b174d8cb585ef29979005537d330 (diff) | |
bsp-51x-upport-request: Move SDHI HS400 hack to SDHI-refactor-SDHn task
Cfr. the corresponding bsp-41x commit.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
| -rw-r--r-- | projects/linux/bsp-51x-upport-request.yaml | 1 | ||||
| -rw-r--r-- | projects/linux/io/done/SDHI-refactor-SDHn.yaml | 1 |
2 files changed, 1 insertions, 1 deletions
diff --git a/projects/linux/bsp-51x-upport-request.yaml b/projects/linux/bsp-51x-upport-request.yaml index 12a3574..fd9cb4d 100644 --- a/projects/linux/bsp-51x-upport-request.yaml +++ b/projects/linux/bsp-51x-upport-request.yaml @@ -169,7 +169,6 @@ bsp51x: - e7bcd75b2ab34b3535d568eb5f8a6042413a0677 # clk: renesas: r8a77{96, 965, 990}: Add ADG clock - e2002ddf1a8a2d3229cec9f0be1d398099ef2c83 # clk: renesas: r8a77{96, 965, 990}: Add ADSP clock - df47d799536c8a1ef50b6219bdacce458c4d3a57 # clk: renesas: r8a77{96, 965, 990}: Add VCP4 clocks - - a605f70375dcab767226f340c570e178f5b53456 # clk: renesas: rcar-gen3: Add set_phase to set SDnCKCR in HS400 - 9dfba43fd5dc1da1bfec66dadfb10c14cf4a72f9 # clk: renesas: rcar-gen3: Use max_rate as maximum rate for normal clock instead max_freq - 7935bac0719228175524c4d868c1244ce3579840 # crypto: ccree - add support cts1(cbc) algorithm - 0e906164fd49f99b88b66526f393e80dabf48dcd # crypto: ccree - add support for MULTI2 mode diff --git a/projects/linux/io/done/SDHI-refactor-SDHn.yaml b/projects/linux/io/done/SDHI-refactor-SDHn.yaml index 869148b..0b7b17b 100644 --- a/projects/linux/io/done/SDHI-refactor-SDHn.yaml +++ b/projects/linux/io/done/SDHI-refactor-SDHn.yaml @@ -11,6 +11,7 @@ bsp41x: bsp51x: - 7013e474a179b299f9a2e0e28f87a6de8820d78b # clk: Add support parent clock in set_phase + - a605f70375dcab767226f340c570e178f5b53456 # clk: renesas: rcar-gen3: Add set_phase to set SDnCKCR in HS400 - bbf1b3923dd954f3c904a1aefd983dae76faf7be # mmc: renesas_sdhi: Fix SDnCKCR setting in 4TAP SoC upstream: |