Age | Commit message (Collapse) | Author |
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This is the correct fix for the RS690 and hopefully the dma coherent work.
For now we limit everybody to a 32-bit DMA mask but it is possible for
RS690 to use a 40-bit DMA mask for the GART table itself,
and the PCIE cards can use 40-bits for the table entries.
Signed-off-by: Dave Airlie <airlied@redhat.com>
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DMA command submission. It's worth remembering that all new bright ideas on how
to make this command reader work properly and according to docs
will probably fail :( Bring in some old code.
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The docs state bits 4-11 represent bits 32-39 of a 40-bit address
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If we ever want to be able to use the 3D engine we have no choice. It
appears that the tiling setup (required for 3D on G8x) is in the page tables.
The immediate benefit of this change however is that it's now not possible
for a client to use the GPU to render over the top of important engine setup
tables, which also live in VRAM.
G8x VRAM size is limited to 512MiB at the moment, as we use a 1-1 mapping
of real vram pages to their offset within the start of a channel's VRAM
DMA object and only populate a single PDE for VRAM use.
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Conflicts:
linux-core/drm_compat.c
linux-core/drm_compat.h
linux-core/drm_ttm.c
shared-core/i915_dma.c
Bump driver minor to 13 due to introduction of new
relocation type.
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modesetting-101
Conflicts:
shared-core/i915_dma.c
shared-core/i915_drv.h
shared-core/i915_irq.c
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they are not pipe A specific. Remove pipe B code.
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Also adjust i915 irq handling as it follows the 16bit'ism's
of the i8xx series.
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Also, power cycle PGRAPH when resetting AGP -- it seems to fix problems encountered by p0g on nv25
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if we are unloading the module, there is no master so therefore no lock
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into modesetting-101
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My 965GM gets interrupts stuck when using the old PIPE_VBLANK interrupt.
Switch to the PIPE_EVENT interrupt mechanism, and set the PIPE*STAT
registers to use START_VBLANK on 965 and VBLANK on previous chips.
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Will hopefully work a bit better than previous code, which depended on
knowing the channel's most recent PUT value. Some chips always return
0 on reading these regs, and currently userspace is the only other entity
which knows the value.
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Not only was this entirely pointless, it actually causes my NV30GL to
die randomly when channels are destroyed.
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Conflicts:
shared-core/drm.h
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this adds something to say the kernel initialised the memory region not
the userspace. and blocks userspace from deallocating kernel areas
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taken from modesetting branch but could be useful outside it.
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Conflicts:
linux-core/drmP.h
linux-core/drm_drv.c
linux-core/drm_proc.c
linux-core/drm_stub.c
linux-core/drm_sysfs.c
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Rip out the whole head thing and replace it with an idr and drm_minor
structure.
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writting relocations, otherwise the GPU probably sees some
inconsistent data. Fix fd.o bug#14656
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Conflicts:
linux-core/drm_compat.c
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to leap it's vblank count a huge value.
This will stall some applications that switch video mode if vblank_mode is set to a non zero value in drirc.
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This change adds a driver feature that for i915 is controlled by a module
parameter. You now need to do insmod i915.ko modeset=1 to enable it the
modesetting paths.
It also fixes up lots of X paths. I can run my new DDX driver on this code
with and without modesetting enabled
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modesetting-101
Conflicts:
shared-core/i915_dma.c
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In particular -EAGAINs, which should be common during Xserver operation.
Also handle the fence creation failure case.
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Texture uploads could hit the blitter coordinate limit, adjust the texture
offset when uploading the pieces. Make sure to check the end address of the
upload too.
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