| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2008-03-21 | r500: fragment program upload is also used to upload constants. | Dave Airlie | |
| Limit frag address to 8 bits | |||
| 2008-03-20 | drm: fixup r500fp submission | Dave Airlie | |
| 2008-03-19 | move some more r300 regs into not allowed on r500 | Dave Airlie | |
| 2008-03-17 | initial r500 RS and FP register and upload code | Dave Airlie | |
| 2008-03-17 | drm/pcigart: fix the pci gart to use the drm_pci wrapper. | Dave Airlie | |
| This is the correct fix for the RS690 and hopefully the dma coherent work. For now we limit everybody to a 32-bit DMA mask but it is possible for RS690 to use a 40-bit DMA mask for the GART table itself, and the PCIE cards can use 40-bits for the table entries. Signed-off-by: Dave Airlie <airlied@redhat.com> | |||
| 2008-03-16 | Avoid unnecessary waits for command regulator pause. | Thomas Hellstrom | |
| 2008-03-16 | [via] Remove some leftover vars. | Thomas Hellstrom | |
| 2008-03-16 | [via] The millionth fixup for the millionth-1 attempt to stabilize the AGP | Thomas Hellstrom | |
| DMA command submission. It's worth remembering that all new bright ideas on how to make this command reader work properly and according to docs will probably fail :( Bring in some old code. | |||
| 2008-03-16 | [via] Fix driver after vblank-rework merge. | Thomas Hellstrom | |
| 2008-03-16 | drm/rs690: set AGP_BASE_2 to 0 | Dave Airlie | |
| 2008-03-16 | drm: set rs690 gart base completly. | Dave Airlie | |
| The docs state bits 4-11 represent bits 32-39 of a 40-bit address | |||
| 2008-03-12 | Fix chip family for RV550 | Alex Deucher | |
| 2008-03-13 | nv50: force channel vram access through vm | Ben Skeggs | |
| If we ever want to be able to use the 3D engine we have no choice. It appears that the tiling setup (required for 3D on G8x) is in the page tables. The immediate benefit of this change however is that it's now not possible for a client to use the GPU to render over the top of important engine setup tables, which also live in VRAM. G8x VRAM size is limited to 512MiB at the moment, as we use a 1-1 mapping of real vram pages to their offset within the start of a channel's VRAM DMA object and only populate a single PDE for VRAM use. | |||
| 2008-03-12 | Merge branch 'intel-post-reloc' | Thomas Hellstrom | |
| Conflicts: linux-core/drm_compat.c linux-core/drm_compat.h linux-core/drm_ttm.c shared-core/i915_dma.c Bump driver minor to 13 due to introduction of new relocation type. | |||
| 2008-03-12 | Avoid large kmallocs. | Thomas Hellstrom | |
| 2008-03-11 | nouveau: move AGP reset to mem_init_agp | Stuart Bennett | |
| Also, power cycle PGRAPH when resetting AGP -- it seems to fix problems encountered by p0g on nv25 | |||
| 2008-03-08 | Switch from PIPE_VBLANK to PIPE_EVENT interrupts. | Keith Packard | |
| My 965GM gets interrupts stuck when using the old PIPE_VBLANK interrupt. Switch to the PIPE_EVENT interrupt mechanism, and set the PIPE*STAT registers to use START_VBLANK on 965 and VBLANK on previous chips. | |||
| 2008-03-08 | drm/radeon: check sarea_priv exists | Dave Airlie | |
| 2008-03-07 | nouveau: redo channel idle detection | Ben Skeggs | |
| Will hopefully work a bit better than previous code, which depended on knowing the channel's most recent PUT value. Some chips always return 0 on reading these regs, and currently userspace is the only other entity which knows the value. | |||
| 2008-03-07 | nouveau: don't touch NV_USER regs on channel destroy. | Ben Skeggs | |
| Not only was this entirely pointless, it actually causes my NV30GL to die randomly when channels are destroyed. | |||
| 2008-03-06 | ttm: make sure userspace can't destroy kernel create memory managers | Dave Airlie | |
| this adds something to say the kernel initialised the memory region not the userspace. and blocks userspace from deallocating kernel areas | |||
| 2008-03-06 | drm/ttm: add ioctl to get back memory managed area sized | Dave Airlie | |
| taken from modesetting branch but could be useful outside it. | |||
| 2008-03-06 | drm: reorganise minor number handling using code from modesetting branch | Dave Airlie | |
| Rip out the whole head thing and replace it with an idr and drm_minor structure. | |||
| 2008-03-05 | i915: Evict if relocatee buffer is CACHED_MAPPED before | Xiang, Haihao | |
| writting relocations, otherwise the GPU probably sees some inconsistent data. Fix fd.o bug#14656 | |||
| 2008-03-04 | Clarify when WAIT_LAZY is relevant to users. | Eric Anholt | |
| 2008-03-04 | Remove unused DRM_FENCE_FLAG_WAIT_IGNORE_SIGNALS. | Eric Anholt | |
| 2008-03-03 | [i915] 2D driver may reset Frame count value, this may lead driver | Zou Nan hai | |
| to leap it's vblank count a huge value. This will stall some applications that switch video mode if vblank_mode is set to a non zero value in drirc. | |||
| 2008-02-29 | Working revision. | Thomas Hellstrom | |
| 2008-02-29 | More post-ioctl work. | Thomas Hellstrom | |
| 2008-02-27 | Reinstate buffer idle before applying relocations. | Thomas Hellstrom | |
| 2008-02-27 | Don't wait for buffer idle before applying relocations. | Thomas Hellstrom | |
| 2008-02-26 | [i915] Relocation fixes. | Thomas Hellstrom | |
| 2008-02-26 | Make the execbuffer code reasonably safe against errors. | Thomas Hellstrom | |
| In particular -EAGAINs, which should be common during Xserver operation. Also handle the fence creation failure case. | |||
| 2008-02-23 | fix texture uploads with large 3d textures (bug 13980) | Roland Scheidegger | |
| Texture uploads could hit the blitter coordinate limit, adjust the texture offset when uploading the pieces. Make sure to check the end address of the upload too. | |||
| 2008-02-22 | nouveau: Remove some random (french) comment. | Maarten Maathuis | |
| 2008-02-22 | nouveau: A single define of dma skips is more than enough. | Maarten Maathuis | |
| 2008-02-22 | Fix one last occurance of struct _drm_i915_batchbuffer. | Kristian Høgsberg | |
| Thanks to Todd Merrill for pointing it out. | |||
| 2008-02-22 | i915: Remove leading underscore from struct tags. | Kristian Høgsberg | |
| This matches the changes in mesa to use the system drm includes for the definitions of the drm ioctl structs. | |||
| 2008-02-20 | fix SAREA | Alan Hourihane | |
| 2008-02-16 | [915]: more registers for S3 (DSPCLK_GATE_D, CACHE_MODE_0, MI_ARB_STATE) | Keith Packard | |
| Failing to preserve the MI_ARB_STATE register was causing FIFO underruns on the VGA output on my HP 2510p after resume. | |||
| 2008-02-16 | nouveau: no GART on ia64 either. | Stephane Marchesin | |
| 2008-02-16 | nv40: actually init all tile regs. | Ben Skeggs | |
| 2008-02-13 | i915: Add a dri2 init path that gets the lock from the dri2 sarea. | Kristian Høgsberg | |
| 2008-02-13 | i915: Only look up dev_priv->mmio_map if it's not already set up | Kristian Høgsberg | |
| 2008-02-13 | i915: Add I915_PARAM_CHIPSET_ID param to get chipset ID. | Kristian Høgsberg | |
| 2008-02-13 | i915: Make sarea_priv setup optional. | Kristian Høgsberg | |
| 2008-02-07 | Fix saveGR array size | Jesse Barnes | |
| Make sure we have enough room for all the GR registers or we'll end up clobbering the AR index register (which should actually be harmless unless the BIOS is making an assumption about it). | |||
| 2008-02-07 | i915: save/restore interrupt state | Jesse Barnes | |
| On resume, if the interrupt state isn't restored correctly, we may end up with a flood of unexpected or ill-timed interrupts, which could cause the kernel to disable the interrupt or vblank events to happen at the wrong time. So save/restore them properly. | |||
| 2008-02-05 | i915: Re-report breadcrumbs on poll to the fence manager, | Thomas Hellstrom | |
| since a breadcrumb may actually turn up before a corresponding fence object has been placed on the fence ring. | |||
| 2008-02-04 | nouveau: make nv34 work every time, not just every 2nd time | Stuart Bennett | |
| And make nv30_graph_init a bit more like mmio-traces | |||
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index : renesas/drm.git | |
| libdrm, cloned from git://anongit.freedesktop.org/mesa/drm | Laurent Pinchart |
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path: root/shared-core