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2013-09-18radeon: Fix tiling mode index for 1D tiled depth/stencil surfaces on CIKMichel Dänzer
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2013-09-06radeon: pad CS to 8 DWAlex Deucher
Aligns the IB to 8 DWs. The aligns the IB to the CP fetch size. r6xx also require at least 4 DW alignment to avoid a hw bug. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-09-06radeon: add berlin pci idsAlex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-28radeon: add kabini pci idsAlex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-28radeon: add Bonaire pci idsAlex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-28radeon: add CIK chip familiesAlex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-06radeon: correct RADEON_GEM_WAIT_IDLE useMark Kettenis
RADEON_GEM_WAIT_IDLE is declared DRM_IOW but libdrm uses it with drmCommandWriteRead instead of drmCommandWrite which leads to the ioctl being unmatched and returning an error on at least OpenBSD. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
2013-05-15radeon: add RADEON_SURF_FMASK flag which disables 2D->1D tiling transitionMarek Olšák
Signed-off-by: Marek Olšák <maraeo@gmail.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2013-05-13radeon: add HAINAN pci idsAlex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-05-13radeon: add HAINAN familyAlex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-04-25radeon: add new richland pci idsAlex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-04-25radeon: add new SI pci idsAlex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-04-12radeon: add si tiling support v5Jerome Glisse
v2: Only writte tile index if flags for it is set v3: Remove useless allow2d scanout flags v4: Split radeon_drm.h update to its own patch v5: update against lastest next tree for radeon Signed-off-by: Jerome Glisse <jglisse@redhat.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2013-03-08radeon: add pci ids for Richland APUsAlex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-03-07radeonsi: make sure tile_split field are not garbageJerome Glisse
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2013-02-04radeon: add OLAND pci idsAlex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-02-04radeon: add OLAND familyAlex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-01-18radeon: Fix 1D tiling layout on SI.Michel Dänzer
Very similar to Evergreen, but slightly different rules for tile / slice alignment. Fortunately, these map quite naturally onto the previous fixes for linear aligned layout on SI. 2D tiling still needs more work here and possibly in the kernel. Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
2012-11-28drm/radeon: track global bo name and always return the sameJerome Glisse
To avoid kernel rejecting cs if we return different global name for same bo keep track of global name and always return the same. Seems to fix issue with suspend/resume failing and repeatly printing following message : [drm:radeon_cs_ioctl] *ERROR* Failed to parse relocation -35! There might still be way for a rogue program to trigger this issue. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2012-11-21radeon: add new SI pci idAlex Deucher
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2012-10-26radeon: fix tile_split of 128-bit surface formats with 8x MSAAMarek Olšák
The calculation led to the number 8192, which is too high. Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-10-24radeon: fix unused-function warningAndreas Boll
radeon_cs_gem.c:333:13: warning: 'cs_gem_dump_bof' defined but not used [-Wunused-function] Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-10-16radeon: add some new SI pci idsAlex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-10-06radeon: fix stencil miptree allocation of combined ZS buffers on EG and SIMarek Olšák
This allows texturing with depth-stencil buffers directly without the copy to CB. The separate miptree description for stencil is added, because the stencil mipmap offsets are not really depth offsets/4 (at least for the texture units). Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-10-06radeon: don't force stencil tile split to 0Marek Olšák
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-10-03radeon: don't take the stencil-specific codepath for buffers without stencilMarek Olšák
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-06radeon: Sampling pitch for non-mipmaps seems padded to slice alignment on SI.Michel Dänzer
Another corner case that isn't well-explained yet. Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
2012-09-06radeon: Memory footprint of SI mipmap base level is padded to powers of two.Michel Dänzer
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
2012-09-05radeon: Fix layout of linear aligned mipmaps on SI.Michel Dänzer
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
2012-08-24radeon: align r600 msaa buffers to a multiple of macrotile size * num samplesMarek Olšák
I am not sure whether this is needed, but better be safe than sorry.
2012-08-24radeon: fix allocation of MSAA surfaces on r600-r700Marek Olšák
Reviewed-by: Jerome Glisse <jglisse@redhat.com>
2012-08-14radeon: add prime import/export supportDave Airlie
this adds radeon version of the prime import/export support. Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-08-09radeon: tweak TILE_SPLIT for MSAA surfacesMarek Olšák
Reviewed-by: Jerome Glisse <jglisse@redhat.com>
2012-08-09radeon: force 2D tiling for MSAA surfacesMarek Olšák
Reviewed-by: Jerome Glisse <jglisse@redhat.com>
2012-08-09radeon: optimize allocation for depth w/o stencil and stencil w/o depth on EGMarek Olšák
If we don't need stencil, don't allocate it. If we need only stencil (like PIPE_FORMAT_S8_UINT), don't allocate depth. v2: actually do it correctly Reviewed-by: Christian König <christian.koenig@amd.com>
2012-08-09radeon: simplify ZS buffer checking on r600Marek Olšák
Setting those flags has no effect anywhere else. Reviewed-by: Christian König <christian.koenig@amd.com>
2012-08-06radeon: add some new SI pci idsAlex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-08-06radeon: add some missing evergreen pci idsAlex Deucher
Noticed by: Harald van Dijk <fdo@gigawatt.nl> Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=53124 Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-06-17radeon/surface: free version after using it.Dave Airlie
fixes leak in valgrind. Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-06-12radeon: force 1D array mode for z/stencil surfaceJerome Glisse
On r6xx or evergreen z/stencil surface don't support linear or linear aligned surface, force 1D tiled mode for those. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2012-06-11radeon: enabled 2D tiling for evergreen only on fixed kernelJerome Glisse
Due to a kernel bug, enabled 2D tiling for evergreen only on newer fixed kernel. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2012-06-11radeon: always properly initialize stencil_offset fieldJerome Glisse
Reported-by: Vadim Girlin <vadimgirlin@gmail.com> Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2012-06-07radeon: fall back to 1D tiling only with broken kernelsAlex Deucher
Certain cards report the the wrong bank setup which causes surface init to fail in the ddx and leads to no accel. If we hit an invalid tiling parameter, just set a default value and disable 2D tiling. Should fix: https://bugs.freedesktop.org/show_bug.cgi?id=43448 Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-06-05radeon: add new pci idsAlex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-05-16radeon: Add Southern Islands PCI IDs.Michel Dänzer
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
2012-05-10radeon: Add new R600 PCI ids for surface managerAnisse Astier
This is the same list of PCI ids added by Alex Deucher in xf86-video-ati commit aacbd629b02cbee3f9e6a0ee452b4e3f21376bd3. This is needed since the addition of the surface allocator helper in commit c51f7f0e460dcadb9f1a56ecf1615810877c33c8 ; it needs to differentiate pre and post-R600 GPUs. Therefore we should maintain another PCI id list. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=48138 Signed-off-by: Anisse Astier <anisse@astier.eu> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-03-20radeon: add TN surface supportAlex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-02-13radeon: fix pitch alignment for scanout bufferJerome Glisse
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2012-02-08radeon_cs_setup_bo: Fix accounting if caller specified write and read domains.Michel Dänzer
Only account for the write domain in that case. Fixes https://bugs.freedesktop.org/show_bug.cgi?id=43893 . Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-02-06radeon: add r600_pci_ids.h to header fileJerome Glisse
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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