diff options
| author | Michel Dänzer <michel.daenzer@amd.com> | 2013-09-18 15:43:05 +0200 |
|---|---|---|
| committer | Michel Dänzer <michel@daenzer.net> | 2013-09-18 18:28:51 +0200 |
| commit | a48d6e5621fea701e36724cc144d9fe293332824 (patch) | |
| tree | 222fc73f71efb6686e4076b9afc243e7ec3ad520 /radeon | |
| parent | b6da447c04ea3f243b56dc964bc8d43bba003ae2 (diff) | |
radeon: Fix tiling mode index for 1D tiled depth/stencil surfaces on CIK
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'radeon')
| -rw-r--r-- | radeon/radeon_surface.c | 15 |
1 files changed, 12 insertions, 3 deletions
diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c index 818e26a9..1710e344 100644 --- a/radeon/radeon_surface.c +++ b/radeon/radeon_surface.c @@ -1382,10 +1382,16 @@ static int si_surface_sanity(struct radeon_surface_manager *surf_man, break; case RADEON_SURF_MODE_1D: if (surf->flags & RADEON_SURF_SBUFFER) { - *stencil_tile_mode = SI_TILE_MODE_DEPTH_STENCIL_1D; + if (surf_man->family >= CHIP_BONAIRE) + *stencil_tile_mode = CIK_TILE_MODE_DEPTH_STENCIL_1D; + else + *stencil_tile_mode = SI_TILE_MODE_DEPTH_STENCIL_1D; } if (surf->flags & RADEON_SURF_ZBUFFER) { - *tile_mode = SI_TILE_MODE_DEPTH_STENCIL_1D; + if (surf_man->family >= CHIP_BONAIRE) + *tile_mode = CIK_TILE_MODE_DEPTH_STENCIL_1D; + else + *tile_mode = SI_TILE_MODE_DEPTH_STENCIL_1D; } else if (surf->flags & RADEON_SURF_SCANOUT) { *tile_mode = SI_TILE_MODE_COLOR_1D_SCANOUT; } else { @@ -1643,7 +1649,10 @@ static int si_surface_init_2d(struct radeon_surface_manager *surf_man, tile_mode = SI_TILE_MODE_COLOR_1D_SCANOUT; break; case SI_TILE_MODE_DEPTH_STENCIL_2D: - tile_mode = SI_TILE_MODE_DEPTH_STENCIL_1D; + if (surf_man->family >= CHIP_BONAIRE) + tile_mode = CIK_TILE_MODE_DEPTH_STENCIL_1D; + else + tile_mode = SI_TILE_MODE_DEPTH_STENCIL_1D; break; default: return -EINVAL; |