summaryrefslogtreecommitdiff
path: root/intel
AgeCommit message (Expand)Author
2014-01-20intel: Create a new drm_intel_bo offset64 field.Kenneth Graunke
2014-01-20intel: Track whether a buffer is idle to avoid trips to the kernel.Eric Anholt
2014-01-10intel: Handle malloc fails in context createBen Widawsky
2014-01-10intel: squash unused variable 'bo_gem'Ben Widawsky
2013-12-13intel/test_decode: Allow gen8 to be infered from the batch filenamesDamien Lespiau
2013-11-26 intel: Track known prime buffers for re-useKeith Packard
2013-11-20intel: Use memset instead of VG_CLEARIan Romanick
2013-11-15intel: Add support for GPU reset status query ioctlIan Romanick
2013-11-08Revert "intel: Add support for GPU reset status query ioctl"Dave Airlie
2013-11-07intel: Add support for GPU reset status query ioctlIan Romanick
2013-11-07intel/bdw: Update MI_BATCH_BUFFER_START for aub dumpsDamien Lespiau
2013-11-07intel/bdw/aub: Update AUB trace block writes for 48-bit addressing.Kenneth Graunke
2013-11-07intel/bdw: Add gen8 to the decode initDamien Lespiau
2013-11-07intel/bdw: Handle gen8 bufmgr_initBen Widawsky
2013-11-07intel/bdw: Add broadwell chipset IDsBen Widawsky
2013-10-29intel: Add MI_LOAD_REGISTER_MEM to intel_decode.c.Kenneth Graunke
2013-10-29intel: Add the Gen6+ version of MI_REPORT_PERF_COUNT to intel_decode.c.Kenneth Graunke
2013-10-10intel: Set bo size from lseek if kernel supports itKristian Høgsberg
2013-08-30intel: Update package name and description in libdrm_intel.pcEmil Velikov
2013-07-16intel: silence valgrind warnings for unsynchronized mapsChia-I Wu
2013-06-10intel/aub: Implement a way to specify the output .aub filenameDamien Lespiau
2013-06-10intel/aub: Return early if we disable aub dumpsDamien Lespiau
2013-06-10intel/aub: Sync the AUB defines with mesa'sDamien Lespiau
2013-06-05intel: Adding more reserved PCI IDs for Haswell.Rodrigo Vivi
2013-06-05intel: Fix Haswell GT3 names.Rodrigo Vivi
2013-04-27intel: Add support for VEBOX ring (v2)Xiang, Haihao
2013-04-04intel-decode: Fix gen6 HIER_DEPTH_BUFFER decodingDaniel Vetter
2013-03-28intel: Fix Haswell CRW PCI IDs.Kenneth Graunke
2013-03-27intel_chipset: Fix up VLV confusionVille Syrjälä
2013-03-27intel_chipset: Use parens around macro argumentsVille Syrjälä
2013-02-11intel_chipset: Merge intel-gpu-tools chipsetsBen Widawsky
2013-02-06intel: fix length mask for Gen5/Gen6 3DSTATE_CLEAR_PARAMSChris Forbes
2013-02-06intel/aub: Actually run BLT batches on the blit ring.Kenneth Graunke
2013-02-02intel: add more VLV PCI IDsJesse Barnes
2013-01-13intel: Remove the fence count contributions when clearing relocsChris Wilson
2012-11-10intel: Fix missing ETIME on BSD operating systemsDavid Shao
2012-10-07intel: Silence a trivial compiler warningChris Wilson
2012-10-07intel: Correct the word decoding for gen2 3DSTATE_LOAD_STATE_IMMEDIATE_1Chris Wilson
2012-10-07intel: Fix "properly test for HAS_LLC"Chris Wilson
2012-09-14intel: Mark bo's exported to prime as not reusableKristian Høgsberg
2012-09-13intel: add support for ValleyViewJesse Barnes
2012-09-01intel: properly test for HAS_LLCDaniel Vetter
2012-08-12intel: Use VG_CLEAR on the context destroy ioctl as well.Kenneth Graunke
2012-08-10intel: Add a function for the new register read ioctl.Eric Anholt
2012-08-08intel: add more Haswell PCI IDsPaulo Zanoni
2012-08-08intel: Bail gracefully if we encounter an unknown Intel deviceChris Wilson
2012-08-02intel: Quiet valgrind warnings in context creation.Eric Anholt
2012-08-02intel: Remove two unused variablesDamien Lespiau
2012-07-20intel: fix build errorRob Clark
2012-07-20intel: add prime interface for getting/setting a prime bo. (v4)Dave Airlie