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authorRoland Scheidegger <rscheidegger_lists@hispeed.ch>2005-03-15 22:12:30 +0000
committerRoland Scheidegger <rscheidegger_lists@hispeed.ch>2005-03-15 22:12:30 +0000
commit34563921dd0b41d4ccf08374227e31d765b40353 (patch)
tree8923166e153a310096f278a5cdd743b347fcb584 /shared-core/radeon_state.c
parentd2fd9200956a94cfd91a39e76994f326bdfc6ac0 (diff)
add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear filtering on
r200
Diffstat (limited to 'shared-core/radeon_state.c')
-rw-r--r--shared-core/radeon_state.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/shared-core/radeon_state.c b/shared-core/radeon_state.c
index 1e606f3b..f6f09ac5 100644
--- a/shared-core/radeon_state.c
+++ b/shared-core/radeon_state.c
@@ -209,6 +209,7 @@ static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t *
case RADEON_EMIT_PP_CUBIC_FACES_0:
case RADEON_EMIT_PP_CUBIC_FACES_1:
case RADEON_EMIT_PP_CUBIC_FACES_2:
+ case R200_EMIT_PP_TRI_PERF_CNTL:
/* These packets don't contain memory offsets */
break;
@@ -581,7 +582,8 @@ static struct {
RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1"}, {
RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0"}, {
RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2"}, {
- RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"},
+ RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"}, {
+ R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF"},
};
/* ================================================================