From 34563921dd0b41d4ccf08374227e31d765b40353 Mon Sep 17 00:00:00 2001 From: Roland Scheidegger Date: Tue, 15 Mar 2005 22:12:30 +0000 Subject: add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear filtering on r200 --- shared-core/radeon_state.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'shared-core/radeon_state.c') diff --git a/shared-core/radeon_state.c b/shared-core/radeon_state.c index 1e606f3b..f6f09ac5 100644 --- a/shared-core/radeon_state.c +++ b/shared-core/radeon_state.c @@ -209,6 +209,7 @@ static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t * case RADEON_EMIT_PP_CUBIC_FACES_0: case RADEON_EMIT_PP_CUBIC_FACES_1: case RADEON_EMIT_PP_CUBIC_FACES_2: + case R200_EMIT_PP_TRI_PERF_CNTL: /* These packets don't contain memory offsets */ break; @@ -581,7 +582,8 @@ static struct { RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1"}, { RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0"}, { RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2"}, { - RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"}, + RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"}, { + R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF"}, }; /* ================================================================ -- cgit v1.2.3