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authorDave Airlie <airlied@linux.ie>2007-03-04 19:10:46 +1100
committerDave Airlie <airlied@linux.ie>2007-03-04 19:10:46 +1100
commit188a93c9dfde31de4d86733fa46b50487d3a4ac0 (patch)
tree9152a127172dc9947794029b141682221b2c4660 /shared-core/radeon_drv.h
parentc9178c3d01f6f38a33f9624c620d290cb9036964 (diff)
radeon: make PCI GART aperture size variable, but making table size variable
This is precursor to getting a TTM backend for this stuff, and also allows the PCI table to be allocated at fb 0
Diffstat (limited to 'shared-core/radeon_drv.h')
-rw-r--r--shared-core/radeon_drv.h4
1 files changed, 3 insertions, 1 deletions
diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index 5c426fe0..3e56af30 100644
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -95,10 +95,11 @@
* 1.24- Add general-purpose packet for manipulating scratch registers (r300)
* 1.25- Add support for r200 vertex programs (R200_EMIT_VAP_PVS_CNTL,
* new packet type)
+ * 1.26- Add support for variable size PCI(E) gart aperture
*/
#define DRIVER_MAJOR 1
-#define DRIVER_MINOR 25
+#define DRIVER_MINOR 26
#define DRIVER_PATCHLEVEL 0
/*
@@ -282,6 +283,7 @@ typedef struct drm_radeon_private {
struct radeon_virt_surface virt_surfaces[2*RADEON_MAX_SURFACES];
unsigned long pcigart_offset;
+ unsigned int pcigart_offset_set;
drm_ati_pcigart_info gart_info;
u32 scratch_ages[5];