From 188a93c9dfde31de4d86733fa46b50487d3a4ac0 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Sun, 4 Mar 2007 19:10:46 +1100 Subject: radeon: make PCI GART aperture size variable, but making table size variable This is precursor to getting a TTM backend for this stuff, and also allows the PCI table to be allocated at fb 0 --- shared-core/radeon_drv.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'shared-core/radeon_drv.h') diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h index 5c426fe0..3e56af30 100644 --- a/shared-core/radeon_drv.h +++ b/shared-core/radeon_drv.h @@ -95,10 +95,11 @@ * 1.24- Add general-purpose packet for manipulating scratch registers (r300) * 1.25- Add support for r200 vertex programs (R200_EMIT_VAP_PVS_CNTL, * new packet type) + * 1.26- Add support for variable size PCI(E) gart aperture */ #define DRIVER_MAJOR 1 -#define DRIVER_MINOR 25 +#define DRIVER_MINOR 26 #define DRIVER_PATCHLEVEL 0 /* @@ -282,6 +283,7 @@ typedef struct drm_radeon_private { struct radeon_virt_surface virt_surfaces[2*RADEON_MAX_SURFACES]; unsigned long pcigart_offset; + unsigned int pcigart_offset_set; drm_ati_pcigart_info gart_info; u32 scratch_ages[5]; -- cgit v1.2.3