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| author | Wang Zhenyu <zhenyu.z.wang@intel.com> | 2007-02-13 16:18:15 +0800 |
|---|---|---|
| committer | Wang Zhenyu <zhenyu.z.wang@intel.com> | 2007-02-13 16:18:15 +0800 |
| commit | 2a2d72623306de01e620485169721c790167d2b1 (patch) | |
| tree | 44da708c7f0a6cc39d73bd81d3106c692f734e22 /shared-core/nv30_graph.c | |
| parent | 3234b290585235e3ce7db99dfeb1714ccc1f6697 (diff) | |
| parent | 5bd13c5e15a14d34356f2363c55b1d4c7ca3269a (diff) | |
Merge branch 'master' into crestline
Diffstat (limited to 'shared-core/nv30_graph.c')
| -rw-r--r-- | shared-core/nv30_graph.c | 12 |
1 files changed, 4 insertions, 8 deletions
diff --git a/shared-core/nv30_graph.c b/shared-core/nv30_graph.c index a5f01ea5..cb183bea 100644 --- a/shared-core/nv30_graph.c +++ b/shared-core/nv30_graph.c @@ -107,10 +107,9 @@ int nv30_graph_context_create(drm_device_t *dev, int channel) struct nouveau_fifo *chan = &dev_priv->fifos[channel]; void (*ctx_init)(drm_device_t *, struct mem_block *); unsigned int ctx_size; - int i, chipset; + int i; - chipset = (NV_READ(NV_PMC_BOOT_0) & 0x0ff00000) >> 20; - switch (chipset) { + switch (dev_priv->chipset) { default: ctx_size = NV30_GRCTX_SIZE; ctx_init = nv30_graph_context_init; @@ -137,10 +136,7 @@ int nv30_graph_init(drm_device_t *dev) { drm_nouveau_private_t *dev_priv = (drm_nouveau_private_t *)dev->dev_private; - int i, chipset; - - chipset = (NV_READ(NV_PMC_BOOT_0) & 0x0ff00000) >> 20; - DRM_DEBUG("chipset (from PMC_BOOT_0): NV%02X\n", chipset); + int i; /* Create Context Pointer Table */ dev_priv->ctx_table_size = 32 * 4; @@ -151,7 +147,7 @@ int nv30_graph_init(drm_device_t *dev) for (i=0; i< dev_priv->ctx_table_size; i+=4) INSTANCE_WR(dev_priv->ctx_table, i/4, 0x00000000); - NV_WRITE(NV_PGRAPH_CHANNEL_CTX_TABLE, nouveau_chip_instance_get(dev, dev_priv->ctx_table)); + NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_TABLE, nouveau_chip_instance_get(dev, dev_priv->ctx_table)); return 0; } |