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-rw-r--r--.gitignore1
-rw-r--r--linux-core/Makefile.kernel4
-rw-r--r--linux-core/README.drm23
-rw-r--r--linux-core/drmP.h10
-rw-r--r--linux-core/drm_bo.c530
-rw-r--r--linux-core/drm_drv.c32
-rw-r--r--linux-core/drm_memory.c7
l---------linux-core/nv04_graph.c1
-rw-r--r--shared-core/drm.h3
-rw-r--r--shared-core/drm_pciids.txt26
-rw-r--r--shared-core/i915_dma.c2
-rw-r--r--shared-core/i915_drv.h7
-rw-r--r--shared-core/nouveau_drv.h9
-rw-r--r--shared-core/nouveau_fifo.c339
-rw-r--r--shared-core/nouveau_irq.c118
-rw-r--r--shared-core/nouveau_reg.h494
-rw-r--r--shared-core/nouveau_state.c8
-rw-r--r--shared-core/nv04_graph.c234
-rw-r--r--shared-core/nv10_graph.c521
-rw-r--r--shared-core/nv20_graph.c34
-rw-r--r--shared-core/nv30_graph.c12
-rw-r--r--shared-core/nv40_graph.c30
-rw-r--r--shared-core/via_dma.c134
-rw-r--r--shared-core/via_drm.h4
-rw-r--r--shared-core/via_drv.h1
-rw-r--r--tests/ttmtest/AUTHORS1
-rw-r--r--tests/ttmtest/ChangeLog23
-rw-r--r--tests/ttmtest/Makefile.am1
-rw-r--r--tests/ttmtest/NEWS0
-rw-r--r--tests/ttmtest/README0
-rw-r--r--tests/ttmtest/configure.ac33
-rwxr-xr-xtests/ttmtest/reconf2
-rw-r--r--tests/ttmtest/src/Makefile.am8
-rw-r--r--tests/ttmtest/src/ttmtest.c429
-rw-r--r--tests/ttmtest/src/xf86dri.c603
-rw-r--r--tests/ttmtest/src/xf86dri.h116
-rw-r--r--tests/ttmtest/src/xf86dristr.h390
37 files changed, 3063 insertions, 1127 deletions
diff --git a/.gitignore b/.gitignore
index d38beb78..0fb0f49f 100644
--- a/.gitignore
+++ b/.gitignore
@@ -83,6 +83,7 @@ drm_pciids.h
export_syms
i915.kld
install-sh
+libdrm/config.h.in
libdrm.pc
libtool
ltmain.sh
diff --git a/linux-core/Makefile.kernel b/linux-core/Makefile.kernel
index b531a70f..05d6e149 100644
--- a/linux-core/Makefile.kernel
+++ b/linux-core/Makefile.kernel
@@ -22,8 +22,8 @@ i830-objs := i830_drv.o i830_dma.o i830_irq.o
i915-objs := i915_drv.o i915_dma.o i915_irq.o i915_mem.o i915_fence.o \
i915_buffer.o
nouveau-objs := nouveau_drv.o nouveau_state.o nouveau_fifo.o nouveau_mem.o \
- nouveau_object.o nouveau_irq.o nv10_graph.o nv30_graph.o nv40_graph.o \
- nv20_graph.o
+ nouveau_object.o nouveau_irq.o nv04_graph.o nv10_graph.o nv20_graph.o nv30_graph.o \
+ nv40_graph.o
radeon-objs := radeon_drv.o radeon_cp.o radeon_state.o radeon_mem.o radeon_irq.o r300_cmdbuf.o
sis-objs := sis_drv.o sis_mm.o
ffb-objs := ffb_drv.o ffb_context.o
diff --git a/linux-core/README.drm b/linux-core/README.drm
index 6441e01e..7bcd6191 100644
--- a/linux-core/README.drm
+++ b/linux-core/README.drm
@@ -1,6 +1,6 @@
************************************************************
* For the very latest on DRI development, please see: *
-* http://dri.sourceforge.net/ *
+* http://dri.freedesktop.org/ *
************************************************************
The Direct Rendering Manager (drm) is a device-independent kernel-level
@@ -23,24 +23,3 @@ ways:
4. The DRM is extensible via the use of small device-specific modules
that rely extensively on the API exported by the DRM module.
-
-
-Documentation on the DRI is available from:
- http://precisioninsight.com/piinsights.html
-
-For specific information about kernel-level support, see:
-
- The Direct Rendering Manager, Kernel Support for the Direct Rendering
- Infrastructure
- http://precisioninsight.com/dr/drm.html
-
- Hardware Locking for the Direct Rendering Infrastructure
- http://precisioninsight.com/dr/locking.html
-
- A Security Analysis of the Direct Rendering Infrastructure
- http://precisioninsight.com/dr/security.html
-
-************************************************************
-* For the very latest on DRI development, please see: *
-* http://dri.sourceforge.net/ *
-************************************************************
diff --git a/linux-core/drmP.h b/linux-core/drmP.h
index af8a544d..9c748e6e 100644
--- a/linux-core/drmP.h
+++ b/linux-core/drmP.h
@@ -999,11 +999,10 @@ typedef struct drm_buffer_object{
atomic_t mapped;
uint32_t flags;
uint32_t mask;
+ uint32_t mem_type;
- drm_mm_node_t *node_ttm; /* MM node for on-card RAM */
- drm_mm_node_t *node_card; /* MM node for ttm*/
- struct list_head lru_ttm; /* LRU for the ttm pages*/
- struct list_head lru_card; /* For memory types with on-card RAM */
+ drm_mm_node_t *mm_node; /* MM node for on-card RAM */
+ struct list_head lru;
struct list_head ddestroy;
uint32_t fence_type;
@@ -1127,7 +1126,8 @@ extern void drm_query_memctl(drm_u64_t *cur_used,
drm_u64_t *low_threshold,
drm_u64_t *high_threshold);
extern void drm_init_memctl(size_t low_threshold,
- size_t high_threshold);
+ size_t high_threshold,
+ size_t unit_size);
/* Misc. IOCTL support (drm_ioctl.h) */
extern int drm_irq_by_busid(struct inode *inode, struct file *filp,
diff --git a/linux-core/drm_bo.c b/linux-core/drm_bo.c
index c0e431b4..2b960c75 100644
--- a/linux-core/drm_bo.c
+++ b/linux-core/drm_bo.c
@@ -55,6 +55,8 @@
* 2.) Refer to ttm locking orders.
*/
+static void drm_bo_destroy_locked(drm_buffer_object_t *bo);
+
#define DRM_FLAG_MASKED(_old, _new, _mask) {\
(_old) ^= (((_old) ^ (_new)) & (_mask)); \
}
@@ -64,89 +66,51 @@ static inline uint32_t drm_bo_type_flags(unsigned type)
return (1 << (24 + type));
}
-static inline drm_buffer_object_t *drm_bo_entry(struct list_head *list,
- unsigned type)
-{
- switch (type) {
- case DRM_BO_MEM_LOCAL:
- case DRM_BO_MEM_TT:
- return list_entry(list, drm_buffer_object_t, lru_ttm);
- case DRM_BO_MEM_VRAM:
- case DRM_BO_MEM_VRAM_NM:
- return list_entry(list, drm_buffer_object_t, lru_card);
- default:
- BUG_ON(1);
- }
- return NULL;
-}
-
-static inline drm_mm_node_t *drm_bo_mm_node(drm_buffer_object_t * bo,
- unsigned type)
-{
- switch (type) {
- case DRM_BO_MEM_LOCAL:
- case DRM_BO_MEM_TT:
- return bo->node_ttm;
- case DRM_BO_MEM_VRAM:
- case DRM_BO_MEM_VRAM_NM:
- return bo->node_card;
- default:
- BUG_ON(1);
- }
- return NULL;
-}
-
/*
* bo locked. dev->struct_mutex locked.
*/
-static void drm_bo_add_to_lru(drm_buffer_object_t * buf,
+static void drm_bo_add_to_lru(drm_buffer_object_t * bo,
drm_buffer_manager_t * bm)
{
struct list_head *list;
- unsigned mem_type;
-
- if (buf->flags & DRM_BO_FLAG_MEM_TT) {
- mem_type = DRM_BO_MEM_TT;
- list =
- (buf->
- flags & (DRM_BO_FLAG_NO_EVICT | DRM_BO_FLAG_NO_MOVE)) ?
- &bm->pinned[mem_type] : &bm->lru[mem_type];
- list_add_tail(&buf->lru_ttm, list);
- } else {
- mem_type = DRM_BO_MEM_LOCAL;
- list =
- (buf->
- flags & (DRM_BO_FLAG_NO_EVICT | DRM_BO_FLAG_NO_MOVE)) ?
- &bm->pinned[mem_type] : &bm->lru[mem_type];
- list_add_tail(&buf->lru_ttm, list);
- }
- if (buf->flags & DRM_BO_FLAG_MEM_VRAM) {
- mem_type = DRM_BO_MEM_VRAM;
- list =
- (buf->
- flags & (DRM_BO_FLAG_NO_EVICT | DRM_BO_FLAG_NO_MOVE)) ?
- &bm->pinned[mem_type] : &bm->lru[mem_type];
- list_add_tail(&buf->lru_card, list);
+ bo->mem_type = 0;
+
+ switch(bo->flags & DRM_BO_MASK_MEM) {
+ case DRM_BO_FLAG_MEM_TT:
+ bo->mem_type = DRM_BO_MEM_TT;
+ break;
+ case DRM_BO_FLAG_MEM_VRAM:
+ bo->mem_type = DRM_BO_MEM_VRAM;
+ break;
+ case DRM_BO_FLAG_MEM_LOCAL:
+ bo->mem_type = DRM_BO_MEM_LOCAL;
+ break;
+ default:
+ BUG_ON(1);
}
+ list = (bo->flags & (DRM_BO_FLAG_NO_EVICT | DRM_BO_FLAG_NO_MOVE)) ?
+ &bm->pinned[bo->mem_type] : &bm->lru[bo->mem_type];
+ list_add_tail(&bo->lru, list);
+ return;
}
/*
* bo locked.
*/
-static int drm_move_tt_to_local(drm_buffer_object_t * buf, int evict,
+static int drm_move_tt_to_local(drm_buffer_object_t * bo, int evict,
int force_no_move)
{
- drm_device_t *dev = buf->dev;
+ drm_device_t *dev = bo->dev;
int ret;
- if (buf->node_ttm) {
+ if (bo->mm_node) {
mutex_lock(&dev->struct_mutex);
if (evict)
- ret = drm_evict_ttm(buf->ttm);
+ ret = drm_evict_ttm(bo->ttm);
else
- ret = drm_unbind_ttm(buf->ttm);
+ ret = drm_unbind_ttm(bo->ttm);
if (ret) {
mutex_unlock(&dev->struct_mutex);
@@ -155,97 +119,19 @@ static int drm_move_tt_to_local(drm_buffer_object_t * buf, int evict,
return ret;
}
- if (!(buf->flags & DRM_BO_FLAG_NO_MOVE) || force_no_move) {
- drm_mm_put_block(buf->node_ttm);
- buf->node_ttm = NULL;
+ if (!(bo->flags & DRM_BO_FLAG_NO_MOVE) || force_no_move) {
+ drm_mm_put_block(bo->mm_node);
+ bo->mm_node = NULL;
}
mutex_unlock(&dev->struct_mutex);
}
- buf->flags &= ~DRM_BO_FLAG_MEM_TT;
- buf->flags |= DRM_BO_FLAG_MEM_LOCAL | DRM_BO_FLAG_CACHED;
+ bo->flags &= ~DRM_BO_FLAG_MEM_TT;
+ bo->flags |= DRM_BO_FLAG_MEM_LOCAL | DRM_BO_FLAG_CACHED;
return 0;
}
-/*
- * Lock dev->struct_mutex
- */
-
-static void drm_bo_destroy_locked(drm_device_t * dev, drm_buffer_object_t * bo)
-{
-
- drm_buffer_manager_t *bm = &dev->bm;
-
- DRM_FLAG_MASKED(bo->priv_flags, 0, _DRM_BO_FLAG_UNFENCED);
-
- /*
- * Somone might try to access us through the still active BM lists.
- */
-
- if (atomic_read(&bo->usage) != 0)
- return;
- if (!list_empty(&bo->ddestroy))
- return;
-
- if (bo->fence) {
- if (!drm_fence_object_signaled(bo->fence, bo->fence_type)) {
-
- drm_fence_object_flush(dev, bo->fence, bo->fence_type);
- list_add_tail(&bo->ddestroy, &bm->ddestroy);
- schedule_delayed_work(&bm->wq,
- ((DRM_HZ / 100) <
- 1) ? 1 : DRM_HZ / 100);
- return;
- } else {
- drm_fence_usage_deref_locked(dev, bo->fence);
- bo->fence = NULL;
- }
- }
- /*
- * Take away from lru lists.
- */
-
- list_del_init(&bo->lru_ttm);
- list_del_init(&bo->lru_card);
-
- if (bo->ttm) {
- unsigned long _end = jiffies + DRM_HZ;
- int ret;
-
- /*
- * This temporarily unlocks struct_mutex.
- */
-
- do {
- ret = drm_unbind_ttm(bo->ttm);
- if (ret == -EAGAIN) {
- mutex_unlock(&dev->struct_mutex);
- schedule();
- mutex_lock(&dev->struct_mutex);
- }
- } while (ret == -EAGAIN && !time_after_eq(jiffies, _end));
-
- if (ret) {
- DRM_ERROR("Couldn't unbind buffer. "
- "Bad. Continuing anyway\n");
- }
- }
-
- if (bo->node_ttm) {
- drm_mm_put_block(bo->node_ttm);
- bo->node_ttm = NULL;
- }
- if (bo->node_card) {
- drm_mm_put_block(bo->node_card);
- bo->node_card = NULL;
- }
- if (bo->ttm_object) {
- drm_ttm_object_deref_locked(dev, bo->ttm_object);
- }
- atomic_dec(&bm->count);
- drm_ctl_free(bo, sizeof(*bo), DRM_MEM_BUFOBJ);
-}
/*
* Call bo->mutex locked.
@@ -284,6 +170,136 @@ static int drm_bo_wait(drm_buffer_object_t * bo, int lazy, int ignore_signals,
/*
* Call dev->struct_mutex locked.
+ * Attempts to remove all private references to a buffer by expiring its
+ * fence object and removing from lru lists and memory managers.
+ */
+
+
+static void drm_bo_cleanup_refs(drm_buffer_object_t *bo, int remove_all)
+{
+ drm_device_t *dev = bo->dev;
+ drm_buffer_manager_t *bm = &dev->bm;
+
+ atomic_inc(&bo->usage);
+ mutex_unlock(&dev->struct_mutex);
+ mutex_lock(&bo->mutex);
+
+ DRM_FLAG_MASKED(bo->priv_flags, 0, _DRM_BO_FLAG_UNFENCED);
+
+ if (bo->fence && drm_fence_object_signaled(bo->fence,
+ bo->fence_type)) {
+ drm_fence_usage_deref_locked(dev, bo->fence);
+ bo->fence = NULL;
+ }
+
+ if (bo->fence && remove_all) {
+ if (bm->nice_mode) {
+ unsigned long _end = jiffies + 3 * DRM_HZ;
+ int ret;
+ do {
+ ret = drm_bo_wait(bo, 0, 1, 0);
+ } while (ret && !time_after_eq(jiffies, _end));
+
+ if (bo->fence) {
+ bm->nice_mode = 0;
+ DRM_ERROR("Detected GPU lockup or "
+ "fence driver was taken down. "
+ "Evicting waiting buffers.\n");
+ }
+ if (bo->fence) {
+ drm_fence_usage_deref_unlocked(dev, bo->fence);
+ bo->fence = NULL;
+ }
+ }
+ }
+ mutex_lock(&dev->struct_mutex);
+
+ if (!atomic_dec_and_test(&bo->usage)) {
+ goto out;
+ }
+
+ if (!bo->fence) {
+ list_del_init(&bo->lru);
+ if (bo->mm_node) {
+ drm_mm_put_block(bo->mm_node);
+ bo->mm_node = NULL;
+ }
+ list_del_init(&bo->ddestroy);
+ mutex_unlock(&bo->mutex);
+ drm_bo_destroy_locked(bo);
+ return;
+ }
+
+ if (list_empty(&bo->ddestroy)) {
+ drm_fence_object_flush(dev, bo->fence, bo->fence_type);
+ list_add_tail(&bo->ddestroy, &bm->ddestroy);
+ schedule_delayed_work(&bm->wq,
+ ((DRM_HZ / 100) <
+ 1) ? 1 : DRM_HZ / 100);
+ }
+
+out:
+ mutex_unlock(&bo->mutex);
+ return;
+}
+
+
+/*
+ * Verify that refcount is 0 and that there are no internal references
+ * to the buffer object. Then destroy it.
+ */
+
+static void drm_bo_destroy_locked(drm_buffer_object_t *bo)
+{
+ drm_device_t *dev = bo->dev;
+ drm_buffer_manager_t *bm = &dev->bm;
+
+ if (list_empty(&bo->lru) && bo->mm_node == NULL && atomic_read(&bo->usage) == 0) {
+ BUG_ON(bo->fence != NULL);
+
+ if (bo->ttm) {
+ unsigned long _end = jiffies + DRM_HZ;
+ int ret;
+
+ do {
+ ret = drm_unbind_ttm(bo->ttm);
+ if (ret == -EAGAIN) {
+ mutex_unlock(&dev->struct_mutex);
+ schedule();
+ mutex_lock(&dev->struct_mutex);
+ }
+ } while (ret == -EAGAIN && !time_after_eq(jiffies, _end));
+
+ if (ret) {
+ DRM_ERROR("Couldn't unbind TTM region while destroying a buffer. "
+ "Bad. Continuing anyway\n");
+ }
+ }
+
+ if (bo->ttm_object) {
+ drm_ttm_object_deref_locked(dev, bo->ttm_object);
+ }
+
+ atomic_dec(&bm->count);
+
+ drm_ctl_free(bo, sizeof(*bo), DRM_MEM_BUFOBJ);
+
+ return;
+ }
+
+ /*
+ * Some stuff is still trying to reference the buffer object.
+ * Get rid of those references.
+ */
+
+ drm_bo_cleanup_refs(bo, 0);
+
+ return;
+}
+
+
+/*
+ * Call dev->struct_mutex locked.
*/
static void drm_bo_delayed_delete(drm_device_t * dev, int remove_all)
@@ -292,15 +308,9 @@ static void drm_bo_delayed_delete(drm_device_t * dev, int remove_all)
drm_buffer_object_t *entry, *nentry;
struct list_head *list, *next;
- drm_fence_object_t *fence;
list_for_each_safe(list, next, &bm->ddestroy) {
entry = list_entry(list, drm_buffer_object_t, ddestroy);
- atomic_inc(&entry->usage);
- if (atomic_read(&entry->usage) != 1) {
- atomic_dec(&entry->usage);
- continue;
- }
nentry = NULL;
if (next != &bm->ddestroy) {
@@ -309,42 +319,8 @@ static void drm_bo_delayed_delete(drm_device_t * dev, int remove_all)
atomic_inc(&nentry->usage);
}
- mutex_unlock(&dev->struct_mutex);
- mutex_lock(&entry->mutex);
- fence = entry->fence;
- if (fence && drm_fence_object_signaled(fence,
- entry->fence_type)) {
- drm_fence_usage_deref_locked(dev, fence);
- entry->fence = NULL;
- }
-
- if (entry->fence && remove_all) {
- if (bm->nice_mode) {
- unsigned long _end = jiffies + 3 * DRM_HZ;
- int ret;
- do {
- ret = drm_bo_wait(entry, 0, 1, 0);
- } while (ret && !time_after_eq(jiffies, _end));
+ drm_bo_cleanup_refs(entry, remove_all);
- if (entry->fence) {
- bm->nice_mode = 0;
- DRM_ERROR("Detected GPU lockup or "
- "fence driver was taken down. "
- "Evicting waiting buffers.\n");
- }
- }
- if (entry->fence) {
- drm_fence_usage_deref_unlocked(dev,
- entry->fence);
- entry->fence = NULL;
- }
- }
- mutex_lock(&dev->struct_mutex);
- mutex_unlock(&entry->mutex);
- if (atomic_dec_and_test(&entry->usage) && (!entry->fence)) {
- list_del_init(&entry->ddestroy);
- drm_bo_destroy_locked(dev, entry);
- }
if (nentry) {
atomic_dec(&nentry->usage);
}
@@ -382,26 +358,27 @@ static void drm_bo_delayed_workqueue(struct work_struct *work)
mutex_unlock(&dev->struct_mutex);
}
-void drm_bo_usage_deref_locked(drm_device_t * dev, drm_buffer_object_t * bo)
+static void drm_bo_usage_deref_locked(drm_buffer_object_t * bo)
{
if (atomic_dec_and_test(&bo->usage)) {
- drm_bo_destroy_locked(dev, bo);
+ drm_bo_destroy_locked(bo);
}
}
static void drm_bo_base_deref_locked(drm_file_t * priv, drm_user_object_t * uo)
{
- drm_bo_usage_deref_locked(priv->head->dev,
- drm_user_object_entry(uo, drm_buffer_object_t,
+ drm_bo_usage_deref_locked(drm_user_object_entry(uo, drm_buffer_object_t,
base));
}
-void drm_bo_usage_deref_unlocked(drm_device_t * dev, drm_buffer_object_t * bo)
+static void drm_bo_usage_deref_unlocked(drm_buffer_object_t * bo)
{
+ drm_device_t *dev = bo->dev;
+
if (atomic_dec_and_test(&bo->usage)) {
mutex_lock(&dev->struct_mutex);
if (atomic_read(&bo->usage) == 0)
- drm_bo_destroy_locked(dev, bo);
+ drm_bo_destroy_locked(bo);
mutex_unlock(&dev->struct_mutex);
}
}
@@ -424,14 +401,15 @@ int drm_fence_buffer_objects(drm_file_t * priv,
uint32_t fence_type = 0;
int count = 0;
int ret = 0;
- struct list_head f_list, *l;
+ struct list_head *l;
+ LIST_HEAD(f_list);
mutex_lock(&dev->struct_mutex);
if (!list)
list = &bm->unfenced;
- list_for_each_entry(entry, list, lru_ttm) {
+ list_for_each_entry(entry, list, lru) {
BUG_ON(!(entry->priv_flags & _DRM_BO_FLAG_UNFENCED));
fence_type |= entry->fence_type;
if (entry->fence_class != 0) {
@@ -454,8 +432,7 @@ int drm_fence_buffer_objects(drm_file_t * priv,
* the ones we already have..
*/
- list_add_tail(&f_list, list);
- list_del_init(list);
+ list_splice_init(list, &f_list);
if (fence) {
if ((fence_type & fence->type) != fence_type) {
@@ -477,13 +454,12 @@ int drm_fence_buffer_objects(drm_file_t * priv,
count = 0;
l = f_list.next;
while (l != &f_list) {
- entry = list_entry(l, drm_buffer_object_t, lru_ttm);
+ entry = list_entry(l, drm_buffer_object_t, lru);
atomic_inc(&entry->usage);
mutex_unlock(&dev->struct_mutex);
mutex_lock(&entry->mutex);
mutex_lock(&dev->struct_mutex);
list_del_init(l);
- list_del_init(&entry->lru_card);
if (entry->priv_flags & _DRM_BO_FLAG_UNFENCED) {
count++;
if (entry->fence)
@@ -495,7 +471,7 @@ int drm_fence_buffer_objects(drm_file_t * priv,
drm_bo_add_to_lru(entry, bm);
}
mutex_unlock(&entry->mutex);
- drm_bo_usage_deref_locked(dev, entry);
+ drm_bo_usage_deref_locked(entry);
l = f_list.next;
}
atomic_add(count, &fence->usage);
@@ -542,18 +518,11 @@ static int drm_bo_evict(drm_buffer_object_t * bo, unsigned mem_type,
if (ret)
goto out;
mutex_lock(&dev->struct_mutex);
- list_del_init(&bo->lru_ttm);
+ list_del_init(&bo->lru);
drm_bo_add_to_lru(bo, bm);
mutex_unlock(&dev->struct_mutex);
}
-#if 0
- else {
- ret = drm_move_vram_to_local(bo);
- mutex_lock(&dev->struct_mutex);
- list_del_init(&bo->lru_card);
- mutex_unlock(&dev->struct_mutex);
- }
-#endif
+
if (ret)
goto out;
@@ -564,24 +533,24 @@ static int drm_bo_evict(drm_buffer_object_t * bo, unsigned mem_type,
}
/*
- * buf->mutex locked.
+ * bo->mutex locked.
*/
-int drm_bo_alloc_space(drm_buffer_object_t * buf, unsigned mem_type,
+int drm_bo_alloc_space(drm_buffer_object_t * bo, unsigned mem_type,
int no_wait)
{
- drm_device_t *dev = buf->dev;
+ drm_device_t *dev = bo->dev;
drm_mm_node_t *node;
drm_buffer_manager_t *bm = &dev->bm;
- drm_buffer_object_t *bo;
+ drm_buffer_object_t *entry;
drm_mm_t *mm = &bm->manager[mem_type];
struct list_head *lru;
- unsigned long size = buf->num_pages;
+ unsigned long size = bo->num_pages;
int ret;
mutex_lock(&dev->struct_mutex);
do {
- node = drm_mm_search_free(mm, size, buf->page_alignment, 1);
+ node = drm_mm_search_free(mm, size, bo->page_alignment, 1);
if (node)
break;
@@ -589,15 +558,15 @@ int drm_bo_alloc_space(drm_buffer_object_t * buf, unsigned mem_type,
if (lru->next == lru)
break;
- bo = drm_bo_entry(lru->next, mem_type);
+ entry = list_entry(lru->next, drm_buffer_object_t, lru);
- atomic_inc(&bo->usage);
+ atomic_inc(&entry->usage);
mutex_unlock(&dev->struct_mutex);
- mutex_lock(&bo->mutex);
+ mutex_lock(&entry->mutex);
BUG_ON(bo->flags & DRM_BO_FLAG_NO_MOVE);
- ret = drm_bo_evict(bo, mem_type, no_wait, 0);
- mutex_unlock(&bo->mutex);
- drm_bo_usage_deref_unlocked(dev, bo);
+ ret = drm_bo_evict(entry, mem_type, no_wait, 0);
+ mutex_unlock(&entry->mutex);
+ drm_bo_usage_deref_unlocked(entry);
if (ret)
return ret;
mutex_lock(&dev->struct_mutex);
@@ -609,17 +578,13 @@ int drm_bo_alloc_space(drm_buffer_object_t * buf, unsigned mem_type,
return -ENOMEM;
}
- node = drm_mm_get_block(node, size, buf->page_alignment);
+ node = drm_mm_get_block(node, size, bo->page_alignment);
mutex_unlock(&dev->struct_mutex);
BUG_ON(!node);
- node->private = (void *)buf;
+ node->private = (void *)bo;
- if (mem_type == DRM_BO_MEM_TT) {
- buf->node_ttm = node;
- } else {
- buf->node_card = node;
- }
- buf->offset = node->start * PAGE_SIZE;
+ bo->mm_node = node;
+ bo->offset = node->start * PAGE_SIZE;
return 0;
}
@@ -629,21 +594,21 @@ static int drm_move_local_to_tt(drm_buffer_object_t * bo, int no_wait)
drm_ttm_backend_t *be;
int ret;
- if (!(bo->node_ttm && (bo->flags & DRM_BO_FLAG_NO_MOVE))) {
- BUG_ON(bo->node_ttm);
+ if (!(bo->mm_node && (bo->flags & DRM_BO_FLAG_NO_MOVE))) {
+ BUG_ON(bo->mm_node);
ret = drm_bo_alloc_space(bo, DRM_BO_MEM_TT, no_wait);
if (ret)
return ret;
}
- DRM_DEBUG("Flipping in to AGP 0x%08lx\n", bo->node_ttm->start);
+ DRM_DEBUG("Flipping in to AGP 0x%08lx\n", bo->mm_node->start);
mutex_lock(&dev->struct_mutex);
ret = drm_bind_ttm(bo->ttm, bo->flags & DRM_BO_FLAG_BIND_CACHED,
- bo->node_ttm->start);
+ bo->mm_node->start);
if (ret) {
- drm_mm_put_block(bo->node_ttm);
- bo->node_ttm = NULL;
+ drm_mm_put_block(bo->mm_node);
+ bo->mm_node = NULL;
}
mutex_unlock(&dev->struct_mutex);
@@ -860,11 +825,7 @@ static int drm_bo_read_cached(drm_buffer_object_t * bo)
int ret = 0;
BUG_ON(bo->priv_flags & _DRM_BO_FLAG_UNFENCED);
- if (bo->node_card)
- ret = drm_bo_evict(bo, DRM_BO_MEM_VRAM, 1, 0);
- if (ret)
- return ret;
- if (bo->node_ttm)
+ if (bo->mm_node)
ret = drm_bo_evict(bo, DRM_BO_MEM_TT, 1, 0);
return ret;
}
@@ -1061,7 +1022,7 @@ static int drm_buffer_object_map(drm_file_t * priv, uint32_t handle,
drm_bo_fill_rep_arg(bo, rep);
out:
mutex_unlock(&bo->mutex);
- drm_bo_usage_deref_unlocked(dev, bo);
+ drm_bo_usage_deref_unlocked(bo);
return ret;
}
@@ -1087,7 +1048,7 @@ static int drm_buffer_object_unmap(drm_file_t * priv, uint32_t handle)
}
drm_remove_ref_object(priv, ro);
- drm_bo_usage_deref_locked(dev, bo);
+ drm_bo_usage_deref_locked(bo);
out:
mutex_unlock(&dev->struct_mutex);
return ret;
@@ -1215,13 +1176,9 @@ static int drm_buffer_object_validate(drm_buffer_object_t * bo,
if ((flag_diff & DRM_BO_FLAG_NO_MOVE) &&
!(new_flags & DRM_BO_FLAG_NO_MOVE)) {
mutex_lock(&dev->struct_mutex);
- if (bo->node_ttm) {
- drm_mm_put_block(bo->node_ttm);
- bo->node_ttm = NULL;
- }
- if (bo->node_card) {
- drm_mm_put_block(bo->node_card);
- bo->node_card = NULL;
+ if (bo->mm_node) {
+ drm_mm_put_block(bo->mm_node);
+ bo->mm_node = NULL;
}
mutex_unlock(&dev->struct_mutex);
}
@@ -1248,15 +1205,13 @@ static int drm_buffer_object_validate(drm_buffer_object_t * bo,
DRM_FLAG_MASKED(bo->priv_flags, _DRM_BO_FLAG_UNFENCED,
_DRM_BO_FLAG_UNFENCED);
mutex_lock(&dev->struct_mutex);
- list_del(&bo->lru_ttm);
- list_add_tail(&bo->lru_ttm, &bm->unfenced);
- list_del_init(&bo->lru_card);
+ list_del(&bo->lru);
+ list_add_tail(&bo->lru, &bm->unfenced);
mutex_unlock(&dev->struct_mutex);
} else {
mutex_lock(&dev->struct_mutex);
- list_del_init(&bo->lru_ttm);
- list_del_init(&bo->lru_card);
+ list_del_init(&bo->lru);
drm_bo_add_to_lru(bo, bm);
mutex_unlock(&dev->struct_mutex);
}
@@ -1302,7 +1257,7 @@ static int drm_bo_handle_validate(drm_file_t * priv, uint32_t handle,
out:
mutex_unlock(&bo->mutex);
- drm_bo_usage_deref_unlocked(dev, bo);
+ drm_bo_usage_deref_unlocked(bo);
return ret;
}
@@ -1320,7 +1275,7 @@ static int drm_bo_handle_info(drm_file_t * priv, uint32_t handle,
(void)drm_bo_busy(bo);
drm_bo_fill_rep_arg(bo, rep);
mutex_unlock(&bo->mutex);
- drm_bo_usage_deref_unlocked(bo->dev, bo);
+ drm_bo_usage_deref_unlocked(bo);
return 0;
}
@@ -1348,7 +1303,7 @@ static int drm_bo_handle_wait(drm_file_t * priv, uint32_t handle,
out:
mutex_unlock(&bo->mutex);
- drm_bo_usage_deref_unlocked(bo->dev, bo);
+ drm_bo_usage_deref_unlocked(bo);
return ret;
}
@@ -1393,6 +1348,49 @@ static int drm_bo_add_ttm(drm_file_t * priv, drm_buffer_object_t * bo)
return ret;
}
+/*
+ * Transfer a buffer object's memory and LRU status to a newly
+ * created object. User-space references remains with the old
+ * object. Call bo->mutex locked.
+ */
+
+int drm_buffer_object_transfer(drm_buffer_object_t *bo,
+ drm_buffer_object_t **new_obj)
+{
+ drm_buffer_object_t *fbo;
+ drm_device_t *dev = bo->dev;
+ drm_buffer_manager_t *bm = &dev->bm;
+
+ fbo = drm_ctl_calloc(1, sizeof(*bo), DRM_MEM_BUFOBJ);
+ if (!fbo)
+ return -ENOMEM;
+
+ *fbo = *bo;
+ mutex_init(&fbo->mutex);
+ mutex_lock(&fbo->mutex);
+ mutex_lock(&dev->struct_mutex);
+
+ INIT_LIST_HEAD(&fbo->ddestroy);
+ INIT_LIST_HEAD(&fbo->lru);
+ list_splice_init(&bo->lru, &fbo->lru);
+
+ bo->mm_node = NULL;
+ bo->ttm = NULL;
+ bo->ttm_object = NULL;
+ bo->fence = NULL;
+ bo->flags = 0;
+
+ fbo->mm_node->private = (void *)fbo;
+ atomic_set(&fbo->usage, 1);
+ atomic_inc(&bm->count);
+ mutex_unlock(&dev->struct_mutex);
+ mutex_unlock(&fbo->mutex);
+
+ *new_obj = fbo;
+ return 0;
+}
+
+
int drm_buffer_object_create(drm_file_t * priv,
unsigned long size,
drm_bo_type_t type,
@@ -1430,14 +1428,12 @@ int drm_buffer_object_create(drm_file_t * priv,
atomic_set(&bo->usage, 1);
atomic_set(&bo->mapped, -1);
DRM_INIT_WAITQUEUE(&bo->event_queue);
- INIT_LIST_HEAD(&bo->lru_ttm);
- INIT_LIST_HEAD(&bo->lru_card);
+ INIT_LIST_HEAD(&bo->lru);
INIT_LIST_HEAD(&bo->ddestroy);
bo->dev = dev;
bo->type = type;
bo->num_pages = num_pages;
- bo->node_card = NULL;
- bo->node_ttm = NULL;
+ bo->mm_node = NULL;
bo->page_alignment = page_alignment;
if (bo->type == drm_bo_type_fake) {
bo->offset = buffer_start;
@@ -1467,7 +1463,7 @@ int drm_buffer_object_create(drm_file_t * priv,
out_err:
mutex_unlock(&bo->mutex);
- drm_bo_usage_deref_unlocked(dev, bo);
+ drm_bo_usage_deref_unlocked(bo);
return ret;
}
@@ -1540,7 +1536,7 @@ int drm_bo_ioctl(DRM_IOCTL_ARGS)
mask &
DRM_BO_FLAG_SHAREABLE);
if (rep.ret)
- drm_bo_usage_deref_unlocked(dev, entry);
+ drm_bo_usage_deref_unlocked(entry);
if (rep.ret)
break;
@@ -1653,7 +1649,7 @@ static int drm_bo_force_list_clean(drm_device_t * dev,
clean = 1;
list_for_each_safe(list, next, head) {
prev = list->prev;
- entry = drm_bo_entry(list, mem_type);
+ entry = list_entry(list, drm_buffer_object_t, lru);
atomic_inc(&entry->usage);
mutex_unlock(&dev->struct_mutex);
mutex_lock(&entry->mutex);
@@ -1661,10 +1657,10 @@ static int drm_bo_force_list_clean(drm_device_t * dev,
if (prev != list->prev || next != list->next) {
mutex_unlock(&entry->mutex);
- drm_bo_usage_deref_locked(dev, entry);
+ drm_bo_usage_deref_locked(entry);
goto retry;
}
- if (drm_bo_mm_node(entry, mem_type)) {
+ if (entry->mm_node) {
clean = 0;
/*
@@ -1721,7 +1717,7 @@ static int drm_bo_force_list_clean(drm_device_t * dev,
mutex_lock(&dev->struct_mutex);
}
mutex_unlock(&entry->mutex);
- drm_bo_usage_deref_locked(dev, entry);
+ drm_bo_usage_deref_locked(entry);
if (prev != list->prev || next != list->next) {
goto retry;
}
@@ -1731,7 +1727,7 @@ static int drm_bo_force_list_clean(drm_device_t * dev,
return 0;
out_err:
mutex_unlock(&entry->mutex);
- drm_bo_usage_deref_unlocked(dev, entry);
+ drm_bo_usage_deref_unlocked(entry);
mutex_lock(&dev->struct_mutex);
return ret;
}
diff --git a/linux-core/drm_drv.c b/linux-core/drm_drv.c
index 45f563ff..ff9b29e7 100644
--- a/linux-core/drm_drv.c
+++ b/linux-core/drm_drv.c
@@ -148,10 +148,11 @@ int drm_lastclose(drm_device_t * dev)
DRM_DEBUG("\n");
- if (drm_bo_driver_finish(dev)) {
- DRM_ERROR("DRM memory manager still busy. "
- "System is unstable. Please reboot.\n");
- }
+ /*
+ * We can't do much about this function failing.
+ */
+
+ drm_bo_driver_finish(dev);
if (dev->driver->lastclose)
dev->driver->lastclose(dev);
@@ -450,9 +451,28 @@ static int __init drm_core_init(void)
{
int ret;
struct sysinfo si;
-
+ unsigned long avail_memctl_mem;
+ unsigned long max_memctl_mem;
+
si_meminfo(&si);
- drm_init_memctl(si.totalram/2, si.totalram*3/4);
+
+ /*
+ * AGP only allows low / DMA32 memory ATM.
+ */
+
+ avail_memctl_mem = si.totalram - si.totalhigh;
+
+ /*
+ * Avoid overflows
+ */
+
+ max_memctl_mem = 1UL << (32 - PAGE_SHIFT);
+ max_memctl_mem = (max_memctl_mem / si.mem_unit) * PAGE_SIZE;
+
+ if (avail_memctl_mem >= max_memctl_mem)
+ avail_memctl_mem = max_memctl_mem;
+
+ drm_init_memctl(avail_memctl_mem/2, avail_memctl_mem*3/4, si.mem_unit);
ret = -ENOMEM;
drm_cards_limit =
diff --git a/linux-core/drm_memory.c b/linux-core/drm_memory.c
index 62f54b67..9a53fa82 100644
--- a/linux-core/drm_memory.c
+++ b/linux-core/drm_memory.c
@@ -95,12 +95,13 @@ void drm_query_memctl(drm_u64_t *cur_used,
EXPORT_SYMBOL(drm_query_memctl);
void drm_init_memctl(size_t p_low_threshold,
- size_t p_high_threshold)
+ size_t p_high_threshold,
+ size_t unit_size)
{
spin_lock(&drm_memctl.lock);
drm_memctl.cur_used = 0;
- drm_memctl.low_threshold = p_low_threshold << PAGE_SHIFT;
- drm_memctl.high_threshold = p_high_threshold << PAGE_SHIFT;
+ drm_memctl.low_threshold = p_low_threshold * unit_size;
+ drm_memctl.high_threshold = p_high_threshold * unit_size;
spin_unlock(&drm_memctl.lock);
}
diff --git a/linux-core/nv04_graph.c b/linux-core/nv04_graph.c
new file mode 120000
index 00000000..0d7a0b35
--- /dev/null
+++ b/linux-core/nv04_graph.c
@@ -0,0 +1 @@
+../shared-core/nv04_graph.c \ No newline at end of file
diff --git a/shared-core/drm.h b/shared-core/drm.h
index 9efb1dc4..0e3b9b89 100644
--- a/shared-core/drm.h
+++ b/shared-core/drm.h
@@ -61,6 +61,9 @@
#ifndef __user
#define __user
#endif
+#ifndef __iomem
+#define __iomem
+#endif
#ifdef __GNUC__
# define DEPRECATED __attribute__ ((deprecated))
diff --git a/shared-core/drm_pciids.txt b/shared-core/drm_pciids.txt
index 0d2639e1..0fc9775b 100644
--- a/shared-core/drm_pciids.txt
+++ b/shared-core/drm_pciids.txt
@@ -186,7 +186,7 @@
0x1002 0x4c51 0 "3D Rage LT Pro"
0x1002 0x4c42 0 "3D Rage LT Pro AGP-133"
0x1002 0x4c44 0 "3D Rage LT Pro AGP-66"
-0x1002 0x4759 0 "Rage 3D IICATI 3D RAGE IIC AGP(A12/A13)
+0x1002 0x4759 0 "Rage 3D IICATI 3D RAGE IIC AGP(A12/A13)"
0x1002 0x474c 0 "Rage XC"
0x1002 0x474f 0 "Rage XL"
0x1002 0x4752 0 "Rage XL"
@@ -266,18 +266,18 @@
[ffb]
[i915]
-0x8086 0x3577 0 "Intel i830M GMCH"
-0x8086 0x2562 0 "Intel i845G GMCH"
-0x8086 0x3582 0 "Intel i852GM/i855GM GMCH"
-0x8086 0x2572 0 "Intel i865G GMCH"
-0x8086 0x2582 0 "Intel i915G"
-0x8086 0x2592 0 "Intel i915GM"
-0x8086 0x2772 0 "Intel i945G"
-0x8086 0x27A2 0 "Intel i945GM"
-0x8086 0x2972 0 "Intel i946GZ"
-0x8086 0x2982 0 "Intel i965G"
-0x8086 0x2992 0 "Intel i965Q"
-0x8086 0x29A2 0 "Intel i965G"
+0x8086 0x3577 CHIP_I8XX "Intel i830M GMCH"
+0x8086 0x2562 CHIP_I8XX "Intel i845G GMCH"
+0x8086 0x3582 CHIP_I8XX "Intel i852GM/i855GM GMCH"
+0x8086 0x2572 CHIP_I8XX "Intel i865G GMCH"
+0x8086 0x2582 CHIP_I9XX|CHIP_I915 "Intel i915G"
+0x8086 0x2592 CHIP_I9XX|CHIP_I915 "Intel i915GM"
+0x8086 0x2772 CHIP_I9XX|CHIP_I915 "Intel i945G"
+0x8086 0x27A2 CHIP_I9XX|CHIP_I915 "Intel i945GM"
+0x8086 0x2972 CHIP_I9XX|CHIP_I965 "Intel i946GZ"
+0x8086 0x2982 CHIP_I9XX|CHIP_I965 "Intel i965G"
+0x8086 0x2992 CHIP_I9XX|CHIP_I965 "Intel i965Q"
+0x8086 0x29A2 CHIP_I9XX|CHIP_I965 "Intel i965G"
[imagine]
0x105d 0x2309 IMAGINE_128 "Imagine 128"
diff --git a/shared-core/i915_dma.c b/shared-core/i915_dma.c
index 912fe0b1..9624fac4 100644
--- a/shared-core/i915_dma.c
+++ b/shared-core/i915_dma.c
@@ -798,7 +798,7 @@ static int i915_mmio(DRM_IOCTL_ARGS)
DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
return DRM_ERR(EINVAL);
}
- DRM_COPY_FROM_USER_IOCTL(mmio, (drm_i915_setparam_t __user *) data,
+ DRM_COPY_FROM_USER_IOCTL(mmio, (drm_i915_mmio_t __user *) data,
sizeof(mmio));
if (mmio.reg >= mmio_table_size)
diff --git a/shared-core/i915_drv.h b/shared-core/i915_drv.h
index ef9f3638..5a76cb15 100644
--- a/shared-core/i915_drv.h
+++ b/shared-core/i915_drv.h
@@ -132,6 +132,13 @@ typedef struct drm_i915_private {
unsigned int swaps_pending;
} drm_i915_private_t;
+enum intel_chip_family {
+ CHIP_I8XX = 0x01,
+ CHIP_I9XX = 0x02,
+ CHIP_I915 = 0x04,
+ CHIP_I965 = 0x08,
+};
+
extern drm_ioctl_desc_t i915_ioctls[];
extern int i915_max_ioctl;
diff --git a/shared-core/nouveau_drv.h b/shared-core/nouveau_drv.h
index 522a8cf9..63721650 100644
--- a/shared-core/nouveau_drv.h
+++ b/shared-core/nouveau_drv.h
@@ -91,7 +91,7 @@ struct nouveau_fifo
struct nouveau_object *objs;
/* XXX dynamic alloc ? */
- uint32_t nv10_pgraph_ctx [340];
+ uint32_t pgraph_ctx [340];
};
struct nouveau_config {
@@ -104,6 +104,8 @@ struct nouveau_config {
typedef struct drm_nouveau_private {
/* the card type, takes NV_* as values */
int card_type;
+ /* exact chipset, derived from NV_PMC_BOOT_0 */
+ int chipset;
int flags;
drm_local_map_t *mmio;
@@ -202,6 +204,11 @@ extern void nouveau_irq_preinstall(drm_device_t*);
extern void nouveau_irq_postinstall(drm_device_t*);
extern void nouveau_irq_uninstall(drm_device_t*);
+/* nv04_graph.c */
+extern void nouveau_nv04_context_switch(drm_device_t *dev);
+extern int nv04_graph_init(drm_device_t *dev);
+extern int nv04_graph_context_create(drm_device_t *dev, int channel);
+
/* nv10_graph.c */
extern void nouveau_nv10_context_switch(drm_device_t *dev);
extern int nv10_graph_init(drm_device_t *dev);
diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c
index e80ba766..7f929c5c 100644
--- a/shared-core/nouveau_fifo.c
+++ b/shared-core/nouveau_fifo.c
@@ -82,7 +82,7 @@ static int nouveau_fifo_instmem_configure(drm_device_t *dev)
dev_priv->ramht_offset = 0x10000;
dev_priv->ramht_bits = 9;
dev_priv->ramht_size = (1 << dev_priv->ramht_bits);
- NV_WRITE(NV_PFIFO_RAMHT,
+ NV_WRITE(NV03_PFIFO_RAMHT,
(0x03 << 24) /* search 128 */ |
((dev_priv->ramht_bits - 9) << 16) |
(dev_priv->ramht_offset >> 8)
@@ -94,7 +94,7 @@ static int nouveau_fifo_instmem_configure(drm_device_t *dev)
/* FIFO runout table (RAMRO) - 512k at 0x11200 */
dev_priv->ramro_offset = 0x11200;
dev_priv->ramro_size = 512;
- NV_WRITE(NV_PFIFO_RAMRO, dev_priv->ramro_offset>>8);
+ NV_WRITE(NV03_PFIFO_RAMRO, dev_priv->ramro_offset>>8);
DRM_DEBUG("RAMRO offset=0x%x, size=%d\n",
dev_priv->ramro_offset,
dev_priv->ramro_size);
@@ -124,14 +124,14 @@ static int nouveau_fifo_instmem_configure(drm_device_t *dev)
case NV_10:
dev_priv->ramfc_offset = 0x11400;
dev_priv->ramfc_size = nouveau_fifo_number(dev) * nouveau_fifo_ctx_size(dev);
- NV_WRITE(NV_PFIFO_RAMFC, (dev_priv->ramfc_offset>>8) |
+ NV_WRITE(NV03_PFIFO_RAMFC, (dev_priv->ramfc_offset>>8) |
(1 << 16) /* 64 Bytes entry*/);
break;
case NV_04:
case NV_03:
dev_priv->ramfc_offset = 0x11400;
dev_priv->ramfc_size = nouveau_fifo_number(dev) * nouveau_fifo_ctx_size(dev);
- NV_WRITE(NV_PFIFO_RAMFC, dev_priv->ramfc_offset>>8);
+ NV_WRITE(NV03_PFIFO_RAMFC, dev_priv->ramfc_offset>>8);
break;
}
DRM_DEBUG("RAMFC offset=0x%x, size=%d\n",
@@ -150,7 +150,7 @@ int nouveau_fifo_init(drm_device_t *dev)
drm_nouveau_private_t *dev_priv = dev->dev_private;
int ret;
- NV_WRITE(NV_PFIFO_CACHES, 0x00000000);
+ NV_WRITE(NV03_PFIFO_CACHES, 0x00000000);
ret = nouveau_fifo_instmem_configure(dev);
if (ret) {
@@ -163,50 +163,55 @@ int nouveau_fifo_init(drm_device_t *dev)
DRM_DEBUG("Setting defaults for remaining PFIFO regs\n");
/* All channels into PIO mode */
- NV_WRITE(NV_PFIFO_MODE, 0x00000000);
+ NV_WRITE(NV04_PFIFO_MODE, 0x00000000);
- NV_WRITE(NV_PFIFO_CACH1_PSH0, 0x00000000);
- NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000000);
+ NV_WRITE(NV03_PFIFO_CACHE1_PUSH0, 0x00000000);
+ NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000000);
/* Channel 0 active, PIO mode */
- NV_WRITE(NV_PFIFO_CACH1_PSH1, 0x00000000);
+ NV_WRITE(NV03_PFIFO_CACHE1_PUSH1, 0x00000000);
/* PUT and GET to 0 */
- NV_WRITE(NV_PFIFO_CACH1_DMAP, 0x00000000);
- NV_WRITE(NV_PFIFO_CACH1_DMAP, 0x00000000);
+ NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUT, 0x00000000);
+ NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUT, 0x00000000);
/* No cmdbuf object */
- NV_WRITE(NV_PFIFO_CACH1_DMAI, 0x00000000);
- NV_WRITE(NV_PFIFO_CACH0_PSH0, 0x00000000);
- NV_WRITE(NV_PFIFO_CACH0_PUL0, 0x00000000);
- NV_WRITE(NV_PFIFO_SIZE, 0x0000FFFF);
- NV_WRITE(NV_PFIFO_CACH1_HASH, 0x0000FFFF);
- NV_WRITE(NV_PFIFO_CACH0_PUL1, 0x00000001);
- NV_WRITE(NV_PFIFO_CACH1_DMAC, 0x00000000);
- NV_WRITE(NV_PFIFO_CACH1_DMAS, 0x00000000);
- NV_WRITE(NV_PFIFO_CACH1_ENG, 0x00000000);
+ NV_WRITE(NV04_PFIFO_CACHE1_DMA_INSTANCE, 0x00000000);
+ NV_WRITE(NV03_PFIFO_CACHE0_PUSH0, 0x00000000);
+ NV_WRITE(NV03_PFIFO_CACHE0_PULL0, 0x00000000);
+ NV_WRITE(NV04_PFIFO_SIZE, 0x0000FFFF);
+ NV_WRITE(NV04_PFIFO_CACHE1_HASH, 0x0000FFFF);
+ NV_WRITE(NV04_PFIFO_CACHE0_PULL1, 0x00000001);
+ NV_WRITE(NV04_PFIFO_CACHE1_DMA_CTL, 0x00000000);
+ NV_WRITE(NV04_PFIFO_CACHE1_DMA_STATE, 0x00000000);
+ NV_WRITE(NV04_PFIFO_CACHE1_ENGINE, 0x00000000);
+
+ NV_WRITE(NV04_PFIFO_CACHE1_DMA_FETCH, NV_PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES |
+ NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
+ NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4 |
#ifdef __BIG_ENDIAN
- NV_WRITE(NV_PFIFO_CACH1_DMAF, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES |
- NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES |
- NV_PFIFO_CACH1_DMAF_MAX_REQS_4 |
- NV_PFIFO_CACH1_BIG_ENDIAN);
-#else
- NV_WRITE(NV_PFIFO_CACH1_DMAF, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES |
- NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES |
- NV_PFIFO_CACH1_DMAF_MAX_REQS_4);
-#endif
- NV_WRITE(NV_PFIFO_CACH1_DMAPSH, 0x00000001);
- NV_WRITE(NV_PFIFO_CACH1_PSH0, 0x00000001);
- NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000001);
- NV_WRITE(NV_PFIFO_CACH1_PUL1, 0x00000001);
-
- NV_WRITE(NV_PGRAPH_CTX_USER, 0x0);
- NV_WRITE(NV_PFIFO_DELAY_0, 0xff /* retrycount*/ );
- if (dev_priv->card_type >= NV_40)
- NV_WRITE(NV_PGRAPH_CTX_CONTROL, 0x00002001);
- else
- NV_WRITE(NV_PGRAPH_CTX_CONTROL, 0x10110000);
-
- NV_WRITE(NV_PFIFO_DMA_TIMESLICE, 0x001fffff);
- NV_WRITE(NV_PFIFO_CACHES, 0x00000001);
+ NV_PFIFO_CACH1_BIG_ENDIAN |
+#endif
+ 0x00000000);
+
+ NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUSH, 0x00000001);
+ NV_WRITE(NV03_PFIFO_CACHE1_PUSH0, 0x00000001);
+ NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000001);
+ NV_WRITE(NV04_PFIFO_CACHE1_PULL1, 0x00000001);
+
+ /* FIXME on NV04 */
+ if (dev_priv->card_type >= NV_10) {
+ NV_WRITE(NV10_PGRAPH_CTX_USER, 0x0);
+ NV_WRITE(NV04_PFIFO_DELAY_0, 0xff /* retrycount*/ );
+ if (dev_priv->card_type >= NV_40)
+ NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x00002001);
+ else
+ NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10110000);
+ } else {
+ NV_WRITE(NV04_PGRAPH_CTX_USER, 0x0);
+ NV_WRITE(NV04_PFIFO_DELAY_0, 0xff /* retrycount*/ );
+ NV_WRITE(NV04_PGRAPH_CTX_CONTROL, 0x10110000);
+ }
+ NV_WRITE(NV04_PFIFO_DMA_TIMESLICE, 0x001fffff);
+ NV_WRITE(NV03_PFIFO_CACHES, 0x00000001);
return 0;
}
@@ -283,16 +288,14 @@ static void nouveau_nv04_context_init(drm_device_t *dev,
RAMFC_WR(DMA_PUT , init->put_base);
RAMFC_WR(DMA_GET , init->put_base);
RAMFC_WR(DMA_INSTANCE , nouveau_chip_instance_get(dev, cb_obj->instance));
+
+ RAMFC_WR(DMA_FETCH, NV_PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES |
+ NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
+ NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4 |
#ifdef __BIG_ENDIAN
- RAMFC_WR(DMA_FETCH, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES |
- NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES |
- NV_PFIFO_CACH1_DMAF_MAX_REQS_4 |
- NV_PFIFO_CACH1_BIG_ENDIAN);
-#else
- RAMFC_WR(DMA_FETCH, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES |
- NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES |
- NV_PFIFO_CACH1_DMAF_MAX_REQS_4);
+ NV_PFIFO_CACH1_BIG_ENDIAN |
#endif
+ 0x00000000);
}
#undef RAMFC_WR
@@ -318,17 +321,14 @@ static void nouveau_nv10_context_init(drm_device_t *dev,
RAMFC_WR(DMA_GET , init->put_base);
RAMFC_WR(DMA_INSTANCE , nouveau_chip_instance_get(dev,
cb_obj->instance));
+
+ RAMFC_WR(DMA_FETCH, NV_PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES |
+ NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
+ NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4 |
#ifdef __BIG_ENDIAN
- RAMFC_WR(DMA_FETCH, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES |
- NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES |
- NV_PFIFO_CACH1_DMAF_MAX_REQS_4 |
- NV_PFIFO_CACH1_BIG_ENDIAN);
-#else
-
- RAMFC_WR(DMA_FETCH, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES |
- NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES |
- NV_PFIFO_CACH1_DMAF_MAX_REQS_4);
+ NV_PFIFO_CACH1_BIG_ENDIAN |
#endif
+ 0x00000000);
}
static void nouveau_nv30_context_init(drm_device_t *dev,
@@ -350,24 +350,23 @@ static void nouveau_nv30_context_init(drm_device_t *dev,
RAMFC_WR(DMA_PUT, init->put_base);
RAMFC_WR(DMA_GET, init->put_base);
- RAMFC_WR(REF_CNT, NV_READ(NV_PFIFO_CACH1_REF_CNT));
+ RAMFC_WR(REF_CNT, NV_READ(NV10_PFIFO_CACHE1_REF_CNT));
RAMFC_WR(DMA_INSTANCE, cb_inst);
- RAMFC_WR(DMA_STATE, NV_READ(NV_PFIFO_CACH1_DMAS));
- RAMFC_WR(DMA_FETCH, NV_PFIFO_CACH1_DMAF_TRIG_128_BYTES |
- NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES |
- NV_PFIFO_CACH1_DMAF_MAX_REQS_8 |
+ RAMFC_WR(DMA_STATE, NV_READ(NV04_PFIFO_CACHE1_DMA_STATE));
+ RAMFC_WR(DMA_FETCH, NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
+ NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
+ NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 |
#ifdef __BIG_ENDIAN
NV_PFIFO_CACH1_BIG_ENDIAN |
-#else
- 0x00000000);
#endif
+ 0x00000000);
- RAMFC_WR(ENGINE, NV_READ(NV_PFIFO_CACH1_ENG));
- RAMFC_WR(PULL1_ENGINE, NV_READ(NV_PFIFO_CACH1_PUL1));
- RAMFC_WR(ACQUIRE_VALUE, NV_READ(NV_PFIFO_CACH1_ACQUIRE_VALUE));
- RAMFC_WR(ACQUIRE_TIMESTAMP, NV_READ(NV_PFIFO_CACH1_ACQUIRE_TIMESTAMP));
- RAMFC_WR(ACQUIRE_TIMEOUT, NV_READ(NV_PFIFO_CACH1_ACQUIRE_TIMEOUT));
- RAMFC_WR(SEMAPHORE, NV_READ(NV_PFIFO_CACH1_SEMAPHORE));
+ RAMFC_WR(ENGINE, NV_READ(NV04_PFIFO_CACHE1_ENGINE));
+ RAMFC_WR(PULL1_ENGINE, NV_READ(NV04_PFIFO_CACHE1_PULL1));
+ RAMFC_WR(ACQUIRE_VALUE, NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_VALUE));
+ RAMFC_WR(ACQUIRE_TIMESTAMP, NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP));
+ RAMFC_WR(ACQUIRE_TIMEOUT, NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT));
+ RAMFC_WR(SEMAPHORE, NV_READ(NV10_PFIFO_CACHE1_SEMAPHORE));
RAMFC_WR(DMA_SUBROUTINE, init->put_base);
}
@@ -378,22 +377,22 @@ static void nouveau_nv10_context_save(drm_device_t *dev)
uint32_t fifoctx;
int channel;
- channel = NV_READ(NV_PFIFO_CACH1_PSH1) & (nouveau_fifo_number(dev)-1);
+ channel = NV_READ(NV03_PFIFO_CACHE1_PUSH1) & (nouveau_fifo_number(dev)-1);
fifoctx = NV_RAMIN + dev_priv->ramfc_offset + channel*64;
- RAMFC_WR(DMA_PUT , NV_READ(NV_PFIFO_CACH1_DMAP));
- RAMFC_WR(DMA_GET , NV_READ(NV_PFIFO_CACH1_DMAG));
- RAMFC_WR(REF_CNT , NV_READ(NV_PFIFO_CACH1_REF_CNT));
- RAMFC_WR(DMA_INSTANCE , NV_READ(NV_PFIFO_CACH1_DMAI));
- RAMFC_WR(DMA_STATE , NV_READ(NV_PFIFO_CACH1_DMAS));
- RAMFC_WR(DMA_FETCH , NV_READ(NV_PFIFO_CACH1_DMAF));
- RAMFC_WR(ENGINE , NV_READ(NV_PFIFO_CACH1_ENG));
- RAMFC_WR(PULL1_ENGINE , NV_READ(NV_PFIFO_CACH1_PUL1));
- RAMFC_WR(ACQUIRE_VALUE , NV_READ(NV_PFIFO_CACH1_ACQUIRE_VALUE));
- RAMFC_WR(ACQUIRE_TIMESTAMP, NV_READ(NV_PFIFO_CACH1_ACQUIRE_TIMESTAMP));
- RAMFC_WR(ACQUIRE_TIMEOUT , NV_READ(NV_PFIFO_CACH1_ACQUIRE_TIMEOUT));
- RAMFC_WR(SEMAPHORE , NV_READ(NV_PFIFO_CACH1_SEMAPHORE));
- RAMFC_WR(DMA_SUBROUTINE , NV_READ(NV_PFIFO_CACH1_DMASR));
+ RAMFC_WR(DMA_PUT , NV_READ(NV04_PFIFO_CACHE1_DMA_PUT));
+ RAMFC_WR(DMA_GET , NV_READ(NV04_PFIFO_CACHE1_DMA_GET));
+ RAMFC_WR(REF_CNT , NV_READ(NV10_PFIFO_CACHE1_REF_CNT));
+ RAMFC_WR(DMA_INSTANCE , NV_READ(NV04_PFIFO_CACHE1_DMA_INSTANCE));
+ RAMFC_WR(DMA_STATE , NV_READ(NV04_PFIFO_CACHE1_DMA_STATE));
+ RAMFC_WR(DMA_FETCH , NV_READ(NV04_PFIFO_CACHE1_DMA_FETCH));
+ RAMFC_WR(ENGINE , NV_READ(NV04_PFIFO_CACHE1_ENGINE));
+ RAMFC_WR(PULL1_ENGINE , NV_READ(NV04_PFIFO_CACHE1_PULL1));
+ RAMFC_WR(ACQUIRE_VALUE , NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_VALUE));
+ RAMFC_WR(ACQUIRE_TIMESTAMP, NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP));
+ RAMFC_WR(ACQUIRE_TIMEOUT , NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT));
+ RAMFC_WR(SEMAPHORE , NV_READ(NV10_PFIFO_CACHE1_SEMAPHORE));
+ RAMFC_WR(DMA_SUBROUTINE , NV_READ(NV10_PFIFO_CACHE1_DMA_SUBROUTINE));
}
#undef RAMFC_WR
@@ -418,9 +417,9 @@ static void nouveau_nv40_context_init(drm_device_t *dev,
RAMFC_WR(DMA_PUT , init->put_base);
RAMFC_WR(DMA_GET , init->put_base);
RAMFC_WR(DMA_INSTANCE , cb_inst);
- RAMFC_WR(DMA_FETCH , NV_PFIFO_CACH1_DMAF_TRIG_128_BYTES |
- NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES |
- NV_PFIFO_CACH1_DMAF_MAX_REQS_8 |
+ RAMFC_WR(DMA_FETCH , NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
+ NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
+ NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 |
#ifdef __BIG_ENDIAN
NV_PFIFO_CACH1_BIG_ENDIAN |
#endif
@@ -436,25 +435,25 @@ static void nouveau_nv40_context_save(drm_device_t *dev)
uint32_t fifoctx;
int channel;
- channel = NV_READ(NV_PFIFO_CACH1_PSH1) & (nouveau_fifo_number(dev)-1);
+ channel = NV_READ(NV03_PFIFO_CACHE1_PUSH1) & (nouveau_fifo_number(dev)-1);
fifoctx = NV_RAMIN + dev_priv->ramfc_offset + channel*128;
- RAMFC_WR(DMA_PUT , NV_READ(NV_PFIFO_CACH1_DMAP));
- RAMFC_WR(DMA_GET , NV_READ(NV_PFIFO_CACH1_DMAG));
- RAMFC_WR(REF_CNT , NV_READ(NV_PFIFO_CACH1_REF_CNT));
- RAMFC_WR(DMA_INSTANCE , NV_READ(NV_PFIFO_CACH1_DMAI));
- RAMFC_WR(DMA_DCOUNT , NV_READ(NV_PFIFO_CACH1_DMA_DCOUNT));
- RAMFC_WR(DMA_STATE , NV_READ(NV_PFIFO_CACH1_DMAS));
- RAMFC_WR(DMA_FETCH , NV_READ(NV_PFIFO_CACH1_DMAF));
- RAMFC_WR(ENGINE , NV_READ(NV_PFIFO_CACH1_ENG));
- RAMFC_WR(PULL1_ENGINE , NV_READ(NV_PFIFO_CACH1_PUL1));
- RAMFC_WR(ACQUIRE_VALUE , NV_READ(NV_PFIFO_CACH1_ACQUIRE_VALUE));
- RAMFC_WR(ACQUIRE_TIMESTAMP, NV_READ(NV_PFIFO_CACH1_ACQUIRE_TIMESTAMP));
- RAMFC_WR(ACQUIRE_TIMEOUT , NV_READ(NV_PFIFO_CACH1_ACQUIRE_TIMEOUT));
- RAMFC_WR(SEMAPHORE , NV_READ(NV_PFIFO_CACH1_SEMAPHORE));
- RAMFC_WR(DMA_SUBROUTINE , NV_READ(NV_PFIFO_CACH1_DMAG));
+ RAMFC_WR(DMA_PUT , NV_READ(NV04_PFIFO_CACHE1_DMA_PUT));
+ RAMFC_WR(DMA_GET , NV_READ(NV04_PFIFO_CACHE1_DMA_GET));
+ RAMFC_WR(REF_CNT , NV_READ(NV10_PFIFO_CACHE1_REF_CNT));
+ RAMFC_WR(DMA_INSTANCE , NV_READ(NV04_PFIFO_CACHE1_DMA_INSTANCE));
+ RAMFC_WR(DMA_DCOUNT , NV_READ(NV10_PFIFO_CACHE1_DMA_DCOUNT));
+ RAMFC_WR(DMA_STATE , NV_READ(NV04_PFIFO_CACHE1_DMA_STATE));
+ RAMFC_WR(DMA_FETCH , NV_READ(NV04_PFIFO_CACHE1_DMA_FETCH));
+ RAMFC_WR(ENGINE , NV_READ(NV04_PFIFO_CACHE1_ENGINE));
+ RAMFC_WR(PULL1_ENGINE , NV_READ(NV04_PFIFO_CACHE1_PULL1));
+ RAMFC_WR(ACQUIRE_VALUE , NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_VALUE));
+ RAMFC_WR(ACQUIRE_TIMESTAMP, NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP));
+ RAMFC_WR(ACQUIRE_TIMEOUT , NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT));
+ RAMFC_WR(SEMAPHORE , NV_READ(NV10_PFIFO_CACHE1_SEMAPHORE));
+ RAMFC_WR(DMA_SUBROUTINE , NV_READ(NV04_PFIFO_CACHE1_DMA_GET));
RAMFC_WR(GRCTX_INSTANCE , NV_READ(NV40_PFIFO_GRCTX_INSTANCE));
- RAMFC_WR(DMA_TIMESLICE , NV_READ(NV_PFIFO_DMA_TIMESLICE) & 0x1FFFF);
+ RAMFC_WR(DMA_TIMESLICE , NV_READ(NV04_PFIFO_DMA_TIMESLICE) & 0x1FFFF);
RAMFC_WR(UNK_40 , NV_READ(NV40_PFIFO_UNK32E4));
}
#undef RAMFC_WR
@@ -475,25 +474,28 @@ nouveau_fifo_context_restore(drm_device_t *dev, int channel)
// FIXME check if we need to refill the time quota with something like NV_WRITE(0x204C, 0x0003FFFF);
if (dev_priv->card_type >= NV_40)
- NV_WRITE(NV_PFIFO_CACH1_PSH1, 0x00010000|channel);
+ NV_WRITE(NV03_PFIFO_CACHE1_PUSH1, 0x00010000|channel);
else
- NV_WRITE(NV_PFIFO_CACH1_PSH1, 0x00000100|channel);
-
- NV_WRITE(NV_PFIFO_CACH1_DMAP, 0 /*RAMFC_DMA_PUT*/);
- NV_WRITE(NV_PFIFO_CACH1_DMAG, 0 /*RAMFC_DMA_GET*/);
- NV_WRITE(NV_PFIFO_CACH1_DMAI, cb_inst);
- NV_WRITE(NV_PFIFO_SIZE , 0x0000FFFF);
- NV_WRITE(NV_PFIFO_CACH1_HASH, 0x0000FFFF);
-
- NV_WRITE(NV_PFIFO_CACH0_PUL1, 0x00000001);
- NV_WRITE(NV_PFIFO_CACH1_DMAC, 0x00000000);
- NV_WRITE(NV_PFIFO_CACH1_DMAS, 0x00000000);
- NV_WRITE(NV_PFIFO_CACH1_ENG, 0x00000000);
+ NV_WRITE(NV03_PFIFO_CACHE1_PUSH1, 0x00000100|channel);
+
+ NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUT, 0 /*RAMFC_DMA_PUT*/);
+ NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET, 0 /*RAMFC_DMA_GET*/);
+ NV_WRITE(NV04_PFIFO_CACHE1_DMA_INSTANCE, cb_inst);
+ NV_WRITE(NV04_PFIFO_SIZE , 0x0000FFFF);
+ NV_WRITE(NV04_PFIFO_CACHE1_HASH, 0x0000FFFF);
+
+ NV_WRITE(NV04_PFIFO_CACHE0_PULL1, 0x00000001);
+ NV_WRITE(NV04_PFIFO_CACHE1_DMA_CTL, 0x00000000);
+ NV_WRITE(NV04_PFIFO_CACHE1_DMA_STATE, 0x00000000);
+ NV_WRITE(NV04_PFIFO_CACHE1_ENGINE, 0x00000000);
+
+ NV_WRITE(NV04_PFIFO_CACHE1_DMA_FETCH, NV_PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES |
+ NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
+ NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4 |
#ifdef __BIG_ENDIAN
- NV_WRITE(NV_PFIFO_CACH1_DMAF, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES|NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES|NV_PFIFO_CACH1_DMAF_MAX_REQS_4|NV_PFIFO_CACH1_BIG_ENDIAN);
-#else
- NV_WRITE(NV_PFIFO_CACH1_DMAF, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES|NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES|NV_PFIFO_CACH1_DMAF_MAX_REQS_4);
+ NV_PFIFO_CACH1_BIG_ENDIAN |
#endif
+ 0x00000000);
}
/* allocates and initializes a fifo for user space consumption */
@@ -537,42 +539,53 @@ static int nouveau_fifo_alloc(drm_device_t* dev,drm_nouveau_fifo_alloc_t* init,
nouveau_wait_for_idle(dev);
/* disable the fifo caches */
- NV_WRITE(NV_PFIFO_CACHES, 0x00000000);
- NV_WRITE(NV_PFIFO_CACH1_DMAPSH, NV_READ(NV_PFIFO_CACH1_DMAPSH)&(~0x1));
- NV_WRITE(NV_PFIFO_CACH1_PSH0, 0x00000000);
- NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000000);
+ NV_WRITE(NV03_PFIFO_CACHES, 0x00000000);
+ NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUSH, NV_READ(NV04_PFIFO_CACHE1_DMA_PUSH)&(~0x1));
+ NV_WRITE(NV03_PFIFO_CACHE1_PUSH0, 0x00000000);
+ NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000000);
/* Construct inital RAMFC for new channel */
- if (dev_priv->card_type < NV_10) {
- nouveau_nv04_context_init(dev, init);
- } else if (dev_priv->card_type < NV_20) {
- nv10_graph_context_create(dev, init->channel);
- nouveau_nv10_context_init(dev, init);
- } else if (dev_priv->card_type < NV_30) {
- ret = nv20_graph_context_create(dev, init->channel);
- if (ret) {
- nouveau_fifo_free(dev, init->channel);
- return ret;
- }
- nouveau_nv10_context_init(dev, init);
- } else if (dev_priv->card_type < NV_40) {
- ret = nv30_graph_context_create(dev, init->channel);
- if (ret) {
- nouveau_fifo_free(dev, init->channel);
- return ret;
- }
- nouveau_nv30_context_init(dev, init);
- } else {
- ret = nv40_graph_context_create(dev, init->channel);
- if (ret) {
- nouveau_fifo_free(dev, init->channel);
- return ret;
- }
- nouveau_nv40_context_init(dev, init);
+ switch(dev_priv->card_type)
+ {
+ case NV_04:
+ case NV_05:
+ nv04_graph_context_create(dev, init->channel);
+ nouveau_nv04_context_init(dev, init);
+ break;
+ case NV_10:
+ nv10_graph_context_create(dev, init->channel);
+ nouveau_nv10_context_init(dev, init);
+ break;
+ case NV_20:
+ ret = nv20_graph_context_create(dev, init->channel);
+ if (ret) {
+ nouveau_fifo_free(dev, init->channel);
+ return ret;
+ }
+ nouveau_nv10_context_init(dev, init);
+ break;
+ case NV_30:
+ ret = nv30_graph_context_create(dev, init->channel);
+ if (ret) {
+ nouveau_fifo_free(dev, init->channel);
+ return ret;
+ }
+ nouveau_nv30_context_init(dev, init);
+ break;
+ case NV_40:
+ case NV_44:
+ case NV_50:
+ ret = nv40_graph_context_create(dev, init->channel);
+ if (ret) {
+ nouveau_fifo_free(dev, init->channel);
+ return ret;
+ }
+ nouveau_nv40_context_init(dev, init);
+ break;
}
/* enable the fifo dma operation */
- NV_WRITE(NV_PFIFO_MODE,NV_READ(NV_PFIFO_MODE)|(1<<init->channel));
+ NV_WRITE(NV04_PFIFO_MODE,NV_READ(NV04_PFIFO_MODE)|(1<<init->channel));
/* setup channel's default get/put values */
NV_WRITE(NV03_FIFO_REGS_DMAPUT(init->channel), init->put_base);
@@ -592,7 +605,7 @@ static int nouveau_fifo_alloc(drm_device_t* dev,drm_nouveau_fifo_alloc_t* init,
chan->ramin_grctx);
/* see comments in nv40_graph_context_restore() */
- NV_WRITE(NV_PGRAPH_CHANNEL_CTX_SIZE, inst);
+ NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_SIZE, inst);
if (dev_priv->card_type >= NV_40) {
NV_WRITE(0x40032C, inst | 0x01000000);
NV_WRITE(NV40_PFIFO_GRCTX_INSTANCE, inst);
@@ -600,13 +613,13 @@ static int nouveau_fifo_alloc(drm_device_t* dev,drm_nouveau_fifo_alloc_t* init,
}
}
- NV_WRITE(NV_PFIFO_CACH1_DMAPSH, 0x00000001);
- NV_WRITE(NV_PFIFO_CACH1_PSH0, 0x00000001);
- NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000001);
- NV_WRITE(NV_PFIFO_CACH1_PUL1, 0x00000001);
+ NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUSH, 0x00000001);
+ NV_WRITE(NV03_PFIFO_CACHE1_PUSH0, 0x00000001);
+ NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000001);
+ NV_WRITE(NV04_PFIFO_CACHE1_PULL1, 0x00000001);
/* reenable the fifo caches */
- NV_WRITE(NV_PFIFO_CACHES, 0x00000001);
+ NV_WRITE(NV03_PFIFO_CACHES, 0x00000001);
/* make the fifo available to user space */
/* first, the fifo control regs */
@@ -640,9 +653,9 @@ void nouveau_fifo_free(drm_device_t* dev,int n)
DRM_INFO("%s: freeing fifo %d\n", __func__, n);
/* disable the fifo caches */
- NV_WRITE(NV_PFIFO_CACHES, 0x00000000);
+ NV_WRITE(NV03_PFIFO_CACHES, 0x00000000);
- NV_WRITE(NV_PFIFO_MODE,NV_READ(NV_PFIFO_MODE)&~(1<<n));
+ NV_WRITE(NV04_PFIFO_MODE,NV_READ(NV04_PFIFO_MODE)&~(1<<n));
// FIXME XXX needs more code
/* Clean RAMFC */
@@ -663,7 +676,7 @@ void nouveau_fifo_free(drm_device_t* dev,int n)
}
/* reenable the fifo caches */
- NV_WRITE(NV_PFIFO_CACHES, 0x00000001);
+ NV_WRITE(NV03_PFIFO_CACHES, 0x00000001);
/* Deallocate command buffer, and dma object */
nouveau_mem_free(dev, dev_priv->fifos[n].cmdbuf_mem);
@@ -741,5 +754,3 @@ drm_ioctl_desc_t nouveau_ioctls[] = {
};
int nouveau_max_ioctl = DRM_ARRAY_SIZE(nouveau_ioctls);
-
-
diff --git a/shared-core/nouveau_irq.c b/shared-core/nouveau_irq.c
index ac88b684..51d4bae1 100644
--- a/shared-core/nouveau_irq.c
+++ b/shared-core/nouveau_irq.c
@@ -43,14 +43,14 @@ void nouveau_irq_preinstall(drm_device_t *dev)
DRM_DEBUG("IRQ: preinst\n");
/* Disable/Clear PFIFO interrupts */
- NV_WRITE(NV_PFIFO_INTEN, 0);
- NV_WRITE(NV_PFIFO_INTSTAT, 0xFFFFFFFF);
+ NV_WRITE(NV03_PFIFO_INTR_EN_0, 0);
+ NV_WRITE(NV03_PMC_INTR_0, 0xFFFFFFFF);
/* Disable/Clear PGRAPH interrupts */
if (dev_priv->card_type<NV_40)
- NV_WRITE(NV04_PGRAPH_INTEN, 0);
+ NV_WRITE(NV03_PGRAPH_INTR_EN, 0);
else
- NV_WRITE(NV40_PGRAPH_INTEN, 0);
- NV_WRITE(NV_PGRAPH_INTSTAT, 0xFFFFFFFF);
+ NV_WRITE(NV40_PGRAPH_INTR_EN, 0);
+ NV_WRITE(NV03_PGRAPH_INTR, 0xFFFFFFFF);
#if 0
/* Disable/Clear CRTC0/1 interrupts */
NV_WRITE(NV_CRTC0_INTEN, 0);
@@ -59,7 +59,7 @@ void nouveau_irq_preinstall(drm_device_t *dev)
NV_WRITE(NV_CRTC1_INTSTAT, NV_CRTC_INTR_VBLANK);
#endif
/* Master disable */
- NV_WRITE(NV_PMC_INTEN, 0);
+ NV_WRITE(NV03_PMC_INTR_EN_0, 0);
}
void nouveau_irq_postinstall(drm_device_t *dev)
@@ -69,7 +69,7 @@ void nouveau_irq_postinstall(drm_device_t *dev)
DRM_DEBUG("IRQ: postinst\n");
/* Enable PFIFO error reporting */
- NV_WRITE(NV_PFIFO_INTEN ,
+ NV_WRITE(NV03_PFIFO_INTR_EN_0 ,
NV_PFIFO_INTR_CACHE_ERROR |
NV_PFIFO_INTR_RUNOUT |
NV_PFIFO_INTR_RUNOUT_OVERFLOW |
@@ -78,11 +78,11 @@ void nouveau_irq_postinstall(drm_device_t *dev)
NV_PFIFO_INTR_SEMAPHORE |
NV_PFIFO_INTR_ACQUIRE_TIMEOUT
);
- NV_WRITE(NV_PFIFO_INTSTAT, 0xFFFFFFFF);
+ NV_WRITE(NV03_PMC_INTR_0, 0xFFFFFFFF);
/* Enable PGRAPH interrupts */
if (dev_priv->card_type<NV_40)
- NV_WRITE(NV04_PGRAPH_INTEN,
+ NV_WRITE(NV03_PGRAPH_INTR_EN,
NV_PGRAPH_INTR_NOTIFY |
NV_PGRAPH_INTR_MISSING_HW |
NV_PGRAPH_INTR_CONTEXT_SWITCH |
@@ -90,14 +90,14 @@ void nouveau_irq_postinstall(drm_device_t *dev)
NV_PGRAPH_INTR_ERROR
);
else
- NV_WRITE(NV40_PGRAPH_INTEN,
+ NV_WRITE(NV40_PGRAPH_INTR_EN,
NV_PGRAPH_INTR_NOTIFY |
NV_PGRAPH_INTR_MISSING_HW |
NV_PGRAPH_INTR_CONTEXT_SWITCH |
NV_PGRAPH_INTR_BUFFER_NOTIFY |
NV_PGRAPH_INTR_ERROR
);
- NV_WRITE(NV_PGRAPH_INTSTAT, 0xFFFFFFFF);
+ NV_WRITE(NV03_PGRAPH_INTR, 0xFFFFFFFF);
#if 0
/* Enable CRTC0/1 interrupts */
@@ -106,7 +106,7 @@ void nouveau_irq_postinstall(drm_device_t *dev)
#endif
/* Master enable */
- NV_WRITE(NV_PMC_INTEN, NV_PMC_INTEN_MASTER_ENABLE);
+ NV_WRITE(NV03_PMC_INTR_EN_0, NV_PMC_INTR_EN_0_MASTER_ENABLE);
}
void nouveau_irq_uninstall(drm_device_t *dev)
@@ -116,19 +116,19 @@ void nouveau_irq_uninstall(drm_device_t *dev)
DRM_DEBUG("IRQ: uninst\n");
/* Disable PFIFO interrupts */
- NV_WRITE(NV_PFIFO_INTEN, 0);
+ NV_WRITE(NV03_PFIFO_INTR_EN_0, 0);
/* Disable PGRAPH interrupts */
if (dev_priv->card_type<NV_40)
- NV_WRITE(NV04_PGRAPH_INTEN, 0);
+ NV_WRITE(NV03_PGRAPH_INTR_EN, 0);
else
- NV_WRITE(NV40_PGRAPH_INTEN, 0);
+ NV_WRITE(NV40_PGRAPH_INTR_EN, 0);
#if 0
/* Disable CRTC0/1 interrupts */
NV_WRITE(NV_CRTC0_INTEN, 0);
NV_WRITE(NV_CRTC1_INTEN, 0);
#endif
/* Master disable */
- NV_WRITE(NV_PMC_INTEN, 0);
+ NV_WRITE(NV03_PMC_INTR_EN_0, 0);
}
static void nouveau_fifo_irq_handler(drm_device_t *dev)
@@ -136,12 +136,12 @@ static void nouveau_fifo_irq_handler(drm_device_t *dev)
uint32_t status, chmode, chstat, channel;
drm_nouveau_private_t *dev_priv = dev->dev_private;
- status = NV_READ(NV_PFIFO_INTSTAT);
+ status = NV_READ(NV03_PMC_INTR_0);
if (!status)
return;
- chmode = NV_READ(NV_PFIFO_MODE);
- chstat = NV_READ(NV_PFIFO_DMA);
- channel=NV_READ(NV_PFIFO_CACH1_PSH1)&(nouveau_fifo_number(dev)-1);
+ chmode = NV_READ(NV04_PFIFO_MODE);
+ chstat = NV_READ(NV04_PFIFO_DMA);
+ channel=NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1);
DRM_DEBUG("NV: PFIFO interrupt! Channel=%d, INTSTAT=0x%08x/MODE=0x%08x/PEND=0x%08x\n", channel, status, chmode, chstat);
@@ -150,14 +150,14 @@ static void nouveau_fifo_irq_handler(drm_device_t *dev)
DRM_ERROR("NV: PFIFO error interrupt\n");
- c1get = NV_READ(NV_PFIFO_CACH1_GET) >> 2;
+ c1get = NV_READ(NV03_PFIFO_CACHE1_GET) >> 2;
if (dev_priv->card_type < NV_40) {
/* Untested, so it may not work.. */
- c1method = NV_READ(NV_PFIFO_CACH1_METHOD(c1get));
- c1data = NV_READ(NV_PFIFO_CACH1_DATA(c1get));
+ c1method = NV_READ(NV04_PFIFO_CACHE1_METHOD(c1get));
+ c1data = NV_READ(NV04_PFIFO_CACHE1_DATA(c1get));
} else {
- c1method = NV_READ(NV40_PFIFO_CACH1_METHOD(c1get));
- c1data = NV_READ(NV40_PFIFO_CACH1_DATA(c1get));
+ c1method = NV_READ(NV40_PFIFO_CACHE1_METHOD(c1get));
+ c1data = NV_READ(NV40_PFIFO_CACHE1_DATA(c1get));
}
DRM_ERROR("NV: Channel %d/%d - Method 0x%04x, Data 0x%08x\n",
@@ -166,40 +166,41 @@ static void nouveau_fifo_irq_handler(drm_device_t *dev)
);
status &= ~NV_PFIFO_INTR_CACHE_ERROR;
- NV_WRITE(NV_PFIFO_INTSTAT, NV_PFIFO_INTR_CACHE_ERROR);
+ NV_WRITE(NV03_PMC_INTR_0, NV_PFIFO_INTR_CACHE_ERROR);
}
if (status & NV_PFIFO_INTR_DMA_PUSHER) {
DRM_INFO("NV: PFIFO DMA pusher interrupt\n");
status &= ~NV_PFIFO_INTR_DMA_PUSHER;
- NV_WRITE(NV_PFIFO_INTSTAT, NV_PFIFO_INTR_DMA_PUSHER);
+ NV_WRITE(NV03_PMC_INTR_0, NV_PFIFO_INTR_DMA_PUSHER);
- NV_WRITE(NV_PFIFO_CACH1_DMAS, 0x00000000);
- if (NV_READ(NV_PFIFO_CACH1_DMAP)!=NV_READ(NV_PFIFO_CACH1_DMAG))
+ NV_WRITE(NV04_PFIFO_CACHE1_DMA_STATE, 0x00000000);
+ if (NV_READ(NV04_PFIFO_CACHE1_DMA_PUT)!=NV_READ(NV04_PFIFO_CACHE1_DMA_GET))
{
- uint32_t getval=NV_READ(NV_PFIFO_CACH1_DMAG)+4;
- NV_WRITE(NV_PFIFO_CACH1_DMAG,getval);
+ uint32_t getval=NV_READ(NV04_PFIFO_CACHE1_DMA_GET)+4;
+ NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET,getval);
}
}
if (status) {
DRM_INFO("NV: unknown PFIFO interrupt. status=0x%08x\n", status);
- NV_WRITE(NV_PFIFO_INTSTAT, status);
+ NV_WRITE(NV03_PMC_INTR_0, status);
}
- NV_WRITE(NV_PMC_INTSTAT, NV_PMC_INTSTAT_PFIFO_PENDING);
+ NV_WRITE(NV03_PMC_INTR_0, NV_PMC_INTR_0_PFIFO_PENDING);
}
+#if 0
static void nouveau_nv04_context_switch(drm_device_t *dev)
{
drm_nouveau_private_t *dev_priv = dev->dev_private;
uint32_t channel,i;
uint32_t max=0;
- NV_WRITE(NV_PGRAPH_FIFO,0x0);
- channel=NV_READ(NV_PFIFO_CACH1_PSH1)&(nouveau_fifo_number(dev)-1);
- //DRM_INFO("raw PFIFO_CACH1_PHS1 reg is %x\n",NV_READ(NV_PFIFO_CACH1_PSH1));
+ NV_WRITE(NV04_PGRAPH_FIFO,0x0);
+ channel=NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1);
+ //DRM_INFO("raw PFIFO_CACH1_PHS1 reg is %x\n",NV_READ(NV03_PFIFO_CACHE1_PUSH1));
//DRM_INFO("currently on channel %d\n",channel);
for (i=0;i<nouveau_fifo_number(dev);i++)
if ((dev_priv->fifos[i].used)&&(i!=channel)) {
@@ -208,13 +209,13 @@ static void nouveau_nv04_context_switch(drm_device_t *dev)
//get=NV_READ(dev_priv->ramfc_offset+4+i*32);
put=NV_READ(NV03_FIFO_REGS_DMAPUT(i));
get=NV_READ(NV03_FIFO_REGS_DMAGET(i));
- pending=NV_READ(NV_PFIFO_DMA);
+ pending=NV_READ(NV04_PFIFO_DMA);
//DRM_INFO("Channel %d (put/get %x/%x)\n",i,put,get);
/* mark all pending channels as such */
if ((put!=get)&!(pending&(1<<i)))
{
pending|=(1<<i);
- NV_WRITE(NV_PFIFO_DMA,pending);
+ NV_WRITE(NV04_PFIFO_DMA,pending);
}
max++;
}
@@ -222,27 +223,28 @@ static void nouveau_nv04_context_switch(drm_device_t *dev)
#if 1
/* 2-channel commute */
- // NV_WRITE(NV_PFIFO_CACH1_PSH1,channel|0x100);
+ // NV_WRITE(NV03_PFIFO_CACHE1_PUSH1,channel|0x100);
if (channel==0)
channel=1;
else
channel=0;
// dev_priv->cur_fifo=channel;
- NV_WRITE(0x2050,channel|0x100);
+ NV_WRITE(NV04_PFIFO_NEXT_CHANNEL,channel|0x100);
#endif
- //NV_WRITE(NV_PFIFO_CACH1_PSH1,max|0x100);
+ //NV_WRITE(NV03_PFIFO_CACHE1_PUSH1,max|0x100);
//NV_WRITE(0x2050,max|0x100);
- NV_WRITE(NV_PGRAPH_FIFO,0x1);
+ NV_WRITE(NV04_PGRAPH_FIFO,0x1);
}
+#endif
static void nouveau_pgraph_irq_handler(drm_device_t *dev)
{
uint32_t status;
drm_nouveau_private_t *dev_priv = dev->dev_private;
- status = NV_READ(NV_PGRAPH_INTSTAT);
+ status = NV_READ(NV03_PGRAPH_INTR);
if (!status)
return;
@@ -259,7 +261,7 @@ static void nouveau_pgraph_irq_handler(drm_device_t *dev)
DRM_DEBUG("instance:0x%08x\tnotify:0x%08x\n", nsource, nstatus);
status &= ~NV_PGRAPH_INTR_NOTIFY;
- NV_WRITE(NV_PGRAPH_INTSTAT, NV_PGRAPH_INTR_NOTIFY);
+ NV_WRITE(NV03_PGRAPH_INTR, NV_PGRAPH_INTR_NOTIFY);
}
if (status & NV_PGRAPH_INTR_BUFFER_NOTIFY) {
@@ -275,14 +277,14 @@ static void nouveau_pgraph_irq_handler(drm_device_t *dev)
DRM_DEBUG("instance:0x%08x\tnotify:0x%08x\n", instance, notify);
status &= ~NV_PGRAPH_INTR_BUFFER_NOTIFY;
- NV_WRITE(NV_PGRAPH_INTSTAT, NV_PGRAPH_INTR_BUFFER_NOTIFY);
+ NV_WRITE(NV03_PGRAPH_INTR, NV_PGRAPH_INTR_BUFFER_NOTIFY);
}
if (status & NV_PGRAPH_INTR_MISSING_HW) {
DRM_ERROR("NV: PGRAPH missing hw interrupt\n");
status &= ~NV_PGRAPH_INTR_MISSING_HW;
- NV_WRITE(NV_PGRAPH_INTSTAT, NV_PGRAPH_INTR_MISSING_HW);
+ NV_WRITE(NV03_PGRAPH_INTR, NV_PGRAPH_INTR_MISSING_HW);
}
if (status & NV_PGRAPH_INTR_ERROR) {
@@ -314,11 +316,11 @@ static void nouveau_pgraph_irq_handler(drm_device_t *dev)
);
status &= ~NV_PGRAPH_INTR_ERROR;
- NV_WRITE(NV_PGRAPH_INTSTAT, NV_PGRAPH_INTR_ERROR);
+ NV_WRITE(NV03_PGRAPH_INTR, NV_PGRAPH_INTR_ERROR);
}
if (status & NV_PGRAPH_INTR_CONTEXT_SWITCH) {
- uint32_t channel=NV_READ(NV_PFIFO_CACH1_PSH1)&(nouveau_fifo_number(dev)-1);
+ uint32_t channel=NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1);
DRM_INFO("NV: PGRAPH context switch interrupt channel %x\n",channel);
switch(dev_priv->card_type)
{
@@ -339,15 +341,15 @@ static void nouveau_pgraph_irq_handler(drm_device_t *dev)
}
status &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
- NV_WRITE(NV_PGRAPH_INTSTAT, NV_PGRAPH_INTR_CONTEXT_SWITCH);
+ NV_WRITE(NV03_PGRAPH_INTR, NV_PGRAPH_INTR_CONTEXT_SWITCH);
}
if (status) {
DRM_INFO("NV: Unknown PGRAPH interrupt! STAT=0x%08x\n", status);
- NV_WRITE(NV_PGRAPH_INTSTAT, status);
+ NV_WRITE(NV03_PGRAPH_INTR, status);
}
- NV_WRITE(NV_PMC_INTSTAT, NV_PMC_INTSTAT_PGRAPH_PENDING);
+ NV_WRITE(NV03_PMC_INTR_0, NV_PMC_INTR_0_PGRAPH_PENDING);
}
static void nouveau_crtc_irq_handler(drm_device_t *dev, int crtc)
@@ -368,23 +370,23 @@ irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS)
drm_nouveau_private_t *dev_priv = dev->dev_private;
uint32_t status;
- status = NV_READ(NV_PMC_INTSTAT);
+ status = NV_READ(NV03_PMC_INTR_0);
if (!status)
return IRQ_NONE;
DRM_DEBUG("PMC INTSTAT: 0x%08x\n", status);
- if (status & NV_PMC_INTSTAT_PFIFO_PENDING) {
+ if (status & NV_PMC_INTR_0_PFIFO_PENDING) {
nouveau_fifo_irq_handler(dev);
- status &= ~NV_PMC_INTSTAT_PFIFO_PENDING;
+ status &= ~NV_PMC_INTR_0_PFIFO_PENDING;
}
- if (status & NV_PMC_INTSTAT_PGRAPH_PENDING) {
+ if (status & NV_PMC_INTR_0_PGRAPH_PENDING) {
nouveau_pgraph_irq_handler(dev);
- status &= ~NV_PMC_INTSTAT_PGRAPH_PENDING;
+ status &= ~NV_PMC_INTR_0_PGRAPH_PENDING;
}
- if (status & NV_PMC_INTSTAT_CRTCn_PENDING) {
+ if (status & NV_PMC_INTR_0_CRTCn_PENDING) {
nouveau_crtc_irq_handler(dev, (status>>24)&3);
- status &= ~NV_PMC_INTSTAT_CRTCn_PENDING;
+ status &= ~NV_PMC_INTR_0_CRTCn_PENDING;
}
if (status)
diff --git a/shared-core/nouveau_reg.h b/shared-core/nouveau_reg.h
index 543be694..966600cf 100644
--- a/shared-core/nouveau_reg.h
+++ b/shared-core/nouveau_reg.h
@@ -45,131 +45,200 @@
# define NV03_FIFO_REGS_DMAPUT(i) (NV03_FIFO_REGS(i)+0x40)
# define NV03_FIFO_REGS_DMAGET(i) (NV03_FIFO_REGS(i)+0x44)
-#define NV_PMC_BOOT_0 0x00000000
-#define NV_PMC_INTSTAT 0x00000100
-# define NV_PMC_INTSTAT_PFIFO_PENDING (1<< 8)
-# define NV_PMC_INTSTAT_PGRAPH_PENDING (1<<12)
-# define NV_PMC_INTSTAT_CRTC0_PENDING (1<<24)
-# define NV_PMC_INTSTAT_CRTC1_PENDING (1<<25)
-# define NV_PMC_INTSTAT_CRTCn_PENDING (3<<24)
-#define NV_PMC_INTEN 0x00000140
-# define NV_PMC_INTEN_MASTER_ENABLE (1<< 0)
+#define NV03_PMC_BOOT_0 0x00000000
+#define NV03_PMC_INTR_0 0x00000100
+# define NV_PMC_INTR_0_PFIFO_PENDING (1<< 8)
+# define NV_PMC_INTR_0_PGRAPH_PENDING (1<<12)
+# define NV_PMC_INTR_0_CRTC0_PENDING (1<<24)
+# define NV_PMC_INTR_0_CRTC1_PENDING (1<<25)
+# define NV_PMC_INTR_0_CRTCn_PENDING (3<<24)
+#define NV03_PMC_INTR_EN_0 0x00000140
+# define NV_PMC_INTR_EN_0_MASTER_ENABLE (1<< 0)
-#define NV_PGRAPH_DEBUG_4 0x00400090
-#define NV_PGRAPH_INTSTAT 0x00400100
-#define NV04_PGRAPH_INTEN 0x00400140
-#define NV40_PGRAPH_INTEN 0x0040013C
+#define NV10_PGRAPH_DEBUG_4 0x00400090
+#define NV03_PGRAPH_INTR 0x00400100
+#define NV03_PGRAPH_INTR_EN 0x00400140
+#define NV40_PGRAPH_INTR_EN 0x0040013C
# define NV_PGRAPH_INTR_NOTIFY (1<< 0)
# define NV_PGRAPH_INTR_MISSING_HW (1<< 4)
# define NV_PGRAPH_INTR_CONTEXT_SWITCH (1<<12)
# define NV_PGRAPH_INTR_BUFFER_NOTIFY (1<<16)
# define NV_PGRAPH_INTR_ERROR (1<<20)
-#define NV_PGRAPH_CTX_CONTROL 0x00400144
-#define NV_PGRAPH_NV40_UNK220 0x00400220
-# define NV_PGRAPH_NV40_UNK220_FB_INSTANCE
-#define NV_PGRAPH_CTX_USER 0x00400148
-#define NV_PGRAPH_CTX_SWITCH1 0x0040014C
-#define NV_PGRAPH_CTX_SWITCH2 0x00400150
-#define NV_PGRAPH_CTX_SWITCH3 0x00400154
-#define NV_PGRAPH_CTX_SWITCH4 0x00400158
-#define NV_PGRAPH_CTX_SWITCH5 0x0040015C
-#define NV_PGRAPH_X_MISC 0x00400500
-#define NV_PGRAPH_Y_MISC 0x00400504
-#define NV_PGRAPH_VALID1 0x00400508
-#define NV_PGRAPH_SOURCE_COLOR 0x0040050C
-#define NV_PGRAPH_MISC24_0 0x00400510
-#define NV_PGRAPH_XY_LOGIC_MISC0 0x00400514
-#define NV_PGRAPH_XY_LOGIC_MISC1 0x00400518
-#define NV_PGRAPH_XY_LOGIC_MISC2 0x0040051C
-#define NV_PGRAPH_XY_LOGIC_MISC3 0x00400520
-#define NV_PGRAPH_CLIPX_0 0x00400524
-#define NV_PGRAPH_CLIPX_1 0x00400528
-#define NV_PGRAPH_CLIPY_0 0x0040052C
-#define NV_PGRAPH_CLIPY_1 0x00400530
-#define NV_PGRAPH_ABS_ICLIP_XMAX 0x00400534
-#define NV_PGRAPH_ABS_ICLIP_YMAX 0x00400538
-#define NV_PGRAPH_ABS_UCLIP_XMIN 0x0040053C
-#define NV_PGRAPH_ABS_UCLIP_YMIN 0x00400540
-#define NV_PGRAPH_ABS_UCLIP_XMAX 0x00400544
-#define NV_PGRAPH_ABS_UCLIP_YMAX 0x00400548
-#define NV_PGRAPH_ABS_UCLIPA_XMIN 0x00400560
-#define NV_PGRAPH_ABS_UCLIPA_YMIN 0x00400564
-#define NV_PGRAPH_ABS_UCLIPA_XMAX 0x00400568
-#define NV_PGRAPH_ABS_UCLIPA_YMAX 0x0040056C
-#define NV_PGRAPH_MISC24_1 0x00400570
-#define NV_PGRAPH_MISC24_2 0x00400574
-#define NV_PGRAPH_VALID2 0x00400578
-#define NV_PGRAPH_PASSTHRU_0 0x0040057C
-#define NV_PGRAPH_PASSTHRU_1 0x00400580
-#define NV_PGRAPH_PASSTHRU_2 0x00400584
-#define NV_PGRAPH_DIMX_TEXTURE 0x00400588
-#define NV_PGRAPH_WDIMX_TEXTURE 0x0040058C
-#define NV_PGRAPH_MONO_COLOR0 0x00400600
-#define NV_PGRAPH_ROP3 0x00400604
-#define NV_PGRAPH_BETA_AND 0x00400608
-#define NV_PGRAPH_BETA_PREMULT 0x0040060C
-#define NV_PGRAPH_BOFFSET0 0x00400640
-#define NV_PGRAPH_BOFFSET1 0x00400644
-#define NV_PGRAPH_BOFFSET2 0x00400648
-#define NV_PGRAPH_BOFFSET3 0x0040064C
-#define NV_PGRAPH_BOFFSET4 0x00400650
-#define NV_PGRAPH_BOFFSET5 0x00400654
-#define NV_PGRAPH_BBASE0 0x00400658
-#define NV_PGRAPH_BBASE1 0x0040065C
-#define NV_PGRAPH_BBASE2 0x00400660
-#define NV_PGRAPH_BBASE3 0x00400664
-#define NV_PGRAPH_BBASE4 0x00400668
-#define NV_PGRAPH_BBASE5 0x0040066C
-#define NV_PGRAPH_BPITCH0 0x00400670
-#define NV_PGRAPH_BPITCH1 0x00400674
-#define NV_PGRAPH_BPITCH2 0x00400678
-#define NV_PGRAPH_BPITCH3 0x0040067C
-#define NV_PGRAPH_BPITCH4 0x00400680
-#define NV_PGRAPH_BLIMIT0 0x00400684
-#define NV_PGRAPH_BLIMIT1 0x00400688
-#define NV_PGRAPH_BLIMIT2 0x0040068C
-#define NV_PGRAPH_BLIMIT3 0x00400690
-#define NV_PGRAPH_BLIMIT4 0x00400694
-#define NV_PGRAPH_BLIMIT5 0x00400698
-#define NV_PGRAPH_BSWIZZLE2 0x0040069C
-#define NV_PGRAPH_BSWIZZLE5 0x004006A0
-#define NV_PGRAPH_SURFACE 0x00400710
-#define NV_PGRAPH_STATE 0x00400714
-#define NV_PGRAPH_NOTIFY 0x00400718
+#define NV10_PGRAPH_CTX_CONTROL 0x00400144
+#define NV10_PGRAPH_CTX_USER 0x00400148
+#define NV10_PGRAPH_CTX_SWITCH1 0x0040014C
+#define NV10_PGRAPH_CTX_SWITCH2 0x00400150
+#define NV10_PGRAPH_CTX_SWITCH3 0x00400154
+#define NV10_PGRAPH_CTX_SWITCH4 0x00400158
+#define NV10_PGRAPH_CTX_SWITCH5 0x0040015C
+#define NV04_PGRAPH_CTX_SWITCH1 0x00400160
+#define NV10_PGRAPH_CTX_CACHE1 0x00400160
+#define NV04_PGRAPH_CTX_SWITCH2 0x00400164
+#define NV04_PGRAPH_CTX_SWITCH3 0x00400168
+#define NV04_PGRAPH_CTX_SWITCH4 0x0040016C
+#define NV04_PGRAPH_CTX_CONTROL 0x00400170
+#define NV04_PGRAPH_CTX_USER 0x00400174
+#define NV04_PGRAPH_CTX_CACHE1 0x00400180
+#define NV10_PGRAPH_CTX_CACHE2 0x00400180
+#define NV03_PGRAPH_CTX_CONTROL 0x00400190
+#define NV03_PGRAPH_CTX_USER 0x00400194
+#define NV04_PGRAPH_CTX_CACHE2 0x004001A0
+#define NV10_PGRAPH_CTX_CACHE3 0x004001A0
+#define NV04_PGRAPH_CTX_CACHE3 0x004001C0
+#define NV10_PGRAPH_CTX_CACHE4 0x004001C0
+#define NV04_PGRAPH_CTX_CACHE4 0x004001E0
+#define NV10_PGRAPH_CTX_CACHE5 0x004001E0
+#define NV40_PGRAPH_UNK220 0x00400220
+# define NV40_PGRAPH_UNK220_FB_INSTANCE 0xFFFFFFFF
+#define NV03_PGRAPH_ABS_X_RAM 0x00400400
+#define NV03_PGRAPH_ABS_Y_RAM 0x00400480
+#define NV03_PGRAPH_X_MISC 0x00400500
+#define NV03_PGRAPH_Y_MISC 0x00400504
+#define NV04_PGRAPH_VALID1 0x00400508
+#define NV04_PGRAPH_SOURCE_COLOR 0x0040050C
+#define NV04_PGRAPH_MISC24_0 0x00400510
+#define NV03_PGRAPH_XY_LOGIC_MISC0 0x00400514
+#define NV03_PGRAPH_XY_LOGIC_MISC1 0x00400518
+#define NV03_PGRAPH_XY_LOGIC_MISC2 0x0040051C
+#define NV03_PGRAPH_XY_LOGIC_MISC3 0x00400520
+#define NV03_PGRAPH_CLIPX_0 0x00400524
+#define NV03_PGRAPH_CLIPX_1 0x00400528
+#define NV03_PGRAPH_CLIPY_0 0x0040052C
+#define NV03_PGRAPH_CLIPY_1 0x00400530
+#define NV03_PGRAPH_ABS_ICLIP_XMAX 0x00400534
+#define NV03_PGRAPH_ABS_ICLIP_YMAX 0x00400538
+#define NV03_PGRAPH_ABS_UCLIP_XMIN 0x0040053C
+#define NV03_PGRAPH_ABS_UCLIP_YMIN 0x00400540
+#define NV03_PGRAPH_ABS_UCLIP_XMAX 0x00400544
+#define NV03_PGRAPH_ABS_UCLIP_YMAX 0x00400548
+#define NV03_PGRAPH_ABS_UCLIPA_XMIN 0x00400560
+#define NV03_PGRAPH_ABS_UCLIPA_YMIN 0x00400564
+#define NV03_PGRAPH_ABS_UCLIPA_XMAX 0x00400568
+#define NV03_PGRAPH_ABS_UCLIPA_YMAX 0x0040056C
+#define NV04_PGRAPH_MISC24_1 0x00400570
+#define NV04_PGRAPH_MISC24_2 0x00400574
+#define NV04_PGRAPH_VALID2 0x00400578
+#define NV04_PGRAPH_PASSTHRU_0 0x0040057C
+#define NV04_PGRAPH_PASSTHRU_1 0x00400580
+#define NV04_PGRAPH_PASSTHRU_2 0x00400584
+#define NV10_PGRAPH_DIMX_TEXTURE 0x00400588
+#define NV10_PGRAPH_WDIMX_TEXTURE 0x0040058C
+#define NV04_PGRAPH_COMBINE_0_ALPHA 0x00400590
+#define NV04_PGRAPH_COMBINE_0_COLOR 0x00400594
+#define NV04_PGRAPH_COMBINE_1_ALPHA 0x00400598
+#define NV04_PGRAPH_COMBINE_1_COLOR 0x0040059C
+#define NV04_PGRAPH_FORMAT_0 0x004005A8
+#define NV04_PGRAPH_FORMAT_1 0x004005AC
+#define NV04_PGRAPH_FILTER_0 0x004005B0
+#define NV04_PGRAPH_FILTER_1 0x004005B4
+#define NV03_PGRAPH_MONO_COLOR0 0x00400600
+#define NV04_PGRAPH_ROP3 0x00400604
+#define NV04_PGRAPH_BETA_AND 0x00400608
+#define NV04_PGRAPH_BETA_PREMULT 0x0040060C
+#define NV04_PGRAPH_FORMATS 0x00400618
+#define NV04_PGRAPH_BOFFSET0 0x00400640
+#define NV04_PGRAPH_BOFFSET1 0x00400644
+#define NV04_PGRAPH_BOFFSET2 0x00400648
+#define NV04_PGRAPH_BOFFSET3 0x0040064C
+#define NV04_PGRAPH_BOFFSET4 0x00400650
+#define NV04_PGRAPH_BOFFSET5 0x00400654
+#define NV04_PGRAPH_BBASE0 0x00400658
+#define NV04_PGRAPH_BBASE1 0x0040065C
+#define NV04_PGRAPH_BBASE2 0x00400660
+#define NV04_PGRAPH_BBASE3 0x00400664
+#define NV04_PGRAPH_BBASE4 0x00400668
+#define NV04_PGRAPH_BBASE5 0x0040066C
+#define NV04_PGRAPH_BPITCH0 0x00400670
+#define NV04_PGRAPH_BPITCH1 0x00400674
+#define NV04_PGRAPH_BPITCH2 0x00400678
+#define NV04_PGRAPH_BPITCH3 0x0040067C
+#define NV04_PGRAPH_BPITCH4 0x00400680
+#define NV04_PGRAPH_BLIMIT0 0x00400684
+#define NV04_PGRAPH_BLIMIT1 0x00400688
+#define NV04_PGRAPH_BLIMIT2 0x0040068C
+#define NV04_PGRAPH_BLIMIT3 0x00400690
+#define NV04_PGRAPH_BLIMIT4 0x00400694
+#define NV04_PGRAPH_BLIMIT5 0x00400698
+#define NV04_PGRAPH_BSWIZZLE2 0x0040069C
+#define NV04_PGRAPH_BSWIZZLE5 0x004006A0
+#define NV04_PGRAPH_SURFACE 0x0040070C
+#define NV04_PGRAPH_STATE 0x00400710
+#define NV10_PGRAPH_SURFACE 0x00400710
+#define NV04_PGRAPH_NOTIFY 0x00400714
+#define NV10_PGRAPH_STATE 0x00400714
+#define NV10_PGRAPH_NOTIFY 0x00400718
-#define NV_PGRAPH_FIFO 0x00400720
+#define NV04_PGRAPH_FIFO 0x00400720
+
+#define NV04_PGRAPH_BPIXEL 0x00400724
+#define NV10_PGRAPH_RDI_INDEX 0x00400750
+#define NV04_PGRAPH_FFINTFC_ST2 0x00400754
+#define NV10_PGRAPH_RDI_DATA 0x00400754
+#define NV04_PGRAPH_DMA_PITCH 0x00400760
+#define NV10_PGRAPH_FFINTFC_ST2 0x00400764
+#define NV04_PGRAPH_DVD_COLORFMT 0x00400764
+#define NV04_PGRAPH_SCALED_FORMAT 0x00400768
+#define NV10_PGRAPH_DMA_PITCH 0x00400770
+#define NV10_PGRAPH_DVD_COLORFMT 0x00400774
+#define NV10_PGRAPH_SCALED_FORMAT 0x00400778
+#define NV10_PGRAPH_CHANNEL_CTX_TABLE 0x00400780
+#define NV10_PGRAPH_CHANNEL_CTX_SIZE 0x00400784
+#define NV10_PGRAPH_CHANNEL_CTX_POINTER 0x00400788
+#define NV04_PGRAPH_PATT_COLOR0 0x00400800
+#define NV04_PGRAPH_PATT_COLOR1 0x00400804
+#define NV04_PGRAPH_PATTERN 0x00400808
+#define NV04_PGRAPH_PATTERN_SHAPE 0x00400810
+#define NV04_PGRAPH_CHROMA 0x00400814
+#define NV04_PGRAPH_CONTROL0 0x00400818
+#define NV04_PGRAPH_CONTROL1 0x0040081C
+#define NV04_PGRAPH_CONTROL2 0x00400820
+#define NV04_PGRAPH_BLEND 0x00400824
+#define NV04_PGRAPH_STORED_FMT 0x00400830
+#define NV04_PGRAPH_PATT_COLORRAM 0x00400900
+#define NV04_PGRAPH_U_RAM 0x00400D00
+#define NV04_PGRAPH_V_RAM 0x00400D40
+#define NV04_PGRAPH_W_RAM 0x00400D80
+#define NV10_PGRAPH_WINDOWCLIP_HORIZONTAL 0x00400F00
+#define NV10_PGRAPH_WINDOWCLIP_VERTICAL 0x00400F20
+#define NV10_PGRAPH_XFMODE0 0x00400F40
+#define NV10_PGRAPH_XFMODE1 0x00400F44
+#define NV10_PGRAPH_GLOBALSTATE0 0x00400F48
+#define NV10_PGRAPH_GLOBALSTATE1 0x00400F4C
+#define NV10_PGRAPH_PIPE_ADDRESS 0x00400F50
+#define NV10_PGRAPH_PIPE_DATA 0x00400F54
+#define NV04_PGRAPH_DMA_START_0 0x00401000
+#define NV04_PGRAPH_DMA_START_1 0x00401004
+#define NV04_PGRAPH_DMA_LENGTH 0x00401008
+#define NV04_PGRAPH_DMA_MISC 0x0040100C
+#define NV04_PGRAPH_DMA_DATA_0 0x00401020
+#define NV04_PGRAPH_DMA_DATA_1 0x00401024
+#define NV04_PGRAPH_DMA_RM 0x00401030
+#define NV04_PGRAPH_DMA_A_XLATE_INST 0x00401040
+#define NV04_PGRAPH_DMA_A_CONTROL 0x00401044
+#define NV04_PGRAPH_DMA_A_LIMIT 0x00401048
+#define NV04_PGRAPH_DMA_A_TLB_PTE 0x0040104C
+#define NV04_PGRAPH_DMA_A_TLB_TAG 0x00401050
+#define NV04_PGRAPH_DMA_A_ADJ_OFFSET 0x00401054
+#define NV04_PGRAPH_DMA_A_OFFSET 0x00401058
+#define NV04_PGRAPH_DMA_A_SIZE 0x0040105C
+#define NV04_PGRAPH_DMA_A_Y_SIZE 0x00401060
+#define NV04_PGRAPH_DMA_B_XLATE_INST 0x00401080
+#define NV04_PGRAPH_DMA_B_CONTROL 0x00401084
+#define NV04_PGRAPH_DMA_B_LIMIT 0x00401088
+#define NV04_PGRAPH_DMA_B_TLB_PTE 0x0040108C
+#define NV04_PGRAPH_DMA_B_TLB_TAG 0x00401090
+#define NV04_PGRAPH_DMA_B_ADJ_OFFSET 0x00401094
+#define NV04_PGRAPH_DMA_B_OFFSET 0x00401098
+#define NV04_PGRAPH_DMA_B_SIZE 0x0040109C
+#define NV04_PGRAPH_DMA_B_Y_SIZE 0x004010A0
-#define NV_PGRAPH_BPIXEL 0x00400724
-#define NV_PGRAPH_RDI_INDEX 0x00400750
-#define NV_PGRAPH_RDI_DATA 0x00400754
-#define NV_PGRAPH_FFINTFC_ST2 0x00400764
-#define NV_PGRAPH_DMA_PITCH 0x00400770
-#define NV_PGRAPH_DVD_COLORFMT 0x00400774
-#define NV_PGRAPH_SCALED_FORMAT 0x00400778
-#define NV_PGRAPH_CHANNEL_CTX_TABLE 0x00400780
-#define NV_PGRAPH_CHANNEL_CTX_SIZE 0x00400784
-#define NV_PGRAPH_CHANNEL_CTX_POINTER 0x00400788
-#define NV_PGRAPH_PATT_COLOR0 0x00400800
-#define NV_PGRAPH_PATT_COLOR1 0x00400804
-#define NV_PGRAPH_PATTERN_SHAPE 0x00400810
-#define NV_PGRAPH_CHROMA 0x00400814
-#define NV_PGRAPH_STORED_FMT 0x00400830
-#define NV_PGRAPH_XFMODE0 0x00400F40
-#define NV_PGRAPH_XFMODE1 0x00400F44
-#define NV_PGRAPH_GLOBALSTATE0 0x00400F48
-#define NV_PGRAPH_GLOBALSTATE1 0x00400F4C
-#define NV_PGRAPH_PIPE_ADDRESS 0x00400F50
-#define NV_PGRAPH_PIPE_DATA 0x00400F54
-#define NV_PGRAPH_DMA_START_0 0x00401000
-#define NV_PGRAPH_DMA_START_1 0x00401004
-#define NV_PGRAPH_DMA_LENGTH 0x00401008
-#define NV_PGRAPH_DMA_MISC 0x0040100C
/* It's a guess that this works on NV03. Confirmed on NV04, though */
-#define NV_PFIFO_DELAY_0 0x00002040
-#define NV_PFIFO_DMA_TIMESLICE 0x00002044
-#define NV_PFIFO_INTSTAT 0x00002100
-#define NV_PFIFO_INTEN 0x00002140
+#define NV04_PFIFO_DELAY_0 0x00002040
+#define NV04_PFIFO_DMA_TIMESLICE 0x00002044
+#define NV04_PFIFO_NEXT_CHANNEL 0x00002050
+#define NV03_PFIFO_INTR_0 0x00002100
+#define NV03_PFIFO_INTR_EN_0 0x00002140
# define NV_PFIFO_INTR_CACHE_ERROR (1<< 0)
# define NV_PFIFO_INTR_RUNOUT (1<< 4)
# define NV_PFIFO_INTR_RUNOUT_OVERFLOW (1<< 8)
@@ -177,105 +246,108 @@
# define NV_PFIFO_INTR_DMA_PT (1<<16)
# define NV_PFIFO_INTR_SEMAPHORE (1<<20)
# define NV_PFIFO_INTR_ACQUIRE_TIMEOUT (1<<24)
-#define NV_PFIFO_RAMHT 0x00002210
-#define NV_PFIFO_RAMFC 0x00002214
-#define NV_PFIFO_RAMRO 0x00002218
+#define NV03_PFIFO_RAMHT 0x00002210
+#define NV03_PFIFO_RAMFC 0x00002214
+#define NV03_PFIFO_RAMRO 0x00002218
#define NV40_PFIFO_RAMFC 0x00002220
-#define NV_PFIFO_CACHES 0x00002500
-#define NV_PFIFO_MODE 0x00002504
-#define NV_PFIFO_DMA 0x00002508
-#define NV_PFIFO_SIZE 0x0000250c
-#define NV_PFIFO_CACH0_PSH0 0x00003000
-#define NV_PFIFO_CACH0_PUL0 0x00003050
-#define NV_PFIFO_CACH0_PUL1 0x00003054
-#define NV_PFIFO_CACH1_PSH0 0x00003200
-#define NV_PFIFO_CACH1_PSH1 0x00003204
-#define NV_PFIFO_CACH1_DMAPSH 0x00003220
-#define NV_PFIFO_CACH1_DMAF 0x00003224
-# define NV_PFIFO_CACH1_DMAF_TRIG_8_BYTES 0x00000000
-# define NV_PFIFO_CACH1_DMAF_TRIG_16_BYTES 0x00000008
-# define NV_PFIFO_CACH1_DMAF_TRIG_24_BYTES 0x00000010
-# define NV_PFIFO_CACH1_DMAF_TRIG_32_BYTES 0x00000018
-# define NV_PFIFO_CACH1_DMAF_TRIG_40_BYTES 0x00000020
-# define NV_PFIFO_CACH1_DMAF_TRIG_48_BYTES 0x00000028
-# define NV_PFIFO_CACH1_DMAF_TRIG_56_BYTES 0x00000030
-# define NV_PFIFO_CACH1_DMAF_TRIG_64_BYTES 0x00000038
-# define NV_PFIFO_CACH1_DMAF_TRIG_72_BYTES 0x00000040
-# define NV_PFIFO_CACH1_DMAF_TRIG_80_BYTES 0x00000048
-# define NV_PFIFO_CACH1_DMAF_TRIG_88_BYTES 0x00000050
-# define NV_PFIFO_CACH1_DMAF_TRIG_96_BYTES 0x00000058
-# define NV_PFIFO_CACH1_DMAF_TRIG_104_BYTES 0x00000060
-# define NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES 0x00000068
-# define NV_PFIFO_CACH1_DMAF_TRIG_120_BYTES 0x00000070
-# define NV_PFIFO_CACH1_DMAF_TRIG_128_BYTES 0x00000078
-# define NV_PFIFO_CACH1_DMAF_TRIG_136_BYTES 0x00000080
-# define NV_PFIFO_CACH1_DMAF_TRIG_144_BYTES 0x00000088
-# define NV_PFIFO_CACH1_DMAF_TRIG_152_BYTES 0x00000090
-# define NV_PFIFO_CACH1_DMAF_TRIG_160_BYTES 0x00000098
-# define NV_PFIFO_CACH1_DMAF_TRIG_168_BYTES 0x000000A0
-# define NV_PFIFO_CACH1_DMAF_TRIG_176_BYTES 0x000000A8
-# define NV_PFIFO_CACH1_DMAF_TRIG_184_BYTES 0x000000B0
-# define NV_PFIFO_CACH1_DMAF_TRIG_192_BYTES 0x000000B8
-# define NV_PFIFO_CACH1_DMAF_TRIG_200_BYTES 0x000000C0
-# define NV_PFIFO_CACH1_DMAF_TRIG_208_BYTES 0x000000C8
-# define NV_PFIFO_CACH1_DMAF_TRIG_216_BYTES 0x000000D0
-# define NV_PFIFO_CACH1_DMAF_TRIG_224_BYTES 0x000000D8
-# define NV_PFIFO_CACH1_DMAF_TRIG_232_BYTES 0x000000E0
-# define NV_PFIFO_CACH1_DMAF_TRIG_240_BYTES 0x000000E8
-# define NV_PFIFO_CACH1_DMAF_TRIG_248_BYTES 0x000000F0
-# define NV_PFIFO_CACH1_DMAF_TRIG_256_BYTES 0x000000F8
-# define NV_PFIFO_CACH1_DMAF_SIZE 0x0000E000
-# define NV_PFIFO_CACH1_DMAF_SIZE_32_BYTES 0x00000000
-# define NV_PFIFO_CACH1_DMAF_SIZE_64_BYTES 0x00002000
-# define NV_PFIFO_CACH1_DMAF_SIZE_96_BYTES 0x00004000
-# define NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES 0x00006000
-# define NV_PFIFO_CACH1_DMAF_SIZE_160_BYTES 0x00008000
-# define NV_PFIFO_CACH1_DMAF_SIZE_192_BYTES 0x0000A000
-# define NV_PFIFO_CACH1_DMAF_SIZE_224_BYTES 0x0000C000
-# define NV_PFIFO_CACH1_DMAF_SIZE_256_BYTES 0x0000E000
-# define NV_PFIFO_CACH1_DMAF_MAX_REQS 0x001F0000
-# define NV_PFIFO_CACH1_DMAF_MAX_REQS_0 0x00000000
-# define NV_PFIFO_CACH1_DMAF_MAX_REQS_1 0x00010000
-# define NV_PFIFO_CACH1_DMAF_MAX_REQS_2 0x00020000
-# define NV_PFIFO_CACH1_DMAF_MAX_REQS_3 0x00030000
-# define NV_PFIFO_CACH1_DMAF_MAX_REQS_4 0x00040000
-# define NV_PFIFO_CACH1_DMAF_MAX_REQS_5 0x00050000
-# define NV_PFIFO_CACH1_DMAF_MAX_REQS_6 0x00060000
-# define NV_PFIFO_CACH1_DMAF_MAX_REQS_7 0x00070000
-# define NV_PFIFO_CACH1_DMAF_MAX_REQS_8 0x00080000
-# define NV_PFIFO_CACH1_DMAF_MAX_REQS_9 0x00090000
-# define NV_PFIFO_CACH1_DMAF_MAX_REQS_10 0x000A0000
-# define NV_PFIFO_CACH1_DMAF_MAX_REQS_11 0x000B0000
-# define NV_PFIFO_CACH1_DMAF_MAX_REQS_12 0x000C0000
-# define NV_PFIFO_CACH1_DMAF_MAX_REQS_13 0x000D0000
-# define NV_PFIFO_CACH1_DMAF_MAX_REQS_14 0x000E0000
-# define NV_PFIFO_CACH1_DMAF_MAX_REQS_15 0x000F0000
-# define NV_PFIFO_CACH1_ENDIAN 0x80000000
-# define NV_PFIFO_CACH1_LITTLE_ENDIAN 0x7FFFFFFF
-# define NV_PFIFO_CACH1_BIG_ENDIAN 0x80000000
-#define NV_PFIFO_CACH1_DMAS 0x00003228
-#define NV_PFIFO_CACH1_DMAI 0x0000322c
-#define NV_PFIFO_CACH1_DMAC 0x00003230
-#define NV_PFIFO_CACH1_DMAP 0x00003240
-#define NV_PFIFO_CACH1_DMAG 0x00003244
-#define NV_PFIFO_CACH1_REF_CNT 0x00003248
-#define NV_PFIFO_CACH1_DMASR 0x0000324C
-#define NV_PFIFO_CACH1_PUL0 0x00003250
-#define NV_PFIFO_CACH1_PUL1 0x00003254
-#define NV_PFIFO_CACH1_HASH 0x00003258
-#define NV_PFIFO_CACH1_ACQUIRE_TIMEOUT 0x00003260
-#define NV_PFIFO_CACH1_ACQUIRE_TIMESTAMP 0x00003264
-#define NV_PFIFO_CACH1_ACQUIRE_VALUE 0x00003268
-#define NV_PFIFO_CACH1_SEMAPHORE 0x0000326C
-#define NV_PFIFO_CACH1_GET 0x00003270
-#define NV_PFIFO_CACH1_ENG 0x00003280
-#define NV_PFIFO_CACH1_DMA_DCOUNT 0x000032A0
+#define NV03_PFIFO_CACHES 0x00002500
+#define NV04_PFIFO_MODE 0x00002504
+#define NV04_PFIFO_DMA 0x00002508
+#define NV04_PFIFO_SIZE 0x0000250c
+#define NV03_PFIFO_CACHE0_PUSH0 0x00003000
+#define NV03_PFIFO_CACHE0_PULL0 0x00003040
+#define NV04_PFIFO_CACHE0_PULL0 0x00003050
+#define NV04_PFIFO_CACHE0_PULL1 0x00003054
+#define NV03_PFIFO_CACHE1_PUSH0 0x00003200
+#define NV03_PFIFO_CACHE1_PUSH1 0x00003204
+#define NV04_PFIFO_CACHE1_DMA_PUSH 0x00003220
+#define NV04_PFIFO_CACHE1_DMA_FETCH 0x00003224
+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_8_BYTES 0x00000000
+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_16_BYTES 0x00000008
+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_24_BYTES 0x00000010
+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_32_BYTES 0x00000018
+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_40_BYTES 0x00000020
+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_48_BYTES 0x00000028
+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_56_BYTES 0x00000030
+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_64_BYTES 0x00000038
+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_72_BYTES 0x00000040
+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_80_BYTES 0x00000048
+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_88_BYTES 0x00000050
+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_96_BYTES 0x00000058
+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_104_BYTES 0x00000060
+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES 0x00000068
+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_120_BYTES 0x00000070
+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES 0x00000078
+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_136_BYTES 0x00000080
+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_144_BYTES 0x00000088
+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_152_BYTES 0x00000090
+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_160_BYTES 0x00000098
+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_168_BYTES 0x000000A0
+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_176_BYTES 0x000000A8
+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_184_BYTES 0x000000B0
+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_192_BYTES 0x000000B8
+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_200_BYTES 0x000000C0
+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_208_BYTES 0x000000C8
+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_216_BYTES 0x000000D0
+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_224_BYTES 0x000000D8
+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_232_BYTES 0x000000E0
+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_240_BYTES 0x000000E8
+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_248_BYTES 0x000000F0
+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_256_BYTES 0x000000F8
+# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE 0x0000E000
+# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_32_BYTES 0x00000000
+# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_64_BYTES 0x00002000
+# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_96_BYTES 0x00004000
+# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES 0x00006000
+# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_160_BYTES 0x00008000
+# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_192_BYTES 0x0000A000
+# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_224_BYTES 0x0000C000
+# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_256_BYTES 0x0000E000
+# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS 0x001F0000
+# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_0 0x00000000
+# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_1 0x00010000
+# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_2 0x00020000
+# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_3 0x00030000
+# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4 0x00040000
+# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_5 0x00050000
+# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_6 0x00060000
+# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_7 0x00070000
+# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 0x00080000
+# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_9 0x00090000
+# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_10 0x000A0000
+# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_11 0x000B0000
+# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_12 0x000C0000
+# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_13 0x000D0000
+# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_14 0x000E0000
+# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_15 0x000F0000
+# define NV_PFIFO_CACHE1_ENDIAN 0x80000000
+# define NV_PFIFO_CACHE1_LITTLE_ENDIAN 0x7FFFFFFF
+# define NV_PFIFO_CACHE1_BIG_ENDIAN 0x80000000
+#define NV04_PFIFO_CACHE1_DMA_STATE 0x00003228
+#define NV04_PFIFO_CACHE1_DMA_INSTANCE 0x0000322c
+#define NV04_PFIFO_CACHE1_DMA_CTL 0x00003230
+#define NV04_PFIFO_CACHE1_DMA_PUT 0x00003240
+#define NV04_PFIFO_CACHE1_DMA_GET 0x00003244
+#define NV10_PFIFO_CACHE1_REF_CNT 0x00003248
+#define NV10_PFIFO_CACHE1_DMA_SUBROUTINE 0x0000324C
+#define NV03_PFIFO_CACHE1_PULL0 0x00003240
+#define NV04_PFIFO_CACHE1_PULL0 0x00003250
+#define NV03_PFIFO_CACHE1_PULL1 0x00003250
+#define NV04_PFIFO_CACHE1_PULL1 0x00003254
+#define NV04_PFIFO_CACHE1_HASH 0x00003258
+#define NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT 0x00003260
+#define NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP 0x00003264
+#define NV10_PFIFO_CACHE1_ACQUIRE_VALUE 0x00003268
+#define NV10_PFIFO_CACHE1_SEMAPHORE 0x0000326C
+#define NV03_PFIFO_CACHE1_GET 0x00003270
+#define NV04_PFIFO_CACHE1_ENGINE 0x00003280
+#define NV10_PFIFO_CACHE1_DMA_DCOUNT 0x000032A0
#define NV40_PFIFO_GRCTX_INSTANCE 0x000032E0
#define NV40_PFIFO_UNK32E4 0x000032E4
-#define NV_PFIFO_CACH1_METHOD(i) (0x00003800+(i*8))
-#define NV_PFIFO_CACH1_DATA(i) (0x00003804+(i*8))
-#define NV40_PFIFO_CACH1_METHOD(i) (0x00090000+(i*8))
-#define NV40_PFIFO_CACH1_DATA(i) (0x00090004+(i*8))
+#define NV04_PFIFO_CACHE1_METHOD(i) (0x00003800+(i*8))
+#define NV04_PFIFO_CACHE1_DATA(i) (0x00003804+(i*8))
+#define NV40_PFIFO_CACHE1_METHOD(i) (0x00090000+(i*8))
+#define NV40_PFIFO_CACHE1_DATA(i) (0x00090004+(i*8))
#define NV_CRTC0_INTSTAT 0x00600100
#define NV_CRTC0_INTEN 0x00600140
diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c
index fb35ba74..f1f272e7 100644
--- a/shared-core/nouveau_state.c
+++ b/shared-core/nouveau_state.c
@@ -83,6 +83,12 @@ int nouveau_firstopen(struct drm_device *dev)
} else
dev_priv->ramin = NULL;
+ /* Determine exact chipset we're running on */
+ if (dev_priv->card_type < NV_10)
+ dev_priv->chipset = dev_priv->card_type;
+ else
+ dev_priv->chipset =(NV_READ(NV03_PMC_BOOT_0) & 0x0ff00000) >> 20;
+
/* Clear RAMIN
* Determine locations for RAMHT/FC/RO
* Initialise PFIFO
@@ -102,6 +108,8 @@ int nouveau_firstopen(struct drm_device *dev)
nv20_graph_init(dev);
else if (dev_priv->card_type >= NV_10)
nv10_graph_init(dev);
+ else if (dev_priv->card_type >= NV_04)
+ nv04_graph_init(dev);
return 0;
}
diff --git a/shared-core/nv04_graph.c b/shared-core/nv04_graph.c
new file mode 100644
index 00000000..830d673e
--- /dev/null
+++ b/shared-core/nv04_graph.c
@@ -0,0 +1,234 @@
+/*
+ * Copyright 2007 Stephane Marchesin
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include "drmP.h"
+#include "drm.h"
+#include "nouveau_drm.h"
+#include "nouveau_drv.h"
+
+struct reg_interval
+{
+ uint32_t reg;
+ int number;
+} nv04_graph_ctx_regs [] = {
+ {NV04_PGRAPH_CTX_SWITCH1, 1},
+ {NV04_PGRAPH_CTX_SWITCH2, 1},
+ {NV04_PGRAPH_CTX_SWITCH3, 1},
+ {NV04_PGRAPH_CTX_SWITCH4, 1},
+ {NV04_PGRAPH_CTX_USER, 1},
+ {NV04_PGRAPH_CTX_CACHE1, 8},
+ {NV04_PGRAPH_CTX_CACHE2, 8},
+ {NV04_PGRAPH_CTX_CACHE3, 8},
+ {NV04_PGRAPH_CTX_CACHE4, 8},
+ {NV03_PGRAPH_ABS_X_RAM, 32},
+ {NV03_PGRAPH_ABS_Y_RAM, 32},
+ {NV03_PGRAPH_X_MISC, 1},
+ {NV03_PGRAPH_Y_MISC, 1},
+ {NV04_PGRAPH_VALID1, 1},
+ {NV04_PGRAPH_SOURCE_COLOR, 1},
+ {NV04_PGRAPH_MISC24_0, 1},
+ {NV03_PGRAPH_XY_LOGIC_MISC0, 1},
+ {NV03_PGRAPH_XY_LOGIC_MISC1, 1},
+ {NV03_PGRAPH_XY_LOGIC_MISC2, 1},
+ {NV03_PGRAPH_XY_LOGIC_MISC3, 1},
+ {NV03_PGRAPH_CLIPX_0, 1},
+ {NV03_PGRAPH_CLIPX_1, 1},
+ {NV03_PGRAPH_CLIPY_0, 1},
+ {NV03_PGRAPH_CLIPY_1, 1},
+ {NV03_PGRAPH_ABS_ICLIP_XMAX, 1},
+ {NV03_PGRAPH_ABS_ICLIP_YMAX, 1},
+ {NV03_PGRAPH_ABS_UCLIP_XMIN, 1},
+ {NV03_PGRAPH_ABS_UCLIP_YMIN, 1},
+ {NV03_PGRAPH_ABS_UCLIP_XMAX, 1},
+ {NV03_PGRAPH_ABS_UCLIP_YMAX, 1},
+ {NV03_PGRAPH_ABS_UCLIPA_XMIN, 1},
+ {NV03_PGRAPH_ABS_UCLIPA_YMIN, 1},
+ {NV03_PGRAPH_ABS_UCLIPA_XMAX, 1},
+ {NV03_PGRAPH_ABS_UCLIPA_YMAX, 1},
+ {NV04_PGRAPH_MISC24_1, 1},
+ {NV04_PGRAPH_MISC24_2, 1},
+ {NV04_PGRAPH_VALID2, 1},
+ {NV04_PGRAPH_PASSTHRU_0, 1},
+ {NV04_PGRAPH_PASSTHRU_1, 1},
+ {NV04_PGRAPH_PASSTHRU_2, 1},
+ {NV04_PGRAPH_COMBINE_0_ALPHA, 1},
+ {NV04_PGRAPH_COMBINE_0_COLOR, 1},
+ {NV04_PGRAPH_COMBINE_1_ALPHA, 1},
+ {NV04_PGRAPH_COMBINE_1_COLOR, 1},
+ // texture state
+ {NV04_PGRAPH_FORMAT_0, 1},
+ {NV04_PGRAPH_FORMAT_1, 1},
+ {NV04_PGRAPH_FILTER_0, 1},
+ {NV04_PGRAPH_FILTER_1, 1},
+ // vertex state
+ {0x004005c0, 1},
+ {0x004005c4, 1},
+ {0x004005c8, 1},
+ {0x004005cc, 1},
+ {0x004005d0, 1},
+ {0x004005d4, 1},
+ {0x004005d8, 1},
+ {0x004005dc, 1},
+ {0x004005e0, 1},
+ {NV03_PGRAPH_MONO_COLOR0, 1},
+ {NV04_PGRAPH_ROP3, 1},
+ {NV04_PGRAPH_BETA_AND, 1},
+ {NV04_PGRAPH_BETA_PREMULT, 1},
+ {NV04_PGRAPH_FORMATS, 1},
+ {NV04_PGRAPH_BOFFSET0, 6},
+ {NV04_PGRAPH_BBASE0, 6},
+ {NV04_PGRAPH_BPITCH0, 5},
+ {NV04_PGRAPH_BLIMIT0, 6},
+ {NV04_PGRAPH_BSWIZZLE2, 1},
+ {NV04_PGRAPH_BSWIZZLE5, 1},
+ {NV04_PGRAPH_SURFACE, 1},
+ {NV04_PGRAPH_STATE, 1},
+ {NV04_PGRAPH_NOTIFY, 1},
+ {NV04_PGRAPH_BPIXEL, 1},
+ {NV04_PGRAPH_DMA_PITCH, 1},
+ {NV04_PGRAPH_DVD_COLORFMT, 1},
+ {NV04_PGRAPH_SCALED_FORMAT, 1},
+ {NV04_PGRAPH_PATT_COLOR0, 1},
+ {NV04_PGRAPH_PATT_COLOR1, 1},
+ {NV04_PGRAPH_PATTERN, 2},
+ {NV04_PGRAPH_PATTERN_SHAPE, 1},
+ {NV04_PGRAPH_CHROMA, 1},
+ {NV04_PGRAPH_CONTROL0, 1},
+ {NV04_PGRAPH_CONTROL1, 1},
+ {NV04_PGRAPH_CONTROL2, 1},
+ {NV04_PGRAPH_BLEND, 1},
+ {NV04_PGRAPH_STORED_FMT, 1},
+ {NV04_PGRAPH_PATT_COLORRAM, 64},
+ {NV04_PGRAPH_U_RAM, 16},
+ {NV04_PGRAPH_V_RAM, 16},
+ {NV04_PGRAPH_W_RAM, 16},
+ {NV04_PGRAPH_DMA_START_0, 1},
+ {NV04_PGRAPH_DMA_START_1, 1},
+ {NV04_PGRAPH_DMA_LENGTH, 1},
+ {NV04_PGRAPH_DMA_MISC, 1},
+ {NV04_PGRAPH_DMA_DATA_0, 1},
+ {NV04_PGRAPH_DMA_DATA_1, 1},
+ {NV04_PGRAPH_DMA_RM, 1},
+ {NV04_PGRAPH_DMA_A_XLATE_INST, 1},
+ {NV04_PGRAPH_DMA_A_CONTROL, 1},
+ {NV04_PGRAPH_DMA_A_LIMIT, 1},
+ {NV04_PGRAPH_DMA_A_TLB_PTE, 1},
+ {NV04_PGRAPH_DMA_A_TLB_TAG, 1},
+ {NV04_PGRAPH_DMA_A_ADJ_OFFSET, 1},
+ {NV04_PGRAPH_DMA_A_OFFSET, 1},
+ {NV04_PGRAPH_DMA_A_SIZE, 1},
+ {NV04_PGRAPH_DMA_A_Y_SIZE, 1},
+ {NV04_PGRAPH_DMA_B_XLATE_INST, 1},
+ {NV04_PGRAPH_DMA_B_CONTROL, 1},
+ {NV04_PGRAPH_DMA_B_LIMIT, 1},
+ {NV04_PGRAPH_DMA_B_TLB_PTE, 1},
+ {NV04_PGRAPH_DMA_B_TLB_TAG, 1},
+ {NV04_PGRAPH_DMA_B_ADJ_OFFSET, 1},
+ {NV04_PGRAPH_DMA_B_OFFSET, 1},
+ {NV04_PGRAPH_DMA_B_SIZE, 1},
+ {NV04_PGRAPH_DMA_B_Y_SIZE, 1},
+};
+
+void nouveau_nv04_context_switch(drm_device_t *dev)
+{
+ drm_nouveau_private_t *dev_priv = dev->dev_private;
+ int channel, channel_old, i, j, index;
+
+ channel=NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1);
+ channel_old = (NV_READ(NV04_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1);
+
+ DRM_INFO("NV: PGRAPH context switch interrupt channel %x -> %x\n",channel_old, channel);
+
+ NV_WRITE(NV03_PFIFO_CACHES, 0x0);
+ NV_WRITE(NV04_PFIFO_CACHE0_PULL0, 0x0);
+ NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x0);
+ NV_WRITE(NV04_PGRAPH_FIFO,0x0);
+
+ // save PGRAPH context
+ index=0;
+ for (i = 0; i<sizeof(nv04_graph_ctx_regs)/sizeof(nv04_graph_ctx_regs[0]); i++)
+ for (j = 0; j<nv04_graph_ctx_regs[i].number; j++)
+ {
+ dev_priv->fifos[channel_old].pgraph_ctx[index] = NV_READ(nv04_graph_ctx_regs[i].reg+j*4);
+ index++;
+ }
+
+ nouveau_wait_for_idle(dev);
+
+ NV_WRITE(NV04_PGRAPH_CTX_CONTROL, 0x10000000);
+ NV_WRITE(NV04_PGRAPH_CTX_USER, (NV_READ(NV04_PGRAPH_CTX_USER) & 0xffffff) | (0x0f << 24));
+
+ nouveau_wait_for_idle(dev);
+ // restore PGRAPH context
+ //XXX not working yet
+#if 1
+ index=0;
+ for (i = 0; i<sizeof(nv04_graph_ctx_regs)/sizeof(nv04_graph_ctx_regs[0]); i++)
+ for (j = 0; j<nv04_graph_ctx_regs[i].number; j++)
+ {
+ NV_WRITE(nv04_graph_ctx_regs[i].reg+j*4, dev_priv->fifos[channel].pgraph_ctx[index]);
+ index++;
+ }
+ nouveau_wait_for_idle(dev);
+#endif
+
+ NV_WRITE(NV04_PGRAPH_CTX_CONTROL, 0x10010100);
+ NV_WRITE(NV04_PGRAPH_CTX_USER, channel << 24);
+ NV_WRITE(NV04_PGRAPH_FFINTFC_ST2, NV_READ(NV04_PGRAPH_FFINTFC_ST2)&0xCFFFFFFF);
+
+ NV_WRITE(NV04_PGRAPH_FIFO,0x0);
+ NV_WRITE(NV04_PFIFO_CACHE0_PULL0, 0x0);
+ NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x1);
+ NV_WRITE(NV03_PFIFO_CACHES, 0x1);
+ NV_WRITE(NV04_PGRAPH_FIFO,0x1);
+}
+
+int nv04_graph_context_create(drm_device_t *dev, int channel) {
+ drm_nouveau_private_t *dev_priv = dev->dev_private;
+ DRM_DEBUG("nv04_graph_context_create %d\n", channel);
+
+ memset(dev_priv->fifos[channel].pgraph_ctx, 0, sizeof(dev_priv->fifos[channel].pgraph_ctx));
+
+ //dev_priv->fifos[channel].pgraph_ctx_user = channel << 24;
+ dev_priv->fifos[channel].pgraph_ctx[0] = 0x0001ffff;
+ /* is it really needed ??? */
+ //dev_priv->fifos[channel].pgraph_ctx[1] = NV_READ(NV_PGRAPH_DEBUG_4);
+ //dev_priv->fifos[channel].pgraph_ctx[2] = NV_READ(0x004006b0);
+
+ return 0;
+}
+
+
+int nv04_graph_init(drm_device_t *dev) {
+ drm_nouveau_private_t *dev_priv = dev->dev_private;
+
+ // check the context is big enough
+ int i,sum=0;
+ for ( i = 0 ; i<sizeof(nv04_graph_ctx_regs)/sizeof(nv04_graph_ctx_regs[0]); i++)
+ sum+=nv04_graph_ctx_regs[i].number;
+ if ( sum*4>sizeof(dev_priv->fifos[0].pgraph_ctx) )
+ DRM_ERROR("pgraph_ctx too small\n");
+ return 0;
+}
+
diff --git a/shared-core/nv10_graph.c b/shared-core/nv10_graph.c
index ccbb34de..ad74b840 100644
--- a/shared-core/nv10_graph.c
+++ b/shared-core/nv10_graph.c
@@ -34,149 +34,149 @@ static void nv10_praph_pipe(drm_device_t *dev) {
nouveau_wait_for_idle(dev);
/* XXX check haiku comments */
- NV_WRITE(NV_PGRAPH_XFMODE0, 0x10000000);
- NV_WRITE(NV_PGRAPH_XFMODE1, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x000064c0);
+ NV_WRITE(NV10_PGRAPH_XFMODE0, 0x10000000);
+ NV_WRITE(NV10_PGRAPH_XFMODE1, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x000064c0);
for (i = 0; i < 4; i++)
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f800000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000);
for (i = 0; i < 4; i++)
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00006ab0);
+ NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00006ab0);
for (i = 0; i < 3; i++)
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f800000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000);
- NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00006a80);
+ NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00006a80);
for (i = 0; i < 3; i++)
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00000040);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000008);
+ NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00000040);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000008);
- NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00000200);
+ NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00000200);
for (i = 0; i < 48; i++)
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
nouveau_wait_for_idle(dev);
- NV_WRITE(NV_PGRAPH_XFMODE0, 0x00000000);
- NV_WRITE(NV_PGRAPH_XFMODE1, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00006400);
+ NV_WRITE(NV10_PGRAPH_XFMODE0, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_XFMODE1, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00006400);
for (i = 0; i < 211; i++)
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
-
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f800000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x40000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x40000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x40000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x40000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f800000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f800000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f800000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f800000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f800000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f800000);
-
- NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00006800);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x40000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x40000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x40000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x40000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000);
+
+ NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00006800);
for (i = 0; i < 162; i++)
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f800000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000);
for (i = 0; i < 25; i++)
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
-
- NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00006c00);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0xbf800000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00007000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x7149f2ca);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x7149f2ca);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x7149f2ca);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x7149f2ca);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x7149f2ca);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x7149f2ca);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x7149f2ca);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x7149f2ca);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+
+ NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00006c00);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0xbf800000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00007000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x7149f2ca);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x7149f2ca);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x7149f2ca);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x7149f2ca);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x7149f2ca);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x7149f2ca);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x7149f2ca);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x7149f2ca);
for (i = 0; i < 35; i++)
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00007400);
+ NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00007400);
for (i = 0; i < 48; i++)
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00007800);
+ NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00007800);
for (i = 0; i < 48; i++)
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00004400);
+ NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00004400);
for (i = 0; i < 32; i++)
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00000000);
for (i = 0; i < 16; i++)
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
- NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00000040);
+ NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00000040);
for (i = 0; i < 4; i++)
- NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
nouveau_wait_for_idle(dev);
}
@@ -184,20 +184,18 @@ static void nv10_praph_pipe(drm_device_t *dev) {
/* TODO replace address with name
use loops */
static int nv10_graph_ctx_regs [] = {
-NV_PGRAPH_XY_LOGIC_MISC0,
-NV_PGRAPH_DEBUG_4,
-0x004006b0,
-
-NV_PGRAPH_CTX_SWITCH1,
-NV_PGRAPH_CTX_SWITCH2,
-NV_PGRAPH_CTX_SWITCH3,
-NV_PGRAPH_CTX_SWITCH4,
-NV_PGRAPH_CTX_SWITCH5,
-0x00400160,
-0x00400180,
-0x004001a0,
-0x004001c0,
-0x004001e0,
+NV03_PGRAPH_XY_LOGIC_MISC0,
+
+//NV10_PGRAPH_CTX_SWITCH1, make ctx switch crash
+NV10_PGRAPH_CTX_SWITCH2,
+NV10_PGRAPH_CTX_SWITCH3,
+NV10_PGRAPH_CTX_SWITCH4,
+NV10_PGRAPH_CTX_SWITCH5,
+NV10_PGRAPH_CTX_CACHE1, /* 8 values from 0x400160 to 0x40017c */
+NV10_PGRAPH_CTX_CACHE2, /* 8 values from 0x400180 to 0x40019c */
+NV10_PGRAPH_CTX_CACHE3, /* 8 values from 0x4001a0 to 0x4001bc */
+NV10_PGRAPH_CTX_CACHE4, /* 8 values from 0x4001c0 to 0x4001dc */
+NV10_PGRAPH_CTX_CACHE5, /* 8 values from 0x4001e0 to 0x4001fc */
0x00400164,
0x00400184,
0x004001a4,
@@ -233,44 +231,44 @@ NV_PGRAPH_CTX_SWITCH5,
0x004001bc,
0x004001dc,
0x004001fc,
-NV_PGRAPH_CTX_USER,
-NV_PGRAPH_DMA_START_0,
-NV_PGRAPH_DMA_START_1,
-NV_PGRAPH_DMA_LENGTH,
-NV_PGRAPH_DMA_MISC,
-NV_PGRAPH_DMA_PITCH,
-NV_PGRAPH_BOFFSET0,
-NV_PGRAPH_BBASE0,
-NV_PGRAPH_BLIMIT0,
-NV_PGRAPH_BOFFSET1,
-NV_PGRAPH_BBASE1,
-NV_PGRAPH_BLIMIT1,
-NV_PGRAPH_BOFFSET2,
-NV_PGRAPH_BBASE2,
-NV_PGRAPH_BLIMIT2,
-NV_PGRAPH_BOFFSET3,
-NV_PGRAPH_BBASE3,
-NV_PGRAPH_BLIMIT3,
-NV_PGRAPH_BOFFSET4,
-NV_PGRAPH_BBASE4,
-NV_PGRAPH_BLIMIT4,
-NV_PGRAPH_BOFFSET5,
-NV_PGRAPH_BBASE5,
-NV_PGRAPH_BLIMIT5,
-NV_PGRAPH_BPITCH0,
-NV_PGRAPH_BPITCH1,
-NV_PGRAPH_BPITCH2,
-NV_PGRAPH_BPITCH3,
-NV_PGRAPH_BPITCH4,
-NV_PGRAPH_SURFACE,
-NV_PGRAPH_STATE,
-NV_PGRAPH_BSWIZZLE2,
-NV_PGRAPH_BSWIZZLE5,
-NV_PGRAPH_BPIXEL,
-NV_PGRAPH_NOTIFY,
-NV_PGRAPH_PATT_COLOR0,
-NV_PGRAPH_PATT_COLOR1,
-0x00400900,
+NV10_PGRAPH_CTX_USER,
+NV04_PGRAPH_DMA_START_0,
+NV04_PGRAPH_DMA_START_1,
+NV04_PGRAPH_DMA_LENGTH,
+NV04_PGRAPH_DMA_MISC,
+NV10_PGRAPH_DMA_PITCH,
+NV04_PGRAPH_BOFFSET0,
+NV04_PGRAPH_BBASE0,
+NV04_PGRAPH_BLIMIT0,
+NV04_PGRAPH_BOFFSET1,
+NV04_PGRAPH_BBASE1,
+NV04_PGRAPH_BLIMIT1,
+NV04_PGRAPH_BOFFSET2,
+NV04_PGRAPH_BBASE2,
+NV04_PGRAPH_BLIMIT2,
+NV04_PGRAPH_BOFFSET3,
+NV04_PGRAPH_BBASE3,
+NV04_PGRAPH_BLIMIT3,
+NV04_PGRAPH_BOFFSET4,
+NV04_PGRAPH_BBASE4,
+NV04_PGRAPH_BLIMIT4,
+NV04_PGRAPH_BOFFSET5,
+NV04_PGRAPH_BBASE5,
+NV04_PGRAPH_BLIMIT5,
+NV04_PGRAPH_BPITCH0,
+NV04_PGRAPH_BPITCH1,
+NV04_PGRAPH_BPITCH2,
+NV04_PGRAPH_BPITCH3,
+NV04_PGRAPH_BPITCH4,
+NV10_PGRAPH_SURFACE,
+NV10_PGRAPH_STATE,
+NV04_PGRAPH_BSWIZZLE2,
+NV04_PGRAPH_BSWIZZLE5,
+NV04_PGRAPH_BPIXEL,
+NV10_PGRAPH_NOTIFY,
+NV04_PGRAPH_PATT_COLOR0,
+NV04_PGRAPH_PATT_COLOR1,
+NV04_PGRAPH_PATT_COLORRAM, /* 64 values from 0x400900 to 0x4009fc */
0x00400904,
0x00400908,
0x0040090c,
@@ -334,14 +332,14 @@ NV_PGRAPH_PATT_COLOR1,
0x004009f4,
0x004009f8,
0x004009fc,
-0x00400808,
+NV04_PGRAPH_PATTERN, /* 2 values from 0x400808 to 0x40080c */
0x0040080c,
-NV_PGRAPH_PATTERN_SHAPE,
-NV_PGRAPH_MONO_COLOR0,
-NV_PGRAPH_ROP3,
-NV_PGRAPH_CHROMA,
-NV_PGRAPH_BETA_AND,
-NV_PGRAPH_BETA_PREMULT,
+NV04_PGRAPH_PATTERN_SHAPE,
+NV03_PGRAPH_MONO_COLOR0,
+NV04_PGRAPH_ROP3,
+NV04_PGRAPH_CHROMA,
+NV04_PGRAPH_BETA_AND,
+NV04_PGRAPH_BETA_PREMULT,
0x00400e70,
0x00400e74,
0x00400e78,
@@ -353,28 +351,12 @@ NV_PGRAPH_BETA_PREMULT,
0x00400ea0,
0x00400ea4,
0x00400ea8,
-0x00400eac,
-0x00400eb0,
-0x00400eb4,
-0x00400eb8,
-0x00400ebc,
-0x00400ec0,
-0x00400ec4,
-0x00400ec8,
-0x00400ecc,
-0x00400ed0,
-0x00400ed4,
-0x00400ed8,
-0x00400edc,
-0x00400ee0,
-0x00400a00,
-0x00400a04,
0x00400e90,
0x00400e94,
0x00400e98,
0x00400e9c,
-0x00400f00,
-0x00400f20,
+NV10_PGRAPH_WINDOWCLIP_HORIZONTAL, /* 8 values from 0x400f00 to 0x400f1c */
+NV10_PGRAPH_WINDOWCLIP_VERTICAL, /* 8 values from 0x400f20 to 0x400f3c */
0x00400f04,
0x00400f24,
0x00400f08,
@@ -389,14 +371,14 @@ NV_PGRAPH_BETA_PREMULT,
0x00400f38,
0x00400f1c,
0x00400f3c,
-NV_PGRAPH_XFMODE0,
-NV_PGRAPH_XFMODE1,
-NV_PGRAPH_GLOBALSTATE0,
-NV_PGRAPH_GLOBALSTATE1,
-NV_PGRAPH_STORED_FMT,
-NV_PGRAPH_SOURCE_COLOR,
-0x00400400,
-0x00400480,
+NV10_PGRAPH_XFMODE0,
+NV10_PGRAPH_XFMODE1,
+NV10_PGRAPH_GLOBALSTATE0,
+NV10_PGRAPH_GLOBALSTATE1,
+NV04_PGRAPH_STORED_FMT,
+NV04_PGRAPH_SOURCE_COLOR,
+NV03_PGRAPH_ABS_X_RAM, /* 32 values from 0x400400 to 0x40047c */
+NV03_PGRAPH_ABS_Y_RAM, /* 32 values from 0x400480 to 0x4004fc */
0x00400404,
0x00400484,
0x00400408,
@@ -459,27 +441,27 @@ NV_PGRAPH_SOURCE_COLOR,
0x004004f8,
0x0040047c,
0x004004fc,
-NV_PGRAPH_ABS_UCLIP_XMIN,
-NV_PGRAPH_ABS_UCLIP_XMAX,
-NV_PGRAPH_ABS_UCLIP_YMIN,
-NV_PGRAPH_ABS_UCLIP_YMAX,
+NV03_PGRAPH_ABS_UCLIP_XMIN,
+NV03_PGRAPH_ABS_UCLIP_XMAX,
+NV03_PGRAPH_ABS_UCLIP_YMIN,
+NV03_PGRAPH_ABS_UCLIP_YMAX,
0x00400550,
0x00400558,
0x00400554,
0x0040055c,
-NV_PGRAPH_ABS_UCLIPA_XMIN,
-NV_PGRAPH_ABS_UCLIPA_XMAX,
-NV_PGRAPH_ABS_UCLIPA_YMIN,
-NV_PGRAPH_ABS_UCLIPA_YMAX,
-NV_PGRAPH_ABS_ICLIP_XMAX,
-NV_PGRAPH_ABS_ICLIP_YMAX,
-NV_PGRAPH_XY_LOGIC_MISC1,
-NV_PGRAPH_XY_LOGIC_MISC2,
-NV_PGRAPH_XY_LOGIC_MISC3,
-NV_PGRAPH_CLIPX_0,
-NV_PGRAPH_CLIPX_1,
-NV_PGRAPH_CLIPY_0,
-NV_PGRAPH_CLIPY_1,
+NV03_PGRAPH_ABS_UCLIPA_XMIN,
+NV03_PGRAPH_ABS_UCLIPA_XMAX,
+NV03_PGRAPH_ABS_UCLIPA_YMIN,
+NV03_PGRAPH_ABS_UCLIPA_YMAX,
+NV03_PGRAPH_ABS_ICLIP_XMAX,
+NV03_PGRAPH_ABS_ICLIP_YMAX,
+NV03_PGRAPH_XY_LOGIC_MISC1,
+NV03_PGRAPH_XY_LOGIC_MISC2,
+NV03_PGRAPH_XY_LOGIC_MISC3,
+NV03_PGRAPH_CLIPX_0,
+NV03_PGRAPH_CLIPX_1,
+NV03_PGRAPH_CLIPY_0,
+NV03_PGRAPH_CLIPY_1,
0x00400e40,
0x00400e44,
0x00400e48,
@@ -508,34 +490,54 @@ NV_PGRAPH_CLIPY_1,
0x00400e34,
0x00400e38,
0x00400e3c,
-NV_PGRAPH_PASSTHRU_0,
-NV_PGRAPH_PASSTHRU_1,
-NV_PGRAPH_PASSTHRU_2,
-NV_PGRAPH_DIMX_TEXTURE,
-NV_PGRAPH_WDIMX_TEXTURE,
-NV_PGRAPH_DVD_COLORFMT,
-NV_PGRAPH_SCALED_FORMAT,
-NV_PGRAPH_MISC24_0,
-NV_PGRAPH_MISC24_1,
-NV_PGRAPH_MISC24_2,
-NV_PGRAPH_X_MISC,
-NV_PGRAPH_Y_MISC,
-NV_PGRAPH_VALID1,
-NV_PGRAPH_VALID2,
-0
+NV04_PGRAPH_PASSTHRU_0,
+NV04_PGRAPH_PASSTHRU_1,
+NV04_PGRAPH_PASSTHRU_2,
+NV10_PGRAPH_DIMX_TEXTURE,
+NV10_PGRAPH_WDIMX_TEXTURE,
+NV10_PGRAPH_DVD_COLORFMT,
+NV10_PGRAPH_SCALED_FORMAT,
+NV04_PGRAPH_MISC24_0,
+NV04_PGRAPH_MISC24_1,
+NV04_PGRAPH_MISC24_2,
+NV03_PGRAPH_X_MISC,
+NV03_PGRAPH_Y_MISC,
+NV04_PGRAPH_VALID1,
+NV04_PGRAPH_VALID2,
+};
+
+static int nv17_graph_ctx_regs [] = {
+NV10_PGRAPH_DEBUG_4,
+0x004006b0,
+0x00400eac,
+0x00400eb0,
+0x00400eb4,
+0x00400eb8,
+0x00400ebc,
+0x00400ec0,
+0x00400ec4,
+0x00400ec8,
+0x00400ecc,
+0x00400ed0,
+0x00400ed4,
+0x00400ed8,
+0x00400edc,
+0x00400ee0,
+0x00400a00,
+0x00400a04,
};
void nouveau_nv10_context_switch(drm_device_t *dev)
{
drm_nouveau_private_t *dev_priv = dev->dev_private;
- int channel, channel_old, i;
+ int channel, channel_old, i, j;
- channel=NV_READ(NV_PFIFO_CACH1_PSH1)&(nouveau_fifo_number(dev)-1);
- channel_old = (NV_READ(NV_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1);
+ channel=NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1);
+ channel_old = (NV_READ(NV10_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1);
DRM_INFO("NV: PGRAPH context switch interrupt channel %x -> %x\n",channel_old, channel);
- NV_WRITE(NV_PGRAPH_FIFO,0x0);
+ NV_WRITE(NV04_PGRAPH_FIFO,0x0);
#if 0
NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000000);
NV_WRITE(NV_PFIFO_CACH1_PUL1, 0x00000000);
@@ -543,52 +545,65 @@ void nouveau_nv10_context_switch(drm_device_t *dev)
#endif
// save PGRAPH context
- for (i = 0; nv10_graph_ctx_regs[i]; i++)
- dev_priv->fifos[channel_old].nv10_pgraph_ctx[i] = NV_READ(nv10_graph_ctx_regs[i]);
+ for (i = 0; i < sizeof(nv10_graph_ctx_regs)/sizeof(nv10_graph_ctx_regs[0]); i++)
+ dev_priv->fifos[channel_old].pgraph_ctx[i] = NV_READ(nv10_graph_ctx_regs[i]);
+ if (dev_priv->chipset>=0x17) {
+ for (j = 0; j < sizeof(nv17_graph_ctx_regs)/sizeof(nv17_graph_ctx_regs[0]); i++,j++)
+ dev_priv->fifos[channel_old].pgraph_ctx[i] = NV_READ(nv17_graph_ctx_regs[j]);
+ }
nouveau_wait_for_idle(dev);
- NV_WRITE(NV_PGRAPH_CTX_CONTROL, 0x10000000);
- NV_WRITE(NV_PGRAPH_CTX_USER, (NV_READ(NV_PGRAPH_CTX_USER) & 0xffffff) | (0x1f << 24));
+ NV_WRITE(NV03_PGRAPH_CTX_CONTROL, 0x10000000);
+ NV_WRITE(NV10_PGRAPH_CTX_USER, (NV_READ(NV10_PGRAPH_CTX_USER) & 0xffffff) | (0x1f << 24));
nouveau_wait_for_idle(dev);
// restore PGRAPH context
//XXX not working yet
-#if 0
- for (i = 0; nv10_graph_ctx_regs[i]; i++)
- NV_WRITE(nv10_graph_ctx_regs[i], dev_priv->fifos[channel].nv10_pgraph_ctx[i]);
+#if 1
+ for (i = 0; i < sizeof(nv10_graph_ctx_regs)/sizeof(nv10_graph_ctx_regs[0]); i++)
+ NV_WRITE(nv10_graph_ctx_regs[i], dev_priv->fifos[channel].pgraph_ctx[i]);
+ if (dev_priv->chipset>=0x17) {
+ for (j = 0; j < sizeof(nv17_graph_ctx_regs)/sizeof(nv17_graph_ctx_regs[0]); i++,j++)
+ NV_WRITE(nv17_graph_ctx_regs[j], dev_priv->fifos[channel].pgraph_ctx[i]);
+ }
nouveau_wait_for_idle(dev);
#endif
- NV_WRITE(NV_PGRAPH_CTX_CONTROL, 0x10010100);
- NV_WRITE(NV_PGRAPH_CTX_USER, channel << 24);
- NV_WRITE(NV_PGRAPH_FFINTFC_ST2, NV_READ(NV_PGRAPH_FFINTFC_ST2)&0xCFFFFFFF);
+ NV_WRITE(NV03_PGRAPH_CTX_CONTROL, 0x10010100);
+ NV_WRITE(NV10_PGRAPH_CTX_USER, channel << 24);
+ NV_WRITE(NV10_PGRAPH_FFINTFC_ST2, NV_READ(NV10_PGRAPH_FFINTFC_ST2)&0xCFFFFFFF);
#if 0
NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000001);
NV_WRITE(NV_PFIFO_CACH1_PUL1, 0x00000001);
NV_WRITE(NV_PFIFO_CACHES, 0x00000001);
#endif
- NV_WRITE(NV_PGRAPH_FIFO,0x1);
+ NV_WRITE(NV04_PGRAPH_FIFO,0x1);
}
int nv10_graph_context_create(drm_device_t *dev, int channel) {
drm_nouveau_private_t *dev_priv = dev->dev_private;
DRM_DEBUG("nv10_graph_context_create %d\n", channel);
- memset(dev_priv->fifos[channel].nv10_pgraph_ctx, 0, sizeof(dev_priv->fifos[channel].nv10_pgraph_ctx));
+ memset(dev_priv->fifos[channel].pgraph_ctx, 0, sizeof(dev_priv->fifos[channel].pgraph_ctx));
//dev_priv->fifos[channel].pgraph_ctx_user = channel << 24;
- dev_priv->fifos[channel].nv10_pgraph_ctx[0] = 0x0001ffff;
+ dev_priv->fifos[channel].pgraph_ctx[0] = 0x0001ffff;
/* is it really needed ??? */
- dev_priv->fifos[channel].nv10_pgraph_ctx[1] = NV_READ(NV_PGRAPH_DEBUG_4);
- dev_priv->fifos[channel].nv10_pgraph_ctx[2] = NV_READ(0x004006b0);
+ if (dev_priv->chipset>=0x17) {
+ dev_priv->fifos[channel].pgraph_ctx[sizeof(nv10_graph_ctx_regs) + 0] = NV_READ(NV10_PGRAPH_DEBUG_4);
+ dev_priv->fifos[channel].pgraph_ctx[sizeof(nv10_graph_ctx_regs) + 1] = NV_READ(0x004006b0);
+ }
+
+
+ //XXX should be saved/restored for each fifo
+ //we supposed here we have X fifo and only one 3D fifo.
+ nv10_praph_pipe(dev);
return 0;
}
int nv10_graph_init(drm_device_t *dev) {
- //XXX should be call at each fifo init
- nv10_praph_pipe(dev);
return 0;
}
diff --git a/shared-core/nv20_graph.c b/shared-core/nv20_graph.c
index 6e351a2d..9ba6a873 100644
--- a/shared-core/nv20_graph.c
+++ b/shared-core/nv20_graph.c
@@ -56,9 +56,9 @@ static void nv20_graph_rdi(drm_device_t *dev) {
(drm_nouveau_private_t *)dev->dev_private;
int i;
- NV_WRITE(NV_PGRAPH_RDI_INDEX, 0x2c80000);
+ NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x2c80000);
for (i = 0; i < 32; i++)
- NV_WRITE(NV_PGRAPH_RDI_DATA, 0);
+ NV_WRITE(NV10_PGRAPH_RDI_DATA, 0);
nouveau_wait_for_idle(dev);
}
@@ -77,8 +77,8 @@ static void nv20_graph_context_save_current(drm_device_t *dev, int channel) {
if (instance != nouveau_chip_instance_get(dev, dev_priv->fifos[channel].ramin_grctx))
DRM_ERROR("nv20_graph_context_save_current : bad instance\n");
- NV_WRITE(NV_PGRAPH_CHANNEL_CTX_SIZE, instance);
- NV_WRITE(NV_PGRAPH_CHANNEL_CTX_POINTER, 2 /* save ctx */);
+ NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_SIZE, instance);
+ NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_POINTER, 2 /* save ctx */);
}
@@ -96,9 +96,9 @@ static void nv20_graph_context_restore(drm_device_t *dev, int channel) {
if (instance != nouveau_chip_instance_get(dev, dev_priv->fifos[channel].ramin_grctx))
DRM_ERROR("nv20_graph_context_restore_current : bad instance\n");
- NV_WRITE(NV_PGRAPH_CTX_USER, channel << 24);
- NV_WRITE(NV_PGRAPH_CHANNEL_CTX_SIZE, instance);
- NV_WRITE(NV_PGRAPH_CHANNEL_CTX_POINTER, 1 /* restore ctx */);
+ NV_WRITE(NV10_PGRAPH_CTX_USER, channel << 24);
+ NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_SIZE, instance);
+ NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_POINTER, 1 /* restore ctx */);
}
void nouveau_nv20_context_switch(drm_device_t *dev)
@@ -106,30 +106,30 @@ void nouveau_nv20_context_switch(drm_device_t *dev)
drm_nouveau_private_t *dev_priv = dev->dev_private;
int channel, channel_old;
- channel=NV_READ(NV_PFIFO_CACH1_PSH1)&(nouveau_fifo_number(dev)-1);
- channel_old = (NV_READ(NV_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1);
+ channel=NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1);
+ channel_old = (NV_READ(NV10_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1);
DRM_DEBUG("NV: PGRAPH context switch interrupt channel %x -> %x\n",channel_old, channel);
- NV_WRITE(NV_PGRAPH_FIFO,0x0);
+ NV_WRITE(NV04_PGRAPH_FIFO,0x0);
nv20_graph_context_save_current(dev, channel_old);
nouveau_wait_for_idle(dev);
- NV_WRITE(NV_PGRAPH_CTX_CONTROL, 0x10000000);
+ NV_WRITE(NV03_PGRAPH_CTX_CONTROL, 0x10000000);
nv20_graph_context_restore(dev, channel);
nouveau_wait_for_idle(dev);
- if ((NV_READ(NV_PGRAPH_CTX_USER) >> 24) != channel)
- DRM_ERROR("nouveau_nv20_context_switch : wrong channel restored %x %x!!!\n", channel, NV_READ(NV_PGRAPH_CTX_USER) >> 24);
+ if ((NV_READ(NV10_PGRAPH_CTX_USER) >> 24) != channel)
+ DRM_ERROR("nouveau_nv20_context_switch : wrong channel restored %x %x!!!\n", channel, NV_READ(NV10_PGRAPH_CTX_USER) >> 24);
- NV_WRITE(NV_PGRAPH_CTX_CONTROL, 0x10010100);
- NV_WRITE(NV_PGRAPH_FFINTFC_ST2, NV_READ(NV_PGRAPH_FFINTFC_ST2)&0xCFFFFFFF);
+ NV_WRITE(NV03_PGRAPH_CTX_CONTROL, 0x10010100);
+ NV_WRITE(NV10_PGRAPH_FFINTFC_ST2, NV_READ(NV10_PGRAPH_FFINTFC_ST2)&0xCFFFFFFF);
- NV_WRITE(NV_PGRAPH_FIFO,0x1);
+ NV_WRITE(NV04_PGRAPH_FIFO,0x1);
}
int nv20_graph_init(drm_device_t *dev) {
@@ -146,7 +146,7 @@ int nv20_graph_init(drm_device_t *dev) {
for (i=0; i< dev_priv->ctx_table_size; i+=4)
INSTANCE_WR(dev_priv->ctx_table, i/4, 0x00000000);
- NV_WRITE(NV_PGRAPH_CHANNEL_CTX_TABLE, nouveau_chip_instance_get(dev, dev_priv->ctx_table));
+ NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_TABLE, nouveau_chip_instance_get(dev, dev_priv->ctx_table));
//XXX need to be done and save/restore for each fifo ???
nv20_graph_rdi(dev);
diff --git a/shared-core/nv30_graph.c b/shared-core/nv30_graph.c
index a5f01ea5..cb183bea 100644
--- a/shared-core/nv30_graph.c
+++ b/shared-core/nv30_graph.c
@@ -107,10 +107,9 @@ int nv30_graph_context_create(drm_device_t *dev, int channel)
struct nouveau_fifo *chan = &dev_priv->fifos[channel];
void (*ctx_init)(drm_device_t *, struct mem_block *);
unsigned int ctx_size;
- int i, chipset;
+ int i;
- chipset = (NV_READ(NV_PMC_BOOT_0) & 0x0ff00000) >> 20;
- switch (chipset) {
+ switch (dev_priv->chipset) {
default:
ctx_size = NV30_GRCTX_SIZE;
ctx_init = nv30_graph_context_init;
@@ -137,10 +136,7 @@ int nv30_graph_init(drm_device_t *dev)
{
drm_nouveau_private_t *dev_priv =
(drm_nouveau_private_t *)dev->dev_private;
- int i, chipset;
-
- chipset = (NV_READ(NV_PMC_BOOT_0) & 0x0ff00000) >> 20;
- DRM_DEBUG("chipset (from PMC_BOOT_0): NV%02X\n", chipset);
+ int i;
/* Create Context Pointer Table */
dev_priv->ctx_table_size = 32 * 4;
@@ -151,7 +147,7 @@ int nv30_graph_init(drm_device_t *dev)
for (i=0; i< dev_priv->ctx_table_size; i+=4)
INSTANCE_WR(dev_priv->ctx_table, i/4, 0x00000000);
- NV_WRITE(NV_PGRAPH_CHANNEL_CTX_TABLE, nouveau_chip_instance_get(dev, dev_priv->ctx_table));
+ NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_TABLE, nouveau_chip_instance_get(dev, dev_priv->ctx_table));
return 0;
}
diff --git a/shared-core/nv40_graph.c b/shared-core/nv40_graph.c
index 00583cdc..659767f2 100644
--- a/shared-core/nv40_graph.c
+++ b/shared-core/nv40_graph.c
@@ -611,10 +611,9 @@ nv40_graph_context_create(drm_device_t *dev, int channel)
struct nouveau_fifo *chan = &dev_priv->fifos[channel];
void (*ctx_init)(drm_device_t *, struct mem_block *);
unsigned int ctx_size;
- int i, chipset;
+ int i;
- chipset = (NV_READ(NV_PMC_BOOT_0) & 0x0ff00000) >> 20;
- switch (chipset) {
+ switch (dev_priv->chipset) {
case 0x40:
ctx_size = NV40_GRCTX_SIZE;
ctx_init = nv40_graph_context_init;
@@ -665,11 +664,11 @@ nv40_graph_context_save_current(drm_device_t *dev)
uint32_t instance;
int i;
- NV_WRITE(NV_PGRAPH_FIFO, 0);
+ NV_WRITE(NV04_PGRAPH_FIFO, 0);
instance = NV_READ(0x40032C) & 0xFFFFF;
if (!instance) {
- NV_WRITE(NV_PGRAPH_FIFO, 1);
+ NV_WRITE(NV04_PGRAPH_FIFO, 1);
return;
}
@@ -685,11 +684,11 @@ nv40_graph_context_save_current(drm_device_t *dev)
DRM_ERROR("failed to save current grctx to ramin\n");
DRM_ERROR("instance = 0x%08x\n", NV_READ(0x40032C));
DRM_ERROR("0x40030C = 0x%08x\n", NV_READ(0x40030C));
- NV_WRITE(NV_PGRAPH_FIFO, 1);
+ NV_WRITE(NV04_PGRAPH_FIFO, 1);
return;
}
- NV_WRITE(NV_PGRAPH_FIFO, 1);
+ NV_WRITE(NV04_PGRAPH_FIFO, 1);
}
/* Restore the context for a specific channel into PGRAPH
@@ -706,7 +705,7 @@ nv40_graph_context_restore(drm_device_t *dev, int channel)
instance = nouveau_chip_instance_get(dev, chan->ramin_grctx);
- NV_WRITE(NV_PGRAPH_FIFO, 0);
+ NV_WRITE(NV04_PGRAPH_FIFO, 0);
NV_WRITE(0x400784, instance);
NV_WRITE(0x400310, NV_READ(0x400310) | 0x40);
NV_WRITE(0x400304, 1);
@@ -720,7 +719,7 @@ nv40_graph_context_restore(drm_device_t *dev, int channel)
channel);
DRM_ERROR("instance = 0x%08x\n", instance);
DRM_ERROR("0x40030C = 0x%08x\n", NV_READ(0x40030C));
- NV_WRITE(NV_PGRAPH_FIFO, 1);
+ NV_WRITE(NV04_PGRAPH_FIFO, 1);
return;
}
@@ -736,7 +735,7 @@ nv40_graph_context_restore(drm_device_t *dev, int channel)
* recieve PGRAPH_INTR_CONTEXT_SWITCH
*/
NV_WRITE(NV40_PFIFO_GRCTX_INSTANCE, instance);
- NV_WRITE(NV_PGRAPH_FIFO, 1);
+ NV_WRITE(NV04_PGRAPH_FIFO, 1);
}
/* Some voodoo that makes context switching work without the binary driver
@@ -896,17 +895,16 @@ nv40_graph_init(drm_device_t *dev)
(drm_nouveau_private_t *)dev->dev_private;
uint32_t *ctx_voodoo;
uint32_t pg0220_inst;
- int i, chipset;
+ int i;
- chipset = (NV_READ(NV_PMC_BOOT_0) & 0x0ff00000) >> 20;
- DRM_DEBUG("chipset (from PMC_BOOT_0): NV%02X\n", chipset);
- switch (chipset) {
+ switch (dev_priv->chipset) {
case 0x40: ctx_voodoo = nv40_ctx_voodoo; break;
case 0x43: ctx_voodoo = nv43_ctx_voodoo; break;
case 0x4a: ctx_voodoo = nv4a_ctx_voodoo; break;
case 0x4e: ctx_voodoo = nv4e_ctx_voodoo; break;
default:
- DRM_ERROR("Unknown ctx_voodoo for chipset 0x%02x\n", chipset);
+ DRM_ERROR("Unknown ctx_voodoo for chipset 0x%02x\n",
+ dev_priv->chipset);
ctx_voodoo = NULL;
break;
}
@@ -932,7 +930,7 @@ nv40_graph_init(drm_device_t *dev)
NV_DMA_ACCESS_RW, NV_DMA_TARGET_VIDMEM);
pg0220_inst = nouveau_chip_instance_get(dev,
dev_priv->fb_obj->instance);
- NV_WRITE(NV_PGRAPH_NV40_UNK220, pg0220_inst);
+ NV_WRITE(NV40_PGRAPH_UNK220, pg0220_inst);
return 0;
}
diff --git a/shared-core/via_dma.c b/shared-core/via_dma.c
index 90dbb6a2..09159634 100644
--- a/shared-core/via_dma.c
+++ b/shared-core/via_dma.c
@@ -192,6 +192,11 @@ static int via_initialize(drm_device_t * dev,
return DRM_ERR(EFAULT);
}
+ if (dev_priv->chipset == VIA_DX9_0) {
+ DRM_ERROR("AGP DMA is not supported on this chip\n");
+ return DRM_ERR(EINVAL);
+ }
+
dev_priv->ring.map.offset = dev->agp->base + init->offset;
dev_priv->ring.map.size = init->size;
dev_priv->ring.map.type = 0;
@@ -294,7 +299,7 @@ static int via_dispatch_cmdbuffer(drm_device_t * dev, drm_via_cmdbuffer_t * cmd)
cmd->size, dev, 1))) {
return ret;
}
-
+
vb = via_check_dma(dev_priv, (cmd->size < 0x100) ? 0x102 : cmd->size);
if (vb == NULL) {
return DRM_ERR(EAGAIN);
@@ -428,70 +433,46 @@ static inline uint32_t *via_get_dma(drm_via_private_t * dev_priv)
* modifying the pause address stored in the buffer itself. If
* the regulator has already paused, restart it.
*/
+
static int via_hook_segment(drm_via_private_t *dev_priv,
uint32_t pause_addr_hi, uint32_t pause_addr_lo,
int no_pci_fire)
{
int paused, count;
volatile uint32_t *paused_at = dev_priv->last_pause_ptr;
+ uint32_t reader,ptr;
+ paused = 0;
via_flush_write_combine();
- while(! *(via_get_dma(dev_priv)-1));
*dev_priv->last_pause_ptr = pause_addr_lo;
via_flush_write_combine();
-
- /*
- * The below statement is inserted to really force the flush.
- * Not sure it is needed.
- */
-
- while(! *dev_priv->last_pause_ptr);
+ reader = *(dev_priv->hw_addr_ptr);
+ ptr = ((volatile char *)paused_at - dev_priv->dma_ptr) +
+ dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr + 4;
dev_priv->last_pause_ptr = via_get_dma(dev_priv) - 1;
- while(! *dev_priv->last_pause_ptr);
-
- paused = 0;
- count = 20;
-
- while (!(paused = (VIA_READ(0x41c) & 0x80000000)) && count--);
- if ((count <= 8) && (count >= 0)) {
- uint32_t rgtr, ptr;
- rgtr = *(dev_priv->hw_addr_ptr);
- ptr = ((volatile char *)dev_priv->last_pause_ptr -
- dev_priv->dma_ptr) + dev_priv->dma_offset +
- (uint32_t) dev_priv->agpAddr + 4 - CMDBUF_ALIGNMENT_SIZE;
- if (rgtr <= ptr) {
- DRM_ERROR
- ("Command regulator\npaused at count %d, address %x, "
- "while current pause address is %x.\n"
- "Please mail this message to "
- "<unichrome-devel@lists.sourceforge.net>\n", count,
- rgtr, ptr);
- }
+ if ((ptr - reader) <= dev_priv->dma_diff ) {
+ count = 10000000;
+ while (!(paused = (VIA_READ(0x41c) & 0x80000000)) && count--);
}
-
+
if (paused && !no_pci_fire) {
- uint32_t rgtr,ptr;
- uint32_t ptr_low;
-
- count = 1000000;
- while ((VIA_READ(VIA_REG_STATUS) & VIA_CMD_RGTR_BUSY)
- && count--);
-
- rgtr = *(dev_priv->hw_addr_ptr);
- ptr = ((volatile char *)paused_at - dev_priv->dma_ptr) +
- dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr + 4;
-
-
- ptr_low = (ptr > 3*CMDBUF_ALIGNMENT_SIZE) ?
- ptr - 3*CMDBUF_ALIGNMENT_SIZE : 0;
- if (rgtr <= ptr && rgtr >= ptr_low) {
+ reader = *(dev_priv->hw_addr_ptr);
+ if ((ptr - reader) == dev_priv->dma_diff) {
+
+ /*
+ * There is a concern that these writes may stall the PCI bus
+ * if the GPU is not idle. However, idling the GPU first
+ * doesn't make a difference.
+ */
+
VIA_WRITE(VIA_REG_TRANSET, (HC_ParaType_PreCR << 16));
VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_hi);
VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_lo);
VIA_READ(VIA_REG_TRANSPACE);
- }
+ }
}
+
return paused;
}
@@ -500,6 +481,9 @@ static int via_hook_segment(drm_via_private_t *dev_priv,
static int via_wait_idle(drm_via_private_t * dev_priv)
{
int count = 10000000;
+
+ while (!(VIA_READ(VIA_REG_STATUS) & VIA_VR_QUEUE_BUSY) && count--);
+
while (count-- && (VIA_READ(VIA_REG_STATUS) &
(VIA_CMD_RGTR_BUSY | VIA_2D_ENG_BUSY |
VIA_3D_ENG_BUSY))) ;
@@ -546,7 +530,9 @@ static void via_cmdbuf_start(drm_via_private_t * dev_priv)
uint32_t end_addr, end_addr_lo;
uint32_t command;
uint32_t agp_base;
-
+ uint32_t ptr;
+ uint32_t reader;
+ int count;
dev_priv->dma_low = 0;
@@ -576,6 +562,24 @@ static void via_cmdbuf_start(drm_via_private_t * dev_priv)
DRM_WRITEMEMORYBARRIER();
VIA_WRITE(VIA_REG_TRANSPACE, command | HC_HAGPCMNT_MASK);
VIA_READ(VIA_REG_TRANSPACE);
+
+ dev_priv->dma_diff = 0;
+
+ count = 10000000;
+ while (!(VIA_READ(0x41c) & 0x80000000) && count--);
+
+ reader = *(dev_priv->hw_addr_ptr);
+ ptr = ((volatile char *)dev_priv->last_pause_ptr - dev_priv->dma_ptr) +
+ dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr + 4;
+
+ /*
+ * This is the difference between where we tell the
+ * command reader to pause and where it actually pauses.
+ * This differs between hw implementation so we need to
+ * detect it.
+ */
+
+ dev_priv->dma_diff = ptr - reader;
}
static void via_pad_cache(drm_via_private_t *dev_priv, int qwords)
@@ -593,20 +597,18 @@ static inline void via_dummy_bitblt(drm_via_private_t * dev_priv)
uint32_t *vb = via_get_dma(dev_priv);
SetReg2DAGP(0x0C, (0 | (0 << 16)));
SetReg2DAGP(0x10, 0 | (0 << 16));
- SetReg2DAGP(0x0, 0x1 | 0x2000 | 0xAA000000);
+ SetReg2DAGP(0x0, 0x1 | 0x2000 | 0xAA000000);
}
-
static void via_cmdbuf_jump(drm_via_private_t * dev_priv)
{
uint32_t agp_base;
uint32_t pause_addr_lo, pause_addr_hi;
uint32_t jump_addr_lo, jump_addr_hi;
volatile uint32_t *last_pause_ptr;
- uint32_t dma_low_save1, dma_low_save2;
agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
- via_align_cmd(dev_priv, HC_HAGPBpID_JUMP, 0, &jump_addr_hi,
+ via_align_cmd(dev_priv, HC_HAGPBpID_JUMP, 0, &jump_addr_hi,
&jump_addr_lo, 0);
dev_priv->dma_wrap = dev_priv->dma_low;
@@ -622,38 +624,14 @@ static void via_cmdbuf_jump(drm_via_private_t * dev_priv)
}
via_dummy_bitblt(dev_priv);
- via_dummy_bitblt(dev_priv);
-
- last_pause_ptr =
- via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,
- &pause_addr_lo, 0) -1;
- via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,
- &pause_addr_lo, 0);
-
- *last_pause_ptr = pause_addr_lo;
- dma_low_save1 = dev_priv->dma_low;
-
- /*
- * Now, set a trap that will pause the regulator if it tries to rerun the old
- * command buffer. (Which may happen if via_hook_segment detecs a command regulator pause
- * and reissues the jump command over PCI, while the regulator has already taken the jump
- * and actually paused at the current buffer end).
- * There appears to be no other way to detect this condition, since the hw_addr_pointer
- * does not seem to get updated immediately when a jump occurs.
- */
-
- last_pause_ptr =
- via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,
+ via_dummy_bitblt(dev_priv);
+ last_pause_ptr = via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,
&pause_addr_lo, 0) -1;
- via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,
+ via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,
&pause_addr_lo, 0);
*last_pause_ptr = pause_addr_lo;
- dma_low_save2 = dev_priv->dma_low;
- dev_priv->dma_low = dma_low_save1;
via_hook_segment( dev_priv, jump_addr_hi, jump_addr_lo, 0);
- dev_priv->dma_low = dma_low_save2;
- via_hook_segment( dev_priv, pause_addr_hi, pause_addr_lo, 0);
}
diff --git a/shared-core/via_drm.h b/shared-core/via_drm.h
index 16421d74..88345bdf 100644
--- a/shared-core/via_drm.h
+++ b/shared-core/via_drm.h
@@ -42,11 +42,11 @@
* backwards incompatibilities, (which should be avoided whenever possible).
*/
-#define VIA_DRM_DRIVER_DATE "20061227"
+#define VIA_DRM_DRIVER_DATE "20070202"
#define VIA_DRM_DRIVER_MAJOR 2
#define VIA_DRM_DRIVER_MINOR 11
-#define VIA_DRM_DRIVER_PATCHLEVEL 0
+#define VIA_DRM_DRIVER_PATCHLEVEL 1
#define VIA_DRM_DRIVER_VERSION (((VIA_DRM_DRIVER_MAJOR) << 16) | (VIA_DRM_DRIVER_MINOR))
#define VIA_NR_SAREA_CLIPRECTS 8
diff --git a/shared-core/via_drv.h b/shared-core/via_drv.h
index 7a8f2c34..42d0c749 100644
--- a/shared-core/via_drv.h
+++ b/shared-core/via_drv.h
@@ -102,6 +102,7 @@ typedef struct drm_via_private {
#ifdef VIA_HAVE_DMABLIT
drm_via_blitq_t blit_queues[VIA_NUM_BLIT_ENGINES];
#endif
+ uint32_t dma_diff;
} drm_via_private_t;
enum via_family {
diff --git a/tests/ttmtest/AUTHORS b/tests/ttmtest/AUTHORS
new file mode 100644
index 00000000..fa4a089d
--- /dev/null
+++ b/tests/ttmtest/AUTHORS
@@ -0,0 +1 @@
+Thomas Hellström <thomas-at-tungstengraphics.com> and others.
diff --git a/tests/ttmtest/ChangeLog b/tests/ttmtest/ChangeLog
new file mode 100644
index 00000000..4588c8db
--- /dev/null
+++ b/tests/ttmtest/ChangeLog
@@ -0,0 +1,23 @@
+2006-01-24 Thomas Hellström <thomas-at-tungstengraphics.com>
+
+ * configure.ac:
+ * src/ttmtest.c:
+
+ Fixed include path.
+
+2006-01-24 Thomas Hellström <thomas-at-tungstengraphics.com>
+
+ * AUTHORS:
+ * Makefile.am:
+ * configure.ac:
+ * reconf:
+ * src/Makefile.am:
+ * src/ttmtest.c: (fastrdtsc), (time_diff), (releaseContext),
+ (testAGP), (main):
+ * src/xf86dri.c: (uniDRIDestroyContext), (uniDRICreateDrawable),
+ (uniDRIDestroyDrawable), (uniDRIGetDrawableInfo):
+ * src/xf86dri.h:
+ * src/xf86dristr.h:
+
+ Initial import of the ttmtest utility.
+ \ No newline at end of file
diff --git a/tests/ttmtest/Makefile.am b/tests/ttmtest/Makefile.am
new file mode 100644
index 00000000..af437a64
--- /dev/null
+++ b/tests/ttmtest/Makefile.am
@@ -0,0 +1 @@
+SUBDIRS = src
diff --git a/tests/ttmtest/NEWS b/tests/ttmtest/NEWS
new file mode 100644
index 00000000..e69de29b
--- /dev/null
+++ b/tests/ttmtest/NEWS
diff --git a/tests/ttmtest/README b/tests/ttmtest/README
new file mode 100644
index 00000000..e69de29b
--- /dev/null
+++ b/tests/ttmtest/README
diff --git a/tests/ttmtest/configure.ac b/tests/ttmtest/configure.ac
new file mode 100644
index 00000000..c41e91ac
--- /dev/null
+++ b/tests/ttmtest/configure.ac
@@ -0,0 +1,33 @@
+AC_INIT
+AC_PROG_CC
+AC_PATH_X
+if test "x$no_x" != "xyes"; then
+ savecpp="$CPPFLAGS"
+ CPPFLAGS="$CPPFLAGS -I$x_includes"
+ AC_CHECK_HEADER($x_includes/X11/Xlib.h,,\
+ [AC_MSG_ERROR(Could not find X installation.)])
+ CPPFLAGS="$savecpp"
+ MDRIINC="-I$x_includes"
+ LIBS="-L$x_libraries $LIBS"
+else
+ AC_MSG_ERROR(Could not find X installation. Aborting.)
+fi
+AC_ARG_WITH(libdrm,
+ AC_HELP_STRING([--with-libdrm=DIR],
+ [Installation prefix of libdrm [[default=/usr]]]),
+ [libdrmpref="$withval"],
+ [libdrmpref="/usr"])
+savecpp="$CPPFLAGS"
+MDRIINC="-I$libdrmpref/include -I$libdrmpref/include/drm -I$x_includes"
+CPPFLAGS="$CPPFLAGS $MDRIINC"
+AC_CHECK_HEADER(xf86drm.h,,\
+ [AC_MSG_ERROR(Could not find libdrm installation. Use --with-libdrm=<libdrm_installation_prefix>)])
+AC_CHECK_HEADER(drm.h,,\
+ [AC_MSG_ERROR(Could not find libdrm installation. Use --with-libdrm=<libdrm_installation_prefix>)])
+CPPFLAGS="$savecpp"
+LIBS="-L$libdrmpref/lib64 -L$libdrmpref/lib $LIBS"
+AC_SUBST(MDRIINC)
+AC_SYS_LARGEFILE
+AM_INIT_AUTOMAKE(minidri,0.1.0)
+AM_CONFIG_HEADER(config.h)
+AC_OUTPUT([Makefile src/Makefile])
diff --git a/tests/ttmtest/reconf b/tests/ttmtest/reconf
new file mode 100755
index 00000000..e64d00ac
--- /dev/null
+++ b/tests/ttmtest/reconf
@@ -0,0 +1,2 @@
+#!/bin/sh
+autoreconf -v --install || exit 1 \ No newline at end of file
diff --git a/tests/ttmtest/src/Makefile.am b/tests/ttmtest/src/Makefile.am
new file mode 100644
index 00000000..b7ee8291
--- /dev/null
+++ b/tests/ttmtest/src/Makefile.am
@@ -0,0 +1,8 @@
+INCLUDES = @MDRIINC@
+bin_PROGRAMS = ttmtest
+ttmtest_SOURCES = \
+ ttmtest.c \
+ xf86dri.c \
+ xf86dri.h \
+ xf86dristr.h
+ttmtest_LDADD = -ldrm -lXext -lX11
diff --git a/tests/ttmtest/src/ttmtest.c b/tests/ttmtest/src/ttmtest.c
new file mode 100644
index 00000000..ae261e28
--- /dev/null
+++ b/tests/ttmtest/src/ttmtest.c
@@ -0,0 +1,429 @@
+/**************************************************************************
+ *
+ * Copyright 2007 Tungsten Graphics, Inc., Cedar Park, TX., USA
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ *
+ **************************************************************************/
+/*
+ * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include <X11/Xlib.h>
+#include <X11/Xutil.h>
+#include <drm/drm.h>
+#include "xf86dri.h"
+#include "xf86drm.h"
+#include "stdio.h"
+#include "sys/types.h"
+#include <unistd.h>
+#include <string.h>
+#include <errno.h>
+#include <stdlib.h>
+#include "sys/mman.h"
+
+typedef struct
+{
+ enum
+ {
+ haveNothing,
+ haveDisplay,
+ haveConnection,
+ haveDriverName,
+ haveDeviceInfo,
+ haveDRM,
+ haveContext
+ }
+ state;
+
+ Display *display;
+ int screen;
+ drm_handle_t sAreaOffset;
+ char *curBusID;
+ char *driverName;
+ int drmFD;
+ XVisualInfo visualInfo;
+ XID id;
+ drm_context_t hwContext;
+ void *driPriv;
+ int driPrivSize;
+ int fbSize;
+ int fbOrigin;
+ int fbStride;
+ drm_handle_t fbHandle;
+ int ddxDriverMajor;
+ int ddxDriverMinor;
+ int ddxDriverPatch;
+} TinyDRIContext;
+
+#ifndef __x86_64__
+static unsigned
+fastrdtsc(void)
+{
+ unsigned eax;
+ __asm__ volatile ("\t"
+ "pushl %%ebx\n\t"
+ "cpuid\n\t" ".byte 0x0f, 0x31\n\t" "popl %%ebx\n":"=a" (eax)
+ :"0"(0)
+ :"ecx", "edx", "cc");
+
+ return eax;
+}
+#else
+static unsigned
+fastrdtsc(void)
+{
+ unsigned eax;
+ __asm__ volatile ("\t" "cpuid\n\t" ".byte 0x0f, 0x31\n\t":"=a" (eax)
+ :"0"(0)
+ :"ecx", "edx", "ebx", "cc");
+
+ return eax;
+}
+#endif
+
+void
+bmError(int val, const char *file, const char *function, int line)
+{
+ fprintf(stderr, "Fatal video memory manager error \"%s\".\n"
+ "Check kernel logs or set the LIBGL_DEBUG\n"
+ "environment variable to \"verbose\" for more info.\n"
+ "Detected in file %s, line %d, function %s.\n",
+ strerror(-val), file, line, function);
+ abort();
+}
+
+#define BM_CKFATAL(val) \
+ do{ \
+ int tstVal = (val); \
+ if (tstVal) \
+ bmError(tstVal, __FILE__, __FUNCTION__, __LINE__); \
+ } while(0);
+
+static unsigned
+time_diff(unsigned t, unsigned t2)
+{
+ return ((t < t2) ? t2 - t : 0xFFFFFFFFU - (t - t2 - 1));
+}
+
+static int
+releaseContext(TinyDRIContext * ctx)
+{
+ switch (ctx->state) {
+ case haveContext:
+ uniDRIDestroyContext(ctx->display, ctx->screen, ctx->id);
+ case haveDRM:
+ drmClose(ctx->drmFD);
+ case haveDeviceInfo:
+ XFree(ctx->driPriv);
+ case haveDriverName:
+ XFree(ctx->driverName);
+ case haveConnection:
+ XFree(ctx->curBusID);
+ uniDRICloseConnection(ctx->display, ctx->screen);
+ case haveDisplay:
+ XCloseDisplay(ctx->display);
+ default:
+ break;
+ }
+ return -1;
+}
+
+static void
+readBuf(void *buf, unsigned long size)
+{
+ volatile unsigned *buf32 = (unsigned *)buf;
+ unsigned *end = (unsigned *)buf32 + size / sizeof(*buf32);
+
+ while (buf32 < end) {
+ (void)*buf32++;
+ }
+}
+
+static int
+benchmarkBuffer(TinyDRIContext * ctx, unsigned long size,
+ unsigned long *ticks)
+{
+ unsigned long curTime, oldTime;
+ int ret;
+ drmBO buf;
+ void *virtual;
+
+ /*
+ * Test system memory objects.
+ */
+
+ oldTime = fastrdtsc();
+ BM_CKFATAL(drmBOCreate(ctx->drmFD, 0, size, 0, NULL,
+ drm_bo_type_dc,
+ DRM_BO_FLAG_READ |
+ DRM_BO_FLAG_WRITE |
+ DRM_BO_FLAG_MEM_LOCAL | DRM_BO_FLAG_NO_MOVE, 0, &buf));
+ curTime = fastrdtsc();
+ *ticks++ = time_diff(oldTime, curTime);
+
+ oldTime = fastrdtsc();
+ BM_CKFATAL(drmBOMap(ctx->drmFD, &buf,
+ DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE, 0, &virtual));
+ curTime = fastrdtsc();
+ *ticks++ = time_diff(oldTime, curTime);
+
+ oldTime = fastrdtsc();
+ memset(virtual, 0xF0, buf.size);
+ curTime = fastrdtsc();
+ *ticks++ = time_diff(oldTime, curTime);
+
+ oldTime = fastrdtsc();
+ memset(virtual, 0x0F, buf.size);
+ curTime = fastrdtsc();
+ *ticks++ = time_diff(oldTime, curTime);
+
+ oldTime = fastrdtsc();
+ readBuf(virtual, buf.size);
+ curTime = fastrdtsc();
+ *ticks++ = time_diff(oldTime, curTime);
+
+ oldTime = fastrdtsc();
+ BM_CKFATAL(drmBOUnmap(ctx->drmFD, &buf));
+ curTime = fastrdtsc();
+ *ticks++ = time_diff(oldTime, curTime);
+
+ /*
+ * Test TT bound buffer objects.
+ */
+
+ BM_CKFATAL(drmGetLock(ctx->drmFD, ctx->hwContext, 0));
+ oldTime = fastrdtsc();
+ BM_CKFATAL(drmBOValidate(ctx->drmFD, &buf,
+ DRM_BO_FLAG_MEM_TT, DRM_BO_MASK_MEM, DRM_BO_HINT_DONT_FENCE));
+ curTime = fastrdtsc();
+ BM_CKFATAL(drmUnlock(ctx->drmFD, ctx->hwContext));
+ *ticks++ = time_diff(oldTime, curTime);
+
+ oldTime = fastrdtsc();
+ BM_CKFATAL(drmBOMap(ctx->drmFD, &buf,
+ DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE, 0, &virtual));
+ curTime = fastrdtsc();
+ *ticks++ = time_diff(oldTime, curTime);
+
+ oldTime = fastrdtsc();
+ memset(virtual, 0xF0, buf.size);
+ curTime = fastrdtsc();
+ *ticks++ = time_diff(oldTime, curTime);
+
+ oldTime = fastrdtsc();
+ memset(virtual, 0x0F, buf.size);
+ curTime = fastrdtsc();
+ *ticks++ = time_diff(oldTime, curTime);
+
+ oldTime = fastrdtsc();
+ readBuf(virtual, buf.size);
+ curTime = fastrdtsc();
+ *ticks++ = time_diff(oldTime, curTime);
+
+ BM_CKFATAL(drmBOUnmap(ctx->drmFD, &buf));
+
+ BM_CKFATAL(drmGetLock(ctx->drmFD, ctx->hwContext, 0));
+ oldTime = fastrdtsc();
+ BM_CKFATAL(drmBOValidate(ctx->drmFD, &buf,
+ DRM_BO_FLAG_MEM_LOCAL, DRM_BO_MASK_MEM, DRM_BO_HINT_DONT_FENCE));
+ curTime = fastrdtsc();
+ *ticks++ = time_diff(oldTime, curTime);
+
+ /*
+ * Test cached buffers objects.
+ */
+
+ oldTime = fastrdtsc();
+ ret = drmBOValidate(ctx->drmFD, &buf,
+ DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_BIND_CACHED,
+ DRM_BO_MASK_MEM | DRM_BO_FLAG_BIND_CACHED, DRM_BO_HINT_DONT_FENCE);
+ curTime = fastrdtsc();
+ drmUnlock(ctx->drmFD, ctx->hwContext);
+
+ if (ret) {
+ printf("Couldn't bind cached. Probably no support\n");
+ BM_CKFATAL(drmBODestroy(ctx->drmFD, &buf));
+ return 1;
+ }
+ *ticks++ = time_diff(oldTime, curTime);
+
+ oldTime = fastrdtsc();
+ BM_CKFATAL(drmBOMap(ctx->drmFD, &buf,
+ DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE, 0, &virtual));
+
+ curTime = fastrdtsc();
+ *ticks++ = time_diff(oldTime, curTime);
+
+ oldTime = fastrdtsc();
+ memset(virtual, 0xF0, buf.size);
+ curTime = fastrdtsc();
+ *ticks++ = time_diff(oldTime, curTime);
+
+ oldTime = fastrdtsc();
+ memset(virtual, 0x0F, buf.size);
+ curTime = fastrdtsc();
+ *ticks++ = time_diff(oldTime, curTime);
+
+ oldTime = fastrdtsc();
+ readBuf(virtual, buf.size);
+ curTime = fastrdtsc();
+ *ticks++ = time_diff(oldTime, curTime);
+
+ BM_CKFATAL(drmBOUnmap(ctx->drmFD, &buf));
+ BM_CKFATAL(drmBODestroy(ctx->drmFD, &buf));
+
+ return 0;
+}
+
+static void
+testAGP(TinyDRIContext * ctx)
+{
+ unsigned long ticks[128], *pTicks;
+ unsigned long size = 4096 * 1024;
+ int ret;
+
+ ret = benchmarkBuffer(ctx, size, ticks);
+ if (ret < 0) {
+ fprintf(stderr, "Buffer error %s\n", strerror(-ret));
+ return;
+ }
+ pTicks = ticks;
+
+ printf("Buffer size %d bytes\n", size);
+ printf("System memory timings ********************************\n");
+ printf("Creation took %12lu ticks\n", *pTicks++);
+ printf("Mapping took %12lu ticks\n", *pTicks++);
+ printf("Writing took %12lu ticks\n", *pTicks++);
+ printf("Writing Again took %12lu ticks\n", *pTicks++);
+ printf("Reading took %12lu ticks\n", *pTicks++);
+ printf("Unmapping took %12lu ticks\n", *pTicks++);
+
+ printf("\nTT Memory timings ************************************\n");
+ printf("Moving to TT took %12lu ticks\n", *pTicks++);
+ printf("Mapping in TT took %12lu ticks\n", *pTicks++);
+ printf("Writing to TT took %12lu ticks\n", *pTicks++);
+ printf("Writing again to TT took %12lu ticks\n", *pTicks++);
+ printf("Reading from TT took %12lu ticks\n", *pTicks++);
+ printf("Moving to system took %12lu ticks\n", *pTicks++);
+
+ if (ret == 1)
+ return;
+
+ printf("\nCached TT Memory timings *****************************\n");
+ printf("Moving to CTT took %12lu ticks\n", *pTicks++);
+ printf("Mapping in CTT took %12lu ticks\n", *pTicks++);
+ printf("Writing to CTT took %12lu ticks\n", *pTicks++);
+ printf("Re-writing to CTT took %12lu ticks\n", *pTicks++);
+ printf("Reading from CTT took %12lu ticks\n", *pTicks++);
+ printf("\n\n");
+}
+
+int
+main()
+{
+ int ret, screen, isCapable;
+ char *displayName = ":0";
+ TinyDRIContext ctx;
+ unsigned magic;
+
+ ctx.screen = 0;
+ ctx.state = haveNothing;
+ ctx.display = XOpenDisplay(displayName);
+ if (!ctx.display) {
+ fprintf(stderr, "Could not open display\n");
+ return releaseContext(&ctx);
+ }
+ ctx.state = haveDisplay;
+
+ ret =
+ uniDRIQueryDirectRenderingCapable(ctx.display, ctx.screen,
+ &isCapable);
+ if (!ret || !isCapable) {
+ fprintf(stderr, "No DRI on this display:sceen\n");
+ return releaseContext(&ctx);
+ }
+
+ if (!uniDRIOpenConnection(ctx.display, ctx.screen, &ctx.sAreaOffset,
+ &ctx.curBusID)) {
+ fprintf(stderr, "Could not open DRI connection.\n");
+ return releaseContext(&ctx);
+ }
+ ctx.state = haveConnection;
+
+ if (!uniDRIGetClientDriverName(ctx.display, ctx.screen,
+ &ctx.ddxDriverMajor, &ctx.ddxDriverMinor,
+ &ctx.ddxDriverPatch, &ctx.driverName)) {
+ fprintf(stderr, "Could not get DRI driver name.\n");
+ return releaseContext(&ctx);
+ }
+ ctx.state = haveDriverName;
+
+ if (!uniDRIGetDeviceInfo(ctx.display, ctx.screen,
+ &ctx.fbHandle, &ctx.fbOrigin, &ctx.fbSize,
+ &ctx.fbStride, &ctx.driPrivSize, &ctx.driPriv)) {
+ fprintf(stderr, "Could not get DRI device info.\n");
+ return releaseContext(&ctx);
+ }
+ ctx.state = haveDriverName;
+
+ if ((ctx.drmFD = drmOpen(NULL, ctx.curBusID)) < 0) {
+ perror("DRM Device could not be opened");
+ return releaseContext(&ctx);
+ }
+ ctx.state = haveDRM;
+
+ drmGetMagic(ctx.drmFD, &magic);
+ if (!uniDRIAuthConnection(ctx.display, ctx.screen, magic)) {
+ fprintf(stderr, "Could not get X server to authenticate us.\n");
+ return releaseContext(&ctx);
+ }
+
+ ret = XMatchVisualInfo(ctx.display, ctx.screen, 24, TrueColor,
+ &ctx.visualInfo);
+ if (!ret) {
+ ret = XMatchVisualInfo(ctx.display, ctx.screen, 16, TrueColor,
+ &ctx.visualInfo);
+ if (!ret) {
+ fprintf(stderr, "Could not find a matching visual.\n");
+ return releaseContext(&ctx);
+ }
+ }
+
+ if (!uniDRICreateContext(ctx.display, ctx.screen, ctx.visualInfo.visual,
+ &ctx.id, &ctx.hwContext)) {
+ fprintf(stderr, "Could not create DRI context.\n");
+ return releaseContext(&ctx);
+ }
+ ctx.state = haveContext;
+
+ testAGP(&ctx);
+
+ releaseContext(&ctx);
+ printf("Terminating normally\n");
+ return 0;
+}
diff --git a/tests/ttmtest/src/xf86dri.c b/tests/ttmtest/src/xf86dri.c
new file mode 100644
index 00000000..ad92504e
--- /dev/null
+++ b/tests/ttmtest/src/xf86dri.c
@@ -0,0 +1,603 @@
+/* $XFree86: xc/lib/GL/dri/XF86dri.c,v 1.13 2002/10/30 12:51:25 alanh Exp $ */
+/**************************************************************************
+
+Copyright 1998-1999 Precision Insight, Inc., Cedar Park, Texas.
+Copyright 2000 VA Linux Systems, Inc.
+All Rights Reserved.
+
+Permission is hereby granted, free of charge, to any person obtaining a
+copy of this software and associated documentation files (the
+"Software"), to deal in the Software without restriction, including
+without limitation the rights to use, copy, modify, merge, publish,
+distribute, sub license, and/or sell copies of the Software, and to
+permit persons to whom the Software is furnished to do so, subject to
+the following conditions:
+
+The above copyright notice and this permission notice (including the
+next paragraph) shall be included in all copies or substantial portions
+of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
+ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
+**************************************************************************/
+
+/*
+ * Authors:
+ * Kevin E. Martin <martin@valinux.com>
+ * Jens Owen <jens@tungstengraphics.com>
+ * Rickard E. (Rik) Faith <faith@valinux.com>
+ *
+ */
+
+/* THIS IS NOT AN X CONSORTIUM STANDARD */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#define NEED_REPLIES
+#include <X11/Xlibint.h>
+#include <X11/extensions/Xext.h>
+#include <X11/extensions/extutil.h>
+#include "xf86dristr.h"
+
+static XExtensionInfo _xf86dri_info_data;
+static XExtensionInfo *xf86dri_info = &_xf86dri_info_data;
+static char xf86dri_extension_name[] = XF86DRINAME;
+
+#define uniDRICheckExtension(dpy,i,val) \
+ XextCheckExtension (dpy, i, xf86dri_extension_name, val)
+
+/*****************************************************************************
+ * *
+ * private utility routines *
+ * *
+ *****************************************************************************/
+
+static int close_display(Display * dpy, XExtCodes * extCodes);
+static /* const */ XExtensionHooks xf86dri_extension_hooks = {
+ NULL, /* create_gc */
+ NULL, /* copy_gc */
+ NULL, /* flush_gc */
+ NULL, /* free_gc */
+ NULL, /* create_font */
+ NULL, /* free_font */
+ close_display, /* close_display */
+ NULL, /* wire_to_event */
+ NULL, /* event_to_wire */
+ NULL, /* error */
+ NULL, /* error_string */
+};
+
+static
+XEXT_GENERATE_FIND_DISPLAY(find_display, xf86dri_info,
+ xf86dri_extension_name, &xf86dri_extension_hooks, 0, NULL)
+
+ static XEXT_GENERATE_CLOSE_DISPLAY(close_display, xf86dri_info)
+
+/*****************************************************************************
+ * *
+ * public XFree86-DRI Extension routines *
+ * *
+ *****************************************************************************/
+#if 0
+#include <stdio.h>
+#define TRACE(msg) fprintf(stderr,"uniDRI%s\n", msg);
+#else
+#define TRACE(msg)
+#endif
+ Bool uniDRIQueryExtension(dpy, event_basep, error_basep)
+ Display *dpy;
+ int *event_basep, *error_basep;
+{
+ XExtDisplayInfo *info = find_display(dpy);
+
+ TRACE("QueryExtension...");
+ if (XextHasExtension(info)) {
+ *event_basep = info->codes->first_event;
+ *error_basep = info->codes->first_error;
+ TRACE("QueryExtension... return True");
+ return True;
+ } else {
+ TRACE("QueryExtension... return False");
+ return False;
+ }
+}
+
+Bool
+uniDRIQueryVersion(dpy, majorVersion, minorVersion, patchVersion)
+ Display *dpy;
+ int *majorVersion;
+ int *minorVersion;
+ int *patchVersion;
+{
+ XExtDisplayInfo *info = find_display(dpy);
+ xXF86DRIQueryVersionReply rep;
+ xXF86DRIQueryVersionReq *req;
+
+ TRACE("QueryVersion...");
+ uniDRICheckExtension(dpy, info, False);
+
+ LockDisplay(dpy);
+ GetReq(XF86DRIQueryVersion, req);
+ req->reqType = info->codes->major_opcode;
+ req->driReqType = X_XF86DRIQueryVersion;
+ if (!_XReply(dpy, (xReply *) & rep, 0, xFalse)) {
+ UnlockDisplay(dpy);
+ SyncHandle();
+ TRACE("QueryVersion... return False");
+ return False;
+ }
+ *majorVersion = rep.majorVersion;
+ *minorVersion = rep.minorVersion;
+ *patchVersion = rep.patchVersion;
+ UnlockDisplay(dpy);
+ SyncHandle();
+ TRACE("QueryVersion... return True");
+ return True;
+}
+
+Bool
+uniDRIQueryDirectRenderingCapable(dpy, screen, isCapable)
+ Display *dpy;
+ int screen;
+ Bool *isCapable;
+{
+ XExtDisplayInfo *info = find_display(dpy);
+ xXF86DRIQueryDirectRenderingCapableReply rep;
+ xXF86DRIQueryDirectRenderingCapableReq *req;
+
+ TRACE("QueryDirectRenderingCapable...");
+ uniDRICheckExtension(dpy, info, False);
+
+ LockDisplay(dpy);
+ GetReq(XF86DRIQueryDirectRenderingCapable, req);
+ req->reqType = info->codes->major_opcode;
+ req->driReqType = X_XF86DRIQueryDirectRenderingCapable;
+ req->screen = screen;
+ if (!_XReply(dpy, (xReply *) & rep, 0, xFalse)) {
+ UnlockDisplay(dpy);
+ SyncHandle();
+ TRACE("QueryDirectRenderingCapable... return False");
+ return False;
+ }
+ *isCapable = rep.isCapable;
+ UnlockDisplay(dpy);
+ SyncHandle();
+ TRACE("QueryDirectRenderingCapable... return True");
+ return True;
+}
+
+Bool
+uniDRIOpenConnection(dpy, screen, hSAREA, busIdString)
+ Display *dpy;
+ int screen;
+ drm_handle_t *hSAREA;
+ char **busIdString;
+{
+ XExtDisplayInfo *info = find_display(dpy);
+ xXF86DRIOpenConnectionReply rep;
+ xXF86DRIOpenConnectionReq *req;
+
+ TRACE("OpenConnection...");
+ uniDRICheckExtension(dpy, info, False);
+
+ LockDisplay(dpy);
+ GetReq(XF86DRIOpenConnection, req);
+ req->reqType = info->codes->major_opcode;
+ req->driReqType = X_XF86DRIOpenConnection;
+ req->screen = screen;
+ if (!_XReply(dpy, (xReply *) & rep, 0, xFalse)) {
+ UnlockDisplay(dpy);
+ SyncHandle();
+ TRACE("OpenConnection... return False");
+ return False;
+ }
+
+ *hSAREA = rep.hSAREALow;
+#ifdef LONG64
+ if (sizeof(drm_handle_t) == 8) {
+ *hSAREA |= ((unsigned long)rep.hSAREAHigh) << 32;
+ }
+#endif
+ if (rep.length) {
+ if (!(*busIdString = (char *)Xcalloc(rep.busIdStringLength + 1, 1))) {
+ _XEatData(dpy, ((rep.busIdStringLength + 3) & ~3));
+ UnlockDisplay(dpy);
+ SyncHandle();
+ TRACE("OpenConnection... return False");
+ return False;
+ }
+ _XReadPad(dpy, *busIdString, rep.busIdStringLength);
+ } else {
+ *busIdString = NULL;
+ }
+ UnlockDisplay(dpy);
+ SyncHandle();
+ TRACE("OpenConnection... return True");
+ return True;
+}
+
+Bool
+uniDRIAuthConnection(dpy, screen, magic)
+ Display *dpy;
+ int screen;
+ drm_magic_t magic;
+{
+ XExtDisplayInfo *info = find_display(dpy);
+ xXF86DRIAuthConnectionReq *req;
+ xXF86DRIAuthConnectionReply rep;
+
+ TRACE("AuthConnection...");
+ uniDRICheckExtension(dpy, info, False);
+
+ LockDisplay(dpy);
+ GetReq(XF86DRIAuthConnection, req);
+ req->reqType = info->codes->major_opcode;
+ req->driReqType = X_XF86DRIAuthConnection;
+ req->screen = screen;
+ req->magic = magic;
+ rep.authenticated = 0;
+ if (!_XReply(dpy, (xReply *) & rep, 0, xFalse) || !rep.authenticated) {
+ UnlockDisplay(dpy);
+ SyncHandle();
+ TRACE("AuthConnection... return False");
+ return False;
+ }
+ UnlockDisplay(dpy);
+ SyncHandle();
+ TRACE("AuthConnection... return True");
+ return True;
+}
+
+Bool
+uniDRICloseConnection(dpy, screen)
+ Display *dpy;
+ int screen;
+{
+ XExtDisplayInfo *info = find_display(dpy);
+ xXF86DRICloseConnectionReq *req;
+
+ TRACE("CloseConnection...");
+
+ uniDRICheckExtension(dpy, info, False);
+
+ LockDisplay(dpy);
+ GetReq(XF86DRICloseConnection, req);
+ req->reqType = info->codes->major_opcode;
+ req->driReqType = X_XF86DRICloseConnection;
+ req->screen = screen;
+ UnlockDisplay(dpy);
+ SyncHandle();
+ TRACE("CloseConnection... return True");
+ return True;
+}
+
+Bool
+uniDRIGetClientDriverName(dpy, screen, ddxDriverMajorVersion,
+ ddxDriverMinorVersion, ddxDriverPatchVersion, clientDriverName)
+ Display *dpy;
+ int screen;
+ int *ddxDriverMajorVersion;
+ int *ddxDriverMinorVersion;
+ int *ddxDriverPatchVersion;
+ char **clientDriverName;
+{
+ XExtDisplayInfo *info = find_display(dpy);
+ xXF86DRIGetClientDriverNameReply rep;
+ xXF86DRIGetClientDriverNameReq *req;
+
+ TRACE("GetClientDriverName...");
+ uniDRICheckExtension(dpy, info, False);
+
+ LockDisplay(dpy);
+ GetReq(XF86DRIGetClientDriverName, req);
+ req->reqType = info->codes->major_opcode;
+ req->driReqType = X_XF86DRIGetClientDriverName;
+ req->screen = screen;
+ if (!_XReply(dpy, (xReply *) & rep, 0, xFalse)) {
+ UnlockDisplay(dpy);
+ SyncHandle();
+ TRACE("GetClientDriverName... return False");
+ return False;
+ }
+
+ *ddxDriverMajorVersion = rep.ddxDriverMajorVersion;
+ *ddxDriverMinorVersion = rep.ddxDriverMinorVersion;
+ *ddxDriverPatchVersion = rep.ddxDriverPatchVersion;
+
+ if (rep.length) {
+ if (!(*clientDriverName =
+ (char *)Xcalloc(rep.clientDriverNameLength + 1, 1))) {
+ _XEatData(dpy, ((rep.clientDriverNameLength + 3) & ~3));
+ UnlockDisplay(dpy);
+ SyncHandle();
+ TRACE("GetClientDriverName... return False");
+ return False;
+ }
+ _XReadPad(dpy, *clientDriverName, rep.clientDriverNameLength);
+ } else {
+ *clientDriverName = NULL;
+ }
+ UnlockDisplay(dpy);
+ SyncHandle();
+ TRACE("GetClientDriverName... return True");
+ return True;
+}
+
+Bool
+uniDRICreateContextWithConfig(dpy, screen, configID, context, hHWContext)
+ Display *dpy;
+ int screen;
+ int configID;
+ XID *context;
+ drm_context_t *hHWContext;
+{
+ XExtDisplayInfo *info = find_display(dpy);
+ xXF86DRICreateContextReply rep;
+ xXF86DRICreateContextReq *req;
+
+ TRACE("CreateContext...");
+ uniDRICheckExtension(dpy, info, False);
+
+ LockDisplay(dpy);
+ GetReq(XF86DRICreateContext, req);
+ req->reqType = info->codes->major_opcode;
+ req->driReqType = X_XF86DRICreateContext;
+ req->visual = configID;
+ req->screen = screen;
+ *context = XAllocID(dpy);
+ req->context = *context;
+ if (!_XReply(dpy, (xReply *) & rep, 0, xFalse)) {
+ UnlockDisplay(dpy);
+ SyncHandle();
+ TRACE("CreateContext... return False");
+ return False;
+ }
+ *hHWContext = rep.hHWContext;
+ UnlockDisplay(dpy);
+ SyncHandle();
+ TRACE("CreateContext... return True");
+ return True;
+}
+
+Bool
+uniDRICreateContext(dpy, screen, visual, context, hHWContext)
+ Display *dpy;
+ int screen;
+ Visual *visual;
+ XID *context;
+ drm_context_t *hHWContext;
+{
+ return uniDRICreateContextWithConfig(dpy, screen, visual->visualid,
+ context, hHWContext);
+}
+
+Bool
+uniDRIDestroyContext(Display * ndpy, int screen, XID context)
+{
+ Display *const dpy = (Display *) ndpy;
+ XExtDisplayInfo *info = find_display(dpy);
+ xXF86DRIDestroyContextReq *req;
+
+ TRACE("DestroyContext...");
+ uniDRICheckExtension(dpy, info, False);
+
+ LockDisplay(dpy);
+ GetReq(XF86DRIDestroyContext, req);
+ req->reqType = info->codes->major_opcode;
+ req->driReqType = X_XF86DRIDestroyContext;
+ req->screen = screen;
+ req->context = context;
+ UnlockDisplay(dpy);
+ SyncHandle();
+ TRACE("DestroyContext... return True");
+ return True;
+}
+
+Bool
+uniDRICreateDrawable(Display * ndpy, int screen,
+ Drawable drawable, drm_drawable_t * hHWDrawable)
+{
+ Display *const dpy = (Display *) ndpy;
+ XExtDisplayInfo *info = find_display(dpy);
+ xXF86DRICreateDrawableReply rep;
+ xXF86DRICreateDrawableReq *req;
+
+ TRACE("CreateDrawable...");
+ uniDRICheckExtension(dpy, info, False);
+
+ LockDisplay(dpy);
+ GetReq(XF86DRICreateDrawable, req);
+ req->reqType = info->codes->major_opcode;
+ req->driReqType = X_XF86DRICreateDrawable;
+ req->screen = screen;
+ req->drawable = drawable;
+ if (!_XReply(dpy, (xReply *) & rep, 0, xFalse)) {
+ UnlockDisplay(dpy);
+ SyncHandle();
+ TRACE("CreateDrawable... return False");
+ return False;
+ }
+ *hHWDrawable = rep.hHWDrawable;
+ UnlockDisplay(dpy);
+ SyncHandle();
+ TRACE("CreateDrawable... return True");
+ return True;
+}
+
+Bool
+uniDRIDestroyDrawable(Display * ndpy, int screen, Drawable drawable)
+{
+ Display *const dpy = (Display *) ndpy;
+ XExtDisplayInfo *info = find_display(dpy);
+ xXF86DRIDestroyDrawableReq *req;
+
+ TRACE("DestroyDrawable...");
+ uniDRICheckExtension(dpy, info, False);
+
+ LockDisplay(dpy);
+ GetReq(XF86DRIDestroyDrawable, req);
+ req->reqType = info->codes->major_opcode;
+ req->driReqType = X_XF86DRIDestroyDrawable;
+ req->screen = screen;
+ req->drawable = drawable;
+ UnlockDisplay(dpy);
+ SyncHandle();
+ TRACE("DestroyDrawable... return True");
+ return True;
+}
+
+Bool
+uniDRIGetDrawableInfo(Display * dpy, int screen, Drawable drawable,
+ unsigned int *index, unsigned int *stamp,
+ int *X, int *Y, int *W, int *H,
+ int *numClipRects, drm_clip_rect_t ** pClipRects,
+ int *backX, int *backY,
+ int *numBackClipRects, drm_clip_rect_t ** pBackClipRects)
+{
+ XExtDisplayInfo *info = find_display(dpy);
+ xXF86DRIGetDrawableInfoReply rep;
+ xXF86DRIGetDrawableInfoReq *req;
+ int total_rects;
+
+ TRACE("GetDrawableInfo...");
+ uniDRICheckExtension(dpy, info, False);
+
+ LockDisplay(dpy);
+ GetReq(XF86DRIGetDrawableInfo, req);
+ req->reqType = info->codes->major_opcode;
+ req->driReqType = X_XF86DRIGetDrawableInfo;
+ req->screen = screen;
+ req->drawable = drawable;
+
+ if (!_XReply(dpy, (xReply *) & rep, 1, xFalse)) {
+ UnlockDisplay(dpy);
+ SyncHandle();
+ TRACE("GetDrawableInfo... return False");
+ return False;
+ }
+ *index = rep.drawableTableIndex;
+ *stamp = rep.drawableTableStamp;
+ *X = (int)rep.drawableX;
+ *Y = (int)rep.drawableY;
+ *W = (int)rep.drawableWidth;
+ *H = (int)rep.drawableHeight;
+ *numClipRects = rep.numClipRects;
+ total_rects = *numClipRects;
+
+ *backX = rep.backX;
+ *backY = rep.backY;
+ *numBackClipRects = rep.numBackClipRects;
+ total_rects += *numBackClipRects;
+
+#if 0
+ /* Because of the fix in Xserver/GL/dri/xf86dri.c, this check breaks
+ * backwards compatibility (Because of the >> 2 shift) but the fix
+ * enables multi-threaded apps to work.
+ */
+ if (rep.length != ((((SIZEOF(xXF86DRIGetDrawableInfoReply) -
+ SIZEOF(xGenericReply) +
+ total_rects * sizeof(drm_clip_rect_t)) +
+ 3) & ~3) >> 2)) {
+ _XEatData(dpy, rep.length);
+ UnlockDisplay(dpy);
+ SyncHandle();
+ TRACE("GetDrawableInfo... return False");
+ return False;
+ }
+#endif
+
+ if (*numClipRects) {
+ int len = sizeof(drm_clip_rect_t) * (*numClipRects);
+
+ *pClipRects = (drm_clip_rect_t *) Xcalloc(len, 1);
+ if (*pClipRects)
+ _XRead(dpy, (char *)*pClipRects, len);
+ } else {
+ *pClipRects = NULL;
+ }
+
+ if (*numBackClipRects) {
+ int len = sizeof(drm_clip_rect_t) * (*numBackClipRects);
+
+ *pBackClipRects = (drm_clip_rect_t *) Xcalloc(len, 1);
+ if (*pBackClipRects)
+ _XRead(dpy, (char *)*pBackClipRects, len);
+ } else {
+ *pBackClipRects = NULL;
+ }
+
+ UnlockDisplay(dpy);
+ SyncHandle();
+ TRACE("GetDrawableInfo... return True");
+ return True;
+}
+
+Bool
+uniDRIGetDeviceInfo(dpy, screen, hFrameBuffer,
+ fbOrigin, fbSize, fbStride, devPrivateSize, pDevPrivate)
+ Display *dpy;
+ int screen;
+ drm_handle_t *hFrameBuffer;
+ int *fbOrigin;
+ int *fbSize;
+ int *fbStride;
+ int *devPrivateSize;
+ void **pDevPrivate;
+{
+ XExtDisplayInfo *info = find_display(dpy);
+ xXF86DRIGetDeviceInfoReply rep;
+ xXF86DRIGetDeviceInfoReq *req;
+
+ TRACE("GetDeviceInfo...");
+ uniDRICheckExtension(dpy, info, False);
+
+ LockDisplay(dpy);
+ GetReq(XF86DRIGetDeviceInfo, req);
+ req->reqType = info->codes->major_opcode;
+ req->driReqType = X_XF86DRIGetDeviceInfo;
+ req->screen = screen;
+ if (!_XReply(dpy, (xReply *) & rep, 0, xFalse)) {
+ UnlockDisplay(dpy);
+ SyncHandle();
+ TRACE("GetDeviceInfo... return False");
+ return False;
+ }
+
+ *hFrameBuffer = rep.hFrameBufferLow;
+#ifdef LONG64
+ if (sizeof(drm_handle_t) == 8) {
+ *hFrameBuffer |= ((unsigned long)rep.hFrameBufferHigh) << 32;
+ }
+#endif
+
+ *fbOrigin = rep.framebufferOrigin;
+ *fbSize = rep.framebufferSize;
+ *fbStride = rep.framebufferStride;
+ *devPrivateSize = rep.devPrivateSize;
+
+ if (rep.length) {
+ if (!(*pDevPrivate = (void *)Xcalloc(rep.devPrivateSize, 1))) {
+ _XEatData(dpy, ((rep.devPrivateSize + 3) & ~3));
+ UnlockDisplay(dpy);
+ SyncHandle();
+ TRACE("GetDeviceInfo... return False");
+ return False;
+ }
+ _XRead(dpy, (char *)*pDevPrivate, rep.devPrivateSize);
+ } else {
+ *pDevPrivate = NULL;
+ }
+
+ UnlockDisplay(dpy);
+ SyncHandle();
+ TRACE("GetDeviceInfo... return True");
+ return True;
+}
diff --git a/tests/ttmtest/src/xf86dri.h b/tests/ttmtest/src/xf86dri.h
new file mode 100644
index 00000000..8fb78968
--- /dev/null
+++ b/tests/ttmtest/src/xf86dri.h
@@ -0,0 +1,116 @@
+/* $XFree86: xc/lib/GL/dri/xf86dri.h,v 1.8 2002/10/30 12:51:25 alanh Exp $ */
+/**************************************************************************
+
+Copyright 1998-1999 Precision Insight, Inc., Cedar Park, Texas.
+Copyright 2000 VA Linux Systems, Inc.
+All Rights Reserved.
+
+Permission is hereby granted, free of charge, to any person obtaining a
+copy of this software and associated documentation files (the
+"Software"), to deal in the Software without restriction, including
+without limitation the rights to use, copy, modify, merge, publish,
+distribute, sub license, and/or sell copies of the Software, and to
+permit persons to whom the Software is furnished to do so, subject to
+the following conditions:
+
+The above copyright notice and this permission notice (including the
+next paragraph) shall be included in all copies or substantial portions
+of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
+ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
+**************************************************************************/
+
+/**
+ * \file xf86dri.h
+ * Protocol numbers and function prototypes for DRI X protocol.
+ *
+ * \author Kevin E. Martin <martin@valinux.com>
+ * \author Jens Owen <jens@tungstengraphics.com>
+ * \author Rickard E. (Rik) Faith <faith@valinux.com>
+ */
+
+#ifndef _XF86DRI_H_
+#define _XF86DRI_H_
+
+#include <X11/Xfuncproto.h>
+#include <drm/drm.h>
+
+#define X_XF86DRIQueryVersion 0
+#define X_XF86DRIQueryDirectRenderingCapable 1
+#define X_XF86DRIOpenConnection 2
+#define X_XF86DRICloseConnection 3
+#define X_XF86DRIGetClientDriverName 4
+#define X_XF86DRICreateContext 5
+#define X_XF86DRIDestroyContext 6
+#define X_XF86DRICreateDrawable 7
+#define X_XF86DRIDestroyDrawable 8
+#define X_XF86DRIGetDrawableInfo 9
+#define X_XF86DRIGetDeviceInfo 10
+#define X_XF86DRIAuthConnection 11
+#define X_XF86DRIOpenFullScreen 12 /* Deprecated */
+#define X_XF86DRICloseFullScreen 13 /* Deprecated */
+
+#define XF86DRINumberEvents 0
+
+#define XF86DRIClientNotLocal 0
+#define XF86DRIOperationNotSupported 1
+#define XF86DRINumberErrors (XF86DRIOperationNotSupported + 1)
+
+#ifndef _XF86DRI_SERVER_
+
+_XFUNCPROTOBEGIN
+ Bool uniDRIQueryExtension(Display * dpy, int *event_base,
+ int *error_base);
+
+Bool uniDRIQueryVersion(Display * dpy, int *majorVersion, int *minorVersion,
+ int *patchVersion);
+
+Bool uniDRIQueryDirectRenderingCapable(Display * dpy, int screen,
+ Bool * isCapable);
+
+Bool uniDRIOpenConnection(Display * dpy, int screen, drm_handle_t * hSAREA,
+ char **busIDString);
+
+Bool uniDRIAuthConnection(Display * dpy, int screen, drm_magic_t magic);
+
+Bool uniDRICloseConnection(Display * dpy, int screen);
+
+Bool uniDRIGetClientDriverName(Display * dpy, int screen,
+ int *ddxDriverMajorVersion, int *ddxDriverMinorVersion,
+ int *ddxDriverPatchVersion, char **clientDriverName);
+
+Bool uniDRICreateContext(Display * dpy, int screen, Visual * visual,
+ XID * ptr_to_returned_context_id, drm_context_t * hHWContext);
+
+Bool uniDRICreateContextWithConfig(Display * dpy, int screen, int configID,
+ XID * ptr_to_returned_context_id, drm_context_t * hHWContext);
+
+extern Bool uniDRIDestroyContext(Display * dpy, int screen, XID context_id);
+
+extern Bool uniDRICreateDrawable(Display * dpy, int screen,
+ Drawable drawable, drm_drawable_t * hHWDrawable);
+
+extern Bool uniDRIDestroyDrawable(Display * dpy, int screen,
+ Drawable drawable);
+
+Bool uniDRIGetDrawableInfo(Display * dpy, int screen, Drawable drawable,
+ unsigned int *index, unsigned int *stamp,
+ int *X, int *Y, int *W, int *H,
+ int *numClipRects, drm_clip_rect_t ** pClipRects,
+ int *backX, int *backY,
+ int *numBackClipRects, drm_clip_rect_t ** pBackClipRects);
+
+Bool uniDRIGetDeviceInfo(Display * dpy, int screen,
+ drm_handle_t * hFrameBuffer, int *fbOrigin, int *fbSize,
+ int *fbStride, int *devPrivateSize, void **pDevPrivate);
+
+_XFUNCPROTOEND
+#endif /* _XF86DRI_SERVER_ */
+#endif /* _XF86DRI_H_ */
diff --git a/tests/ttmtest/src/xf86dristr.h b/tests/ttmtest/src/xf86dristr.h
new file mode 100644
index 00000000..3b43438e
--- /dev/null
+++ b/tests/ttmtest/src/xf86dristr.h
@@ -0,0 +1,390 @@
+/* $XFree86: xc/lib/GL/dri/xf86dristr.h,v 1.10 2002/10/30 12:51:25 alanh Exp $ */
+/**************************************************************************
+
+Copyright 1998-1999 Precision Insight, Inc., Cedar Park, Texas.
+Copyright 2000 VA Linux Systems, Inc.
+All Rights Reserved.
+
+Permission is hereby granted, free of charge, to any person obtaining a
+copy of this software and associated documentation files (the
+"Software"), to deal in the Software without restriction, including
+without limitation the rights to use, copy, modify, merge, publish,
+distribute, sub license, and/or sell copies of the Software, and to
+permit persons to whom the Software is furnished to do so, subject to
+the following conditions:
+
+The above copyright notice and this permission notice (including the
+next paragraph) shall be included in all copies or substantial portions
+of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
+ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
+**************************************************************************/
+
+/*
+ * Authors:
+ * Kevin E. Martin <martin@valinux.com>
+ * Jens Owen <jens@tungstengraphics.com>
+ * Rickard E. (Rik) Fiath <faith@valinux.com>
+ *
+ */
+
+#ifndef _XF86DRISTR_H_
+#define _XF86DRISTR_H_
+
+#include "xf86dri.h"
+
+#define XF86DRINAME "XFree86-DRI"
+
+/* The DRI version number. This was originally set to be the same of the
+ * XFree86 version number. However, this version is really indepedent of
+ * the XFree86 version.
+ *
+ * Version History:
+ * 4.0.0: Original
+ * 4.0.1: Patch to bump clipstamp when windows are destroyed, 28 May 02
+ * 4.1.0: Add transition from single to multi in DRMInfo rec, 24 Jun 02
+ */
+#define XF86DRI_MAJOR_VERSION 4
+#define XF86DRI_MINOR_VERSION 1
+#define XF86DRI_PATCH_VERSION 0
+
+typedef struct _XF86DRIQueryVersion
+{
+ CARD8 reqType; /* always DRIReqCode */
+ CARD8 driReqType; /* always X_DRIQueryVersion */
+ CARD16 length B16;
+} xXF86DRIQueryVersionReq;
+
+#define sz_xXF86DRIQueryVersionReq 4
+
+typedef struct
+{
+ BYTE type; /* X_Reply */
+ BOOL pad1;
+ CARD16 sequenceNumber B16;
+ CARD32 length B32;
+ CARD16 majorVersion B16; /* major version of DRI protocol */
+ CARD16 minorVersion B16; /* minor version of DRI protocol */
+ CARD32 patchVersion B32; /* patch version of DRI protocol */
+ CARD32 pad3 B32;
+ CARD32 pad4 B32;
+ CARD32 pad5 B32;
+ CARD32 pad6 B32;
+} xXF86DRIQueryVersionReply;
+
+#define sz_xXF86DRIQueryVersionReply 32
+
+typedef struct _XF86DRIQueryDirectRenderingCapable
+{
+ CARD8 reqType; /* always DRIReqCode */
+ CARD8 driReqType; /* X_DRIQueryDirectRenderingCapable */
+ CARD16 length B16;
+ CARD32 screen B32;
+} xXF86DRIQueryDirectRenderingCapableReq;
+
+#define sz_xXF86DRIQueryDirectRenderingCapableReq 8
+
+typedef struct
+{
+ BYTE type; /* X_Reply */
+ BOOL pad1;
+ CARD16 sequenceNumber B16;
+ CARD32 length B32;
+ BOOL isCapable;
+ BOOL pad2;
+ BOOL pad3;
+ BOOL pad4;
+ CARD32 pad5 B32;
+ CARD32 pad6 B32;
+ CARD32 pad7 B32;
+ CARD32 pad8 B32;
+ CARD32 pad9 B32;
+} xXF86DRIQueryDirectRenderingCapableReply;
+
+#define sz_xXF86DRIQueryDirectRenderingCapableReply 32
+
+typedef struct _XF86DRIOpenConnection
+{
+ CARD8 reqType; /* always DRIReqCode */
+ CARD8 driReqType; /* always X_DRIOpenConnection */
+ CARD16 length B16;
+ CARD32 screen B32;
+} xXF86DRIOpenConnectionReq;
+
+#define sz_xXF86DRIOpenConnectionReq 8
+
+typedef struct
+{
+ BYTE type; /* X_Reply */
+ BOOL pad1;
+ CARD16 sequenceNumber B16;
+ CARD32 length B32;
+ CARD32 hSAREALow B32;
+ CARD32 hSAREAHigh B32;
+ CARD32 busIdStringLength B32;
+ CARD32 pad6 B32;
+ CARD32 pad7 B32;
+ CARD32 pad8 B32;
+} xXF86DRIOpenConnectionReply;
+
+#define sz_xXF86DRIOpenConnectionReply 32
+
+typedef struct _XF86DRIAuthConnection
+{
+ CARD8 reqType; /* always DRIReqCode */
+ CARD8 driReqType; /* always X_DRICloseConnection */
+ CARD16 length B16;
+ CARD32 screen B32;
+ CARD32 magic B32;
+} xXF86DRIAuthConnectionReq;
+
+#define sz_xXF86DRIAuthConnectionReq 12
+
+typedef struct
+{
+ BYTE type;
+ BOOL pad1;
+ CARD16 sequenceNumber B16;
+ CARD32 length B32;
+ CARD32 authenticated B32;
+ CARD32 pad2 B32;
+ CARD32 pad3 B32;
+ CARD32 pad4 B32;
+ CARD32 pad5 B32;
+ CARD32 pad6 B32;
+} xXF86DRIAuthConnectionReply;
+
+#define zx_xXF86DRIAuthConnectionReply 32
+
+typedef struct _XF86DRICloseConnection
+{
+ CARD8 reqType; /* always DRIReqCode */
+ CARD8 driReqType; /* always X_DRICloseConnection */
+ CARD16 length B16;
+ CARD32 screen B32;
+} xXF86DRICloseConnectionReq;
+
+#define sz_xXF86DRICloseConnectionReq 8
+
+typedef struct _XF86DRIGetClientDriverName
+{
+ CARD8 reqType; /* always DRIReqCode */
+ CARD8 driReqType; /* always X_DRIGetClientDriverName */
+ CARD16 length B16;
+ CARD32 screen B32;
+} xXF86DRIGetClientDriverNameReq;
+
+#define sz_xXF86DRIGetClientDriverNameReq 8
+
+typedef struct
+{
+ BYTE type; /* X_Reply */
+ BOOL pad1;
+ CARD16 sequenceNumber B16;
+ CARD32 length B32;
+ CARD32 ddxDriverMajorVersion B32;
+ CARD32 ddxDriverMinorVersion B32;
+ CARD32 ddxDriverPatchVersion B32;
+ CARD32 clientDriverNameLength B32;
+ CARD32 pad5 B32;
+ CARD32 pad6 B32;
+} xXF86DRIGetClientDriverNameReply;
+
+#define sz_xXF86DRIGetClientDriverNameReply 32
+
+typedef struct _XF86DRICreateContext
+{
+ CARD8 reqType; /* always DRIReqCode */
+ CARD8 driReqType; /* always X_DRICreateContext */
+ CARD16 length B16;
+ CARD32 screen B32;
+ CARD32 visual B32;
+ CARD32 context B32;
+} xXF86DRICreateContextReq;
+
+#define sz_xXF86DRICreateContextReq 16
+
+typedef struct
+{
+ BYTE type; /* X_Reply */
+ BOOL pad1;
+ CARD16 sequenceNumber B16;
+ CARD32 length B32;
+ CARD32 hHWContext B32;
+ CARD32 pad2 B32;
+ CARD32 pad3 B32;
+ CARD32 pad4 B32;
+ CARD32 pad5 B32;
+ CARD32 pad6 B32;
+} xXF86DRICreateContextReply;
+
+#define sz_xXF86DRICreateContextReply 32
+
+typedef struct _XF86DRIDestroyContext
+{
+ CARD8 reqType; /* always DRIReqCode */
+ CARD8 driReqType; /* always X_DRIDestroyContext */
+ CARD16 length B16;
+ CARD32 screen B32;
+ CARD32 context B32;
+} xXF86DRIDestroyContextReq;
+
+#define sz_xXF86DRIDestroyContextReq 12
+
+typedef struct _XF86DRICreateDrawable
+{
+ CARD8 reqType; /* always DRIReqCode */
+ CARD8 driReqType; /* always X_DRICreateDrawable */
+ CARD16 length B16;
+ CARD32 screen B32;
+ CARD32 drawable B32;
+} xXF86DRICreateDrawableReq;
+
+#define sz_xXF86DRICreateDrawableReq 12
+
+typedef struct
+{
+ BYTE type; /* X_Reply */
+ BOOL pad1;
+ CARD16 sequenceNumber B16;
+ CARD32 length B32;
+ CARD32 hHWDrawable B32;
+ CARD32 pad2 B32;
+ CARD32 pad3 B32;
+ CARD32 pad4 B32;
+ CARD32 pad5 B32;
+ CARD32 pad6 B32;
+} xXF86DRICreateDrawableReply;
+
+#define sz_xXF86DRICreateDrawableReply 32
+
+typedef struct _XF86DRIDestroyDrawable
+{
+ CARD8 reqType; /* always DRIReqCode */
+ CARD8 driReqType; /* always X_DRIDestroyDrawable */
+ CARD16 length B16;
+ CARD32 screen B32;
+ CARD32 drawable B32;
+} xXF86DRIDestroyDrawableReq;
+
+#define sz_xXF86DRIDestroyDrawableReq 12
+
+typedef struct _XF86DRIGetDrawableInfo
+{
+ CARD8 reqType; /* always DRIReqCode */
+ CARD8 driReqType; /* always X_DRIGetDrawableInfo */
+ CARD16 length B16;
+ CARD32 screen B32;
+ CARD32 drawable B32;
+} xXF86DRIGetDrawableInfoReq;
+
+#define sz_xXF86DRIGetDrawableInfoReq 12
+
+typedef struct
+{
+ BYTE type; /* X_Reply */
+ BOOL pad1;
+ CARD16 sequenceNumber B16;
+ CARD32 length B32;
+ CARD32 drawableTableIndex B32;
+ CARD32 drawableTableStamp B32;
+ INT16 drawableX B16;
+ INT16 drawableY B16;
+ INT16 drawableWidth B16;
+ INT16 drawableHeight B16;
+ CARD32 numClipRects B32;
+ INT16 backX B16;
+ INT16 backY B16;
+ CARD32 numBackClipRects B32;
+} xXF86DRIGetDrawableInfoReply;
+
+#define sz_xXF86DRIGetDrawableInfoReply 36
+
+typedef struct _XF86DRIGetDeviceInfo
+{
+ CARD8 reqType; /* always DRIReqCode */
+ CARD8 driReqType; /* always X_DRIGetDeviceInfo */
+ CARD16 length B16;
+ CARD32 screen B32;
+} xXF86DRIGetDeviceInfoReq;
+
+#define sz_xXF86DRIGetDeviceInfoReq 8
+
+typedef struct
+{
+ BYTE type; /* X_Reply */
+ BOOL pad1;
+ CARD16 sequenceNumber B16;
+ CARD32 length B32;
+ CARD32 hFrameBufferLow B32;
+ CARD32 hFrameBufferHigh B32;
+ CARD32 framebufferOrigin B32;
+ CARD32 framebufferSize B32;
+ CARD32 framebufferStride B32;
+ CARD32 devPrivateSize B32;
+} xXF86DRIGetDeviceInfoReply;
+
+#define sz_xXF86DRIGetDeviceInfoReply 32
+
+typedef struct _XF86DRIOpenFullScreen
+{
+ CARD8 reqType; /* always DRIReqCode */
+ CARD8 driReqType; /* always X_DRIOpenFullScreen */
+ CARD16 length B16;
+ CARD32 screen B32;
+ CARD32 drawable B32;
+} xXF86DRIOpenFullScreenReq;
+
+#define sz_xXF86DRIOpenFullScreenReq 12
+
+typedef struct
+{
+ BYTE type;
+ BOOL pad1;
+ CARD16 sequenceNumber B16;
+ CARD32 length B32;
+ CARD32 isFullScreen B32;
+ CARD32 pad2 B32;
+ CARD32 pad3 B32;
+ CARD32 pad4 B32;
+ CARD32 pad5 B32;
+ CARD32 pad6 B32;
+} xXF86DRIOpenFullScreenReply;
+
+#define sz_xXF86DRIOpenFullScreenReply 32
+
+typedef struct _XF86DRICloseFullScreen
+{
+ CARD8 reqType; /* always DRIReqCode */
+ CARD8 driReqType; /* always X_DRICloseFullScreen */
+ CARD16 length B16;
+ CARD32 screen B32;
+ CARD32 drawable B32;
+} xXF86DRICloseFullScreenReq;
+
+#define sz_xXF86DRICloseFullScreenReq 12
+
+typedef struct
+{
+ BYTE type;
+ BOOL pad1;
+ CARD16 sequenceNumber B16;
+ CARD32 length B32;
+ CARD32 pad2 B32;
+ CARD32 pad3 B32;
+ CARD32 pad4 B32;
+ CARD32 pad5 B32;
+ CARD32 pad6 B32;
+ CARD32 pad7 B32;
+} xXF86DRICloseFullScreenReply;
+
+#define sz_xXF86DRICloseFullScreenReply 32
+
+#endif /* _XF86DRISTR_H_ */