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authorMichel Dänzer <michel.daenzer@amd.com>2013-09-18 15:43:05 +0200
committerMichel Dänzer <michel@daenzer.net>2013-09-18 18:28:51 +0200
commita48d6e5621fea701e36724cc144d9fe293332824 (patch)
tree222fc73f71efb6686e4076b9afc243e7ec3ad520 /include
parentb6da447c04ea3f243b56dc964bc8d43bba003ae2 (diff)
radeon: Fix tiling mode index for 1D tiled depth/stencil surfaces on CIK
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'include')
-rw-r--r--include/drm/radeon_drm.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/include/drm/radeon_drm.h b/include/drm/radeon_drm.h
index 86cef15d..d1bebf5a 100644
--- a/include/drm/radeon_drm.h
+++ b/include/drm/radeon_drm.h
@@ -1004,4 +1004,6 @@ struct drm_radeon_info {
#define SI_TILE_MODE_DEPTH_STENCIL_2D_4AA 3
#define SI_TILE_MODE_DEPTH_STENCIL_2D_8AA 2
+#define CIK_TILE_MODE_DEPTH_STENCIL_1D 5
+
#endif