From a48d6e5621fea701e36724cc144d9fe293332824 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michel=20D=C3=A4nzer?= Date: Wed, 18 Sep 2013 15:43:05 +0200 Subject: radeon: Fix tiling mode index for 1D tiled depth/stencil surfaces on CIK Reviewed-by: Alex Deucher --- include/drm/radeon_drm.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/drm/radeon_drm.h b/include/drm/radeon_drm.h index 86cef15d..d1bebf5a 100644 --- a/include/drm/radeon_drm.h +++ b/include/drm/radeon_drm.h @@ -1004,4 +1004,6 @@ struct drm_radeon_info { #define SI_TILE_MODE_DEPTH_STENCIL_2D_4AA 3 #define SI_TILE_MODE_DEPTH_STENCIL_2D_8AA 2 +#define CIK_TILE_MODE_DEPTH_STENCIL_1D 5 + #endif -- cgit v1.2.3