/* r128_cce.c -- ATI Rage 128 driver -*- linux-c -*- * Created: Wed Apr 5 19:24:19 2000 by kevin@precisioninsight.com * * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. * * Authors: * Gareth Hughes */ #include "r128.h" #include "drmP.h" #include "drm.h" #include "r128_drm.h" #include "r128_drv.h" #define R128_FIFO_DEBUG 0 /* CCE microcode (from ATI) */ static u32 r128_cce_microcode[] = { 0, 276838400, 0, 268449792, 2, 142, 2, 145, 0, 1076765731, 0, 1617039951, 0, 774592877, 0, 1987540286, 0, 2307490946U, 0, 599558925, 0, 589505315, 0, 596487092, 0, 589505315, 1, 11544576, 1, 206848, 1, 311296, 1, 198656, 2, 912273422, 11, 262144, 0, 0, 1, 33559837, 1, 7438, 1, 14809, 1, 6615, 12, 28, 1, 6614, 12, 28, 2, 23, 11, 18874368, 0, 16790922, 1, 409600, 9, 30, 1, 147854772, 16, 420483072, 3, 8192, 0, 10240, 1, 198656, 1, 15630, 1, 51200, 10, 34858, 9, 42, 1, 33559823, 2, 10276, 1, 15717, 1, 15718, 2, 43, 1, 15936948, 1, 570480831, 1, 14715071, 12, 322123831, 1, 33953125, 12, 55, 1, 33559908, 1, 15718, 2, 46, 4, 2099258, 1, 526336, 1, 442623, 4, 4194365, 1, 509952, 1, 459007, 3, 0, 12, 92, 2, 46, 12, 176, 1, 15734, 1, 206848, 1, 18432, 1, 133120, 1, 100670734, 1, 149504, 1, 165888, 1, 15975928, 1, 1048576, 6, 3145806, 1, 15715, 16, 2150645232U, 2, 268449859, 2, 10307, 12, 176, 1, 15734, 1, 15735, 1, 15630, 1, 15631, 1, 5253120, 6, 3145810, 16, 2150645232U, 1, 15864, 2, 82, 1, 343310, 1, 1064207, 2, 3145813, 1, 15728, 1, 7817, 1, 15729, 3, 15730, 12, 92, 2, 98, 1, 16168, 1, 16167, 1, 16002, 1, 16008, 1, 15974, 1, 15975, 1, 15990, 1, 15976, 1, 15977, 1, 15980, 0, 15981, 1, 10240, 1, 5253120, 1, 15720, 1, 198656, 6, 110, 1, 180224, 1, 103824738, 2, 112, 2, 3145839, 0, 536885440, 1, 114880, 14, 125, 12, 206975, 1, 33559995, 12, 198784, 0, 33570236, 1, 15803, 0, 15804, 3, 294912, 1, 294912, 3, 442370, 1, 11544576, 0, 811612160, 1, 12593152, 1, 11536384, 1, 14024704, 7, 310382726, 0, 10240, 1, 14796, 1, 14797, 1, 14793, 1, 14794, 0, 14795, 1, 268679168, 1, 9437184, 1, 268449792, 1, 198656, 1, 9452827, 1, 1075854602, 1, 1075854603, 1, 557056, 1, 114880, 14, 159, 12, 198784, 1, 1109409213, 12, 198783, 1, 1107312059, 12, 198784, 1, 1109409212, 2, 162, 1, 1075854781, 1, 1073757627, 1, 1075854780, 1, 540672, 1, 10485760, 6, 3145894, 16, 274741248, 9, 168, 3, 4194304, 3, 4209949, 0, 0, 0, 256, 14, 174, 1, 114857, 1, 33560007, 12, 176, 0, 10240, 1, 114858, 1, 33560018, 1, 114857, 3, 33560007, 1, 16008, 1, 114874, 1, 33560360, 1, 114875, 1, 33560154, 0, 15963, 0, 256, 0, 4096, 1, 409611, 9, 188, 0, 10240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; int r128_do_wait_for_idle( drm_r128_private_t *dev_priv ); int R128_READ_PLL(drm_device_t *dev, int addr) { drm_r128_private_t *dev_priv = dev->dev_private; R128_WRITE8(R128_CLOCK_CNTL_INDEX, addr & 0x1f); return R128_READ(R128_CLOCK_CNTL_DATA); } #if R128_FIFO_DEBUG static void r128_status( drm_r128_private_t *dev_priv ) { printk( "GUI_STAT = 0x%08x\n", (unsigned int)R128_READ( R128_GUI_STAT ) ); printk( "PM4_STAT = 0x%08x\n", (unsigned int)R128_READ( R128_PM4_STAT ) ); printk( "PM4_BUFFER_DL_WPTR = 0x%08x\n", (unsigned int)R128_READ( R128_PM4_BUFFER_DL_WPTR ) ); printk( "PM4_BUFFER_DL_RPTR = 0x%08x\n", (unsigned int)R128_READ( R128_PM4_BUFFER_DL_RPTR ) ); printk( "PM4_MICRO_CNTL = 0x%08x\n", (unsigned int)R128_READ( R128_PM4_MICRO_CNTL ) ); printk( "PM4_BUFFER_CNTL = 0x%08x\n", (unsigned int)R128_READ( R128_PM4_BUFFER_CNTL ) ); } #endif /* ================================================================ * Engine, FIFO control */ static int r128_do_pixcache_flush( drm_r128_private_t *dev_priv ) { u32 tmp; int i; tmp = R128_READ( R128_PC_NGUI_CTLSTAT ) | R128_PC_FLUSH_ALL; R128_WRITE( R128_PC_NGUI_CTLSTAT, tmp ); for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { if ( !(R128_READ( R128_PC_NGUI_CTLSTAT ) & R128_PC_BUSY) ) { return 0; } DRM_UDELAY( 1 ); } #if R128_FIFO_DEBUG DRM_ERROR( "failed!\n" ); #endif return DRM_ERR(EBUSY); } static int r128_do_wait_for_fifo( drm_r128_private_t *dev_priv, int entries ) { int i; for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { int slots = R128_READ( R128_GUI_STAT ) & R128_GUI_FIFOCNT_MASK; if ( slots >= entries ) return 0; DRM_UDELAY( 1 ); } #if R128_FIFO_DEBUG DRM_ERROR( "failed!\n" ); #endif return DRM_ERR(EBUSY); } int r128_do_wait_for_idle( drm_r128_private_t *dev_priv ) { int i, ret; ret = r128_do_wait_for_fifo( dev_priv, 64 ); if ( ret ) return ret; for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { if ( !(R128_READ( R128_GUI_STAT ) & R128_GUI_ACTIVE) ) { r128_do_pixcache_flush( dev_priv ); return 0; } DRM_UDELAY( 1 ); } #if R128_FIFO_DEBUG DRM_ERROR( "failed!\n" ); #endif return DRM_ERR(EBUSY); } /* ================================================================ * CCE control, initialization */ /* Load the microcode for the CCE */ static void r128_cce_load_microcode( drm_r128_private_t *dev_priv ) { int i; DRM_DEBUG( "\n" ); r128_do_wait_for_idle( dev_priv ); R128_WRITE( R128_PM4_MICROCODE_ADDR, 0 ); for ( i = 0 ; i < 256 ; i++ ) { R128_WRITE( R128_PM4_MICROCODE_DATAH, r128_cce_microcode[i * 2] ); R128_WRITE( R128_PM4_MICROCODE_DATAL, r128_cce_microcode[i * 2 + 1] ); } } /* Flush any pending commands to the CCE. This should only be used just * prior to a wait for idle, as it informs the engine that the command * stream is ending. */ static void r128_do_cce_flush( drm_r128_private_t *dev_priv ) { u32 tmp; tmp = R128_READ( R128_PM4_BUFFER_DL_WPTR ) | R128_PM4_BUFFER_DL_DONE; R128_WRITE( R128_PM4_BUFFER_DL_WPTR, tmp ); } /* Wait for the CCE to go idle. */ iMultimedia-chat-meeting-2018-08-23 11:16 < pinchartl> welcome to the multimedia meeting! 11:16 < pinchartl> Topic 1. Status Check for the Multimedia Tasks 11:16 < pinchartl> * Jacopo 11:16 < pinchartl> Since last meeting: 11:16 < pinchartl> - Ebisu HDMI and CVBS integration 11:16 < pinchartl> [RFT 0/8] arm64: dts: renesas: Ebisu: Add HDMI and CVBS input 11:16 < pinchartl> - DU non DPLL channel clock selection 11:16 < pinchartl> [PATCH v2 0/2] drm: rcar-du: Rework clock configuration 11:16 < pinchartl> Tested Laurent's re-implementation 11:16 < pinchartl> - More DU work 11:16 < pinchartl> [PATCH 0/3] drm: rcar-du: A few cosmetic changes 11:16 < pinchartl> WIP: Handle ESCR/OTAR register according to new datasheet 11:16 < pinchartl> - soc_camera removal: more patches are coming from community 11:16 < pinchartl> review: [PATCH v1 0/5] [media] soc_camera: ov9640 switch to v4l2_async 11:16 < pinchartl> - Tested and reviewed Sakari's v4l2-fwnode rework on VIN and CEU 11:16 < pinchartl> Testing + review: [PATCH 00/21] V4L2 fwnode rework; support for default 11:16 < pinchartl> configuration 11:16 < pinchartl> - Autumn conference planning 11:16 < pinchartl> - Got a talk accepted at ELC-E 11:16 < pinchartl> Until next meeting: 11:16 < pinchartl> - Keep pushing on DU's patch upport 11:16 < pinchartl> - Finalize clock selection patch series 11:16 < pinchartl> - Finalize ESCR/OTAR handling 11:16 < pinchartl> - Finalize Ebisu HDMI and CVBS upstreaming and support Laurent for testing 11:16 < pinchartl> - I will have a few days off at the end of the month 11:16 < pinchartl> Issues and Blockers: None 11:16 < pinchartl> jmondi: any comment ? 11:17 < jmondi> yes 11:17 < jmondi> you have taken in your tree the non-DPLL channel clock selection patch 11:17 < jmondi> are we good then? 11:18 < pinchartl> I think so, yes. I'll move that to the done list 11:18 < pinchartl> (it's already there, so I'll just remove it from the "until next meeting" list) 11:18 < jmondi> you have taken the 'cosmetic' patche too, so, yeah! 11:19 < pinchartl> * Kieran 11:19 < pinchartl> Since last meeting: 11:19 < pinchartl> - Updated periupport list 11:19 < pinchartl> - RCar DU Interlaced restrictions 11:19 < pinchartl> - RCar DU 4K support 11:19 < pinchartl> - Updated GMSLv3 based on review comments 11:19 < pinchartl> - Organised ELCE attendance 11:19 < pinchartl> - VSP1 clamp for 1x1 11:19 < pinchartl> Until next meeting: 11:19 < pinchartl> - More DU/VSP Cleanup work 11:19 < pinchartl> - Retest/examine partition algorithm limitation patch 11:19 < pinchartl> - Repost writeback prototype 11:19 < pinchartl> Issues and blockers: None 11:19 < pinchartl> Notes: 11:19 < pinchartl> - Will be on vacation from September 1st to the 14th 11:19 < pinchartl> kbingham: any comment ? 11:19 < kbingham> None currently. 11:20 < pinchartl> thanks 11:20 < pinchartl> * Laurent 11:20 < pinchartl> Since last meeting: 11:20 < pinchartl> - Patch review 11:20 < pinchartl> - Reworked DU clock configuration 11:20 < pinchartl> - D3/E3 DU LVDS PLL upstreaming 11:20 < pinchartl> - Reviewed GMSL patches 11:20 < pinchartl> - Worked with Niklas face-to-face for two days 11:20 < pinchartl> Until next meeting: 11:20 < pinchartl> - Patch review 11:20 < pinchartl> - D3/E3 DU LVDS PLL upstreaming 11:20 < pinchartl> - Get GMSL patches merged 11:20 < pinchartl> Issues and blockers: None 11:20 < pinchartl> I have no comment :-) 11:20 < pinchartl> * Morimoto-san 11:20 < pinchartl> Since last meeting: 11:20 < pinchartl> - RSND TDM expand mode upport 11:20 < pinchartl> - RSND Multi DAI support 11:20 < pinchartl> Until next meeting: 11:20 < pinchartl> - Continue multi DAI support and post patches 11:20 < pinchartl> Issues and Blockers: None 11:20 < pinchartl> morimoto: any comment ? 11:20 < morimoto> yes 11:20 < morimoto> but not this 11:21 < morimoto> please contine 11:21 < pinchartl> ok :-) 11:21 < pinchartl> * Niklas 11:21 < pinchartl> Since last meeting: 11:21 < pinchartl> - Extended multiplexed stream patch-set 11:21 < pinchartl> ADV7482 virtual channel can now be selected at runtime. 11:21 < pinchartl> - Shared office with Laurent for 2 days of work and meetings. 11:21 < pinchartl> Until next meeting: 11:21 < pinchartl> - Post multiplexed stream patch-set. 11:21 < pinchartl> - Post held back VIN format patches. 11:21 < pinchartl> Issues and blockers: 11:21 < pinchartl> - kbuild boot keeps finding small issues in the multiplexed stream patch-set 11:21 < pinchartl> This has delayed posting of the series. 11:21 < pinchartl> neg: any comment ? 11:21 < neg> No comment 11:22 < pinchartl> * Simon (Kaneko-san) 11:22 < pinchartl> Since last meeting: 11:22 < pinchartl> - D3 Audio upport 11:22 < pinchartl> Until next meeting: 11:22 < pinchartl> - Testing M3-N Audio support 11:22 < pinchartl> - E3 Audio upport 11:22 < pinchartl> Issues and blockers: None 11:22 < pinchartl> horms_: any comment ? 11:23 < pinchartl> * Ulrich 11:23 < pinchartl> Since last meeting: 11:23 < pinchartl> - Sent D3 HDMI prototype with LVDS PLL support 11:23 < pinchartl> Until next meeting: None 11:23 < pinchartl> Issues and blockers: None 11:23 < pinchartl> uli___: any comment ? 11:23 < uli___> nope 11:23 < pinchartl> any comment from anyone on the status check ? 11:24 < jmondi> pinchartl: will you need a D3 for testing then? 11:24 < jmondi> or can you do it with E3? 11:24 < neg> not on the status check but I'm interested if you plan to test jmondi VIN/CSI-2 patches 11:24 < jmondi> neg: ebisu patches? 11:25 < pinchartl> jmondi: I'll test primarily on E3, but testing on D3 would be useful too 11:25 < neg> jmondi: yes 11:25 < jmondi> pinchartl: let me know how can I help 11:25 < pinchartl> thanks 11:25 < pinchartl> neg: I will test Jacopo's patches, yes 11:25 < jmondi> neg: I would like to look into the CSI-2 E3 integration, the BSP patch is quite big 11:25 < neg> pinchartl: thanks 11:25 < jmondi> s/I would like to/I would like you to/ 11:26 < jmondi> makes quite a difference :) 11:26 < neg> jmondi: :-) 11:26 < neg> It's on my list of things to review but wanted to make sure someone was testing them as I feel bad about them going upstream without being tested 11:26 < pinchartl> morimoto: you said you have a comment, the mic is yours 11:27 < jmondi> neg: thanks ;) 11:28 < morimoto> pinchartl: thanks. but I found answer from your email 11:28 < morimoto> thus, all clear for me now 11:28 < pinchartl> ok :-) 11:28 < pinchartl> anything else from anyone ? 11:28 < neg> not from me, I'm happy 11:28 < jmondi> not from here 11:28 < morimoto> nothing from me, too 11:28 < pinchartl> alright, that's it for today then 11:28 < kbingham> all good here 11:29 < pinchartl> the next meeting will be two weeks from now, on September the 6th 11:29 < pinchartl> thank you all for attending, have a nice day and evening
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-28 17:41:13 +0000
n"); dev->dev_private = (void *)dev_priv; r128_do_cleanup_cce( dev ); return DRM_ERR(EINVAL); } DRM_FIND_MAP( dev_priv->mmio, init->mmio_offset ); if(!dev_priv->mmio) { DRM_ERROR("could not find mmio region!\n"); dev->dev_private = (void *)dev_priv; r128_do_cleanup_cce( dev ); return DRM_ERR(EINVAL); } DRM_FIND_MAP( dev_priv->cce_ring, init->ring_offset ); if(!dev_priv->cce_ring) { DRM_ERROR("could not find cce ring region!\n"); dev->dev_private = (void *)dev_priv; r128_do_cleanup_cce( dev ); return DRM_ERR(EINVAL); } DRM_FIND_MAP( dev_priv->ring_rptr, init->ring_rptr_offset ); if(!dev_priv->ring_rptr) { DRM_ERROR("could not find ring read pointer!\n"); dev->dev_private = (void *)dev_priv; r128_do_cleanup_cce( dev ); return DRM_ERR(EINVAL); } DRM_FIND_MAP( dev_priv->buffers, init->buffers_offset ); if(!dev_priv->buffers) { DRM_ERROR("could not find dma buffer region!\n"); dev->dev_private = (void *)dev_priv; r128_do_cleanup_cce( dev ); return DRM_ERR(EINVAL); } if ( !dev_priv->is_pci ) { DRM_FIND_MAP( dev_priv->agp_textures, init->agp_textures_offset ); if(!dev_priv->agp_textures) { DRM_ERROR("could not find agp texture region!\n"); dev->dev_private = (void *)dev_priv; r128_do_cleanup_cce( dev ); return DRM_ERR(EINVAL); } } dev_priv->sarea_priv = (drm_r128_sarea_t *)((u8 *)dev_priv->sarea->handle + init->sarea_priv_offset); if ( !dev_priv->is_pci ) { DRM_IOREMAP( dev_priv->cce_ring ); DRM_IOREMAP( dev_priv->ring_rptr ); DRM_IOREMAP( dev_priv->buffers ); if(!dev_priv->cce_ring->handle || !dev_priv->ring_rptr->handle || !dev_priv->buffers->handle) { DRM_ERROR("Could not ioremap agp regions!\n"); dev->dev_private = (void *)dev_priv; r128_do_cleanup_cce( dev ); return DRM_ERR(ENOMEM); } } else { dev_priv->cce_ring->handle = (void *)dev_priv->cce_ring->offset; dev_priv->ring_rptr->handle = (void *)dev_priv->ring_rptr->offset; dev_priv->buffers->handle = (void *)dev_priv->buffers->offset; } #if __REALLY_HAVE_AGP if ( !dev_priv->is_pci ) dev_priv->cce_buffers_offset = dev->agp->base; else #endif dev_priv->cce_buffers_offset = dev->sg->handle; dev_priv->ring.head = ((__volatile__ u32 *) dev_priv->ring_rptr->handle); dev_priv->ring.start = (u32 *)dev_priv->cce_ring->handle; dev_priv->ring.end = ((u32 *)dev_priv->cce_ring->handle + init->ring_size / sizeof(u32)); dev_priv->ring.size = init->ring_size; dev_priv->ring.size_l2qw = DRM(order)( init->ring_size / 8 ); dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1; dev_priv->ring.high_mark = 128; dev_priv->ring.ring_rptr = dev_priv->ring_rptr; dev_priv->sarea_priv->last_frame = 0; R128_WRITE( R128_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame ); dev_priv->sarea_priv->last_dispatch = 0; R128_WRITE( R128_LAST_DISPATCH_REG, dev_priv->sarea_priv->last_dispatch ); #if __REALLY_HAVE_SG if ( dev_priv->is_pci ) { if (!DRM(ati_pcigart_init)( dev, &dev_priv->phys_pci_gart, &dev_priv->bus_pci_gart) ) { DRM_ERROR( "failed to init PCI GART!\n" ); dev->dev_private = (void *)dev_priv; r128_do_cleanup_cce( dev ); return DRM_ERR(ENOMEM); } R128_WRITE( R128_PCI_GART_PAGE, dev_priv->bus_pci_gart ); } #endif r128_cce_init_ring_buffer( dev, dev_priv ); r128_cce_load_microcode( dev_priv ); dev->dev_private = (void *)dev_priv; r128_do_engine_reset( dev ); return 0; } int r128_do_cleanup_cce( drm_device_t *dev ) { if ( dev->dev_private ) { drm_r128_private_t *dev_priv = dev->dev_private; #if __REALLY_HAVE_SG if ( !dev_priv->is_pci ) { #endif DRM_IOREMAPFREE( dev_priv->cce_ring ); DRM_IOREMAPFREE( dev_priv->ring_rptr ); DRM_IOREMAPFREE( dev_priv->buffers ); #if __REALLY_HAVE_SG } else { if (!DRM(ati_pcigart_cleanup)( dev, dev_priv->phys_pci_gart, dev_priv->bus_pci_gart )) DRM_ERROR( "failed to cleanup PCI GART!\n" ); } #endif DRM(free)( dev->dev_private, sizeof(drm_r128_private_t), DRM_MEM_DRIVER ); dev->dev_private = NULL; } return 0; } int r128_cce_init( DRM_IOCTL_ARGS ) { DRM_DEVICE; drm_r128_init_t init; DRM_DEBUG( "\n" ); DRM_COPY_FROM_USER_IOCTL( init, (drm_r128_init_t *)data, sizeof(init) ); switch ( init.func ) { case R128_INIT_CCE: return r128_do_init_cce( dev, &init ); case R128_CLEANUP_CCE: return r128_do_cleanup_cce( dev ); } return DRM_ERR(EINVAL); } int r128_cce_start( DRM_IOCTL_ARGS ) { DRM_DEVICE; drm_r128_private_t *dev_priv = dev->dev_private; DRM_DEBUG( "\n" ); LOCK_TEST_WITH_RETURN( dev ); if ( dev_priv->cce_running || dev_priv->cce_mode == R128_PM4_NONPM4 ) { DRM_DEBUG( "%s while CCE running\n", __FUNCTION__ ); return 0; } r128_do_cce_start( dev_priv ); return 0; } /* Stop the CCE. The engine must have been idled before calling this * routine. */ int r128_cce_stop( DRM_IOCTL_ARGS ) { DRM_DEVICE; drm_r128_private_t *dev_priv = dev->dev_private; drm_r128_cce_stop_t stop; int ret; DRM_DEBUG( "\n" ); LOCK_TEST_WITH_RETURN( dev ); DRM_COPY_FROM_USER_IOCTL(stop, (drm_r128_cce_stop_t *)data, sizeof(stop) ); /* Flush any pending CCE commands. This ensures any outstanding * commands are exectuted by the engine before we turn it off. */ if ( stop.flush ) { r128_do_cce_flush( dev_priv ); } /* If we fail to make the engine go idle, we return an error * code so that the DRM ioctl wrapper can try again. */ if ( stop.idle ) { ret = r128_do_cce_idle( dev_priv ); if ( ret ) return ret; } /* Finally, we can turn off the CCE. If the engine isn't idle, * we will get some dropped triangles as they won't be fully * rendered before the CCE is shut down. */ r128_do_cce_stop( dev_priv ); /* Reset the engine */ r128_do_engine_reset( dev ); return 0; } /* Just reset the CCE ring. Called as part of an X Server engine reset. */ int r128_cce_reset( DRM_IOCTL_ARGS ) { DRM_DEVICE; drm_r128_private_t *dev_priv = dev->dev_private; DRM_DEBUG( "\n" ); LOCK_TEST_WITH_RETURN( dev ); if ( !dev_priv ) { DRM_DEBUG( "%s called before init done\n", __FUNCTION__ ); return DRM_ERR(EINVAL); } r128_do_cce_reset( dev_priv ); /* The CCE is no longer running after an engine reset */ dev_priv->cce_running = 0; return 0; } int r128_cce_idle( DRM_IOCTL_ARGS ) { DRM_DEVICE; drm_r128_private_t *dev_priv = dev->dev_private; DRM_DEBUG( "\n" ); LOCK_TEST_WITH_RETURN( dev ); if ( dev_priv->cce_running ) { r128_do_cce_flush( dev_priv ); } return r128_do_cce_idle( dev_priv ); } int r128_engine_reset( DRM_IOCTL_ARGS ) { DRM_DEVICE; DRM_DEBUG( "\n" ); LOCK_TEST_WITH_RETURN( dev ); return r128_do_engine_reset( dev ); } /* ================================================================ * Fullscreen mode */ static int r128_do_init_pageflip( drm_device_t *dev ) { drm_r128_private_t *dev_priv = dev->dev_private; DRM_DEBUG( "\n" ); dev_priv->crtc_offset = R128_READ( R128_CRTC_OFFSET ); dev_priv->crtc_offset_cntl = R128_READ( R128_CRTC_OFFSET_CNTL ); R128_WRITE( R128_CRTC_OFFSET, dev_priv->front_offset ); R128_WRITE( R128_CRTC_OFFSET_CNTL, dev_priv->crtc_offset_cntl | R128_CRTC_OFFSET_FLIP_CNTL ); dev_priv->page_flipping = 1; dev_priv->current_page = 0; return 0; } int r128_do_cleanup_pageflip( drm_device_t *dev ) { drm_r128_private_t *dev_priv = dev->dev_private; DRM_DEBUG( "\n" ); R128_WRITE( R128_CRTC_OFFSET, dev_priv->crtc_offset ); R128_WRITE( R128_CRTC_OFFSET_CNTL, dev_priv->crtc_offset_cntl ); dev_priv->page_flipping = 0; dev_priv->current_page = 0; return 0; } int r128_fullscreen( DRM_IOCTL_ARGS ) { DRM_DEVICE; drm_r128_fullscreen_t fs; LOCK_TEST_WITH_RETURN( dev ); DRM_COPY_FROM_USER_IOCTL( fs, (drm_r128_fullscreen_t *)data, sizeof(fs) ); switch ( fs.func ) { case R128_INIT_FULLSCREEN: return r128_do_init_pageflip( dev ); case R128_CLEANUP_FULLSCREEN: return r128_do_cleanup_pageflip( dev ); } return DRM_ERR(EINVAL); } /* ================================================================ * Freelist management */ #define R128_BUFFER_USED 0xffffffff #define R128_BUFFER_FREE 0 #if 0 static int r128_freelist_init( drm_device_t *dev ) { drm_device_dma_t *dma = dev->dma; drm_r128_private_t *dev_priv = dev->dev_private; drm_buf_t *buf; drm_r128_buf_priv_t *buf_priv; drm_r128_freelist_t *entry; int i; dev_priv->head = DRM(alloc)( sizeof(drm_r128_freelist_t), DRM_MEM_DRIVER ); if ( dev_priv->head == NULL ) return DRM_ERR(ENOMEM); memset( dev_priv->head, 0, sizeof(drm_r128_freelist_t) ); dev_priv->head->age = R128_BUFFER_USED; for ( i = 0 ; i < dma->buf_count ; i++ ) { buf = dma->buflist[i]; buf_priv = buf->dev_private; entry = DRM(alloc)( sizeof(drm_r128_freelist_t), DRM_MEM_DRIVER ); if ( !entry ) return DRM_ERR(ENOMEM); entry->age = R128_BUFFER_FREE; entry->buf = buf; entry->prev = dev_priv->head; entry->next = dev_priv->head->next; if ( !entry->next ) dev_priv->tail = entry; buf_priv->discard = 0; buf_priv->dispatched = 0; buf_priv->list_entry = entry; dev_priv->head->next = entry; if ( dev_priv->head->next ) dev_priv->head->next->prev = entry; } return 0; } #endif drm_buf_t *r128_freelist_get( drm_device_t *dev ) { drm_device_dma_t *dma = dev->dma; drm_r128_private_t *dev_priv = dev->dev_private; drm_r128_buf_priv_t *buf_priv; drm_buf_t *buf; int i, t; /* FIXME: Optimize -- use freelist code */ for ( i = 0 ; i < dma->buf_count ; i++ ) { buf = dma->buflist[i]; buf_priv = buf->dev_private; if ( buf->pid == 0 ) return buf; } for ( t = 0 ; t < dev_priv->usec_timeout ; t++ ) { u32 done_age = R128_READ( R128_LAST_DISPATCH_REG ); for ( i = 0 ; i < dma->buf_count ; i++ ) { buf = dma->buflist[i]; buf_priv = buf->dev_private; if ( buf->pending && buf_priv->age <= done_age ) { /* The buffer has been processed, so it * can now be used. */ buf->pending = 0; return buf; } } DRM_UDELAY( 1 ); } DRM_ERROR( "returning NULL!\n" ); return NULL; } void r128_freelist_reset( drm_device_t *dev ) { drm_device_dma_t *dma = dev->dma; int i; for ( i = 0 ; i < dma->buf_count ; i++ ) { drm_buf_t *buf = dma->buflist[i]; drm_r128_buf_priv_t *buf_priv = buf->dev_private; buf_priv->age = 0; } } /* ================================================================ * CCE command submission */ int r128_wait_ring( drm_r128_private_t *dev_priv, int n ) { drm_r128_ring_buffer_t *ring = &dev_priv->ring; int i; for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { r128_update_ring_snapshot( ring ); if ( ring->space >= n ) return 0; DRM_UDELAY( 1 ); } /* FIXME: This is being ignored... */ DRM_ERROR( "failed!\n" ); return DRM_ERR(EBUSY); } static int r128_cce_get_buffers( drm_device_t *dev, drm_dma_t *d ) { int i; drm_buf_t *buf; for ( i = d->granted_count ; i < d->request_count ; i++ ) { buf = r128_freelist_get( dev ); if ( !buf ) return DRM_ERR(EAGAIN); buf->pid = DRM_CURRENTPID; if ( DRM_COPY_TO_USER( &d->request_indices[i], &buf->idx, sizeof(buf->idx) ) ) return DRM_ERR(EFAULT); if ( DRM_COPY_TO_USER( &d->request_sizes[i], &buf->total, sizeof(buf->total) ) ) return DRM_ERR(EFAULT); d->granted_count++; } return 0; } int r128_cce_buffers( DRM_IOCTL_ARGS ) { DRM_DEVICE; drm_device_dma_t *dma = dev->dma; int ret = 0; drm_dma_t d; LOCK_TEST_WITH_RETURN( dev ); DRM_COPY_FROM_USER_IOCTL( d, (drm_dma_t *) data, sizeof(d) ); /* Please don't send us buffers. */ if ( d.send_count != 0 ) { DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n", DRM_CURRENTPID, d.send_count ); return DRM_ERR(EINVAL); } /* We'll send you buffers. */ if ( d.request_count < 0 || d.request_count > dma->buf_count ) { DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n", DRM_CURRENTPID, d.request_count, dma->buf_count ); return DRM_ERR(EINVAL); } d.granted_count = 0; if ( d.request_count ) { ret = r128_cce_get_buffers( dev, &d ); } DRM_COPY_TO_USER_IOCTL((drm_dma_t *) data, d, sizeof(d) ); return ret; }