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title: SDHI; upport BSP patches
team: IO
key: fe6714da-a9b4-11eb-a028-6bbd20fa8e8a
status: Active
assignee: Wolfram
bsp41x:
- 0237478dc67b71ff92082e06323c015631098b71 # arm64: dts: r8a77980-v3hsk: Enable onboard eMMC
- c2ca1ccb83afd7c790ae361c720d257e050483f2 # mmc: core: Issue power off notification in mmc_remove()
- 5d60e36aaa96fa39d1a524cc4ff373c0f36616e0 # mmc: renesas_sdhi: reset calibration register
- 73405fef502d43737be9a50d29935bee133fe7ab # mmc: renesas_sdhi: Add internal DMA transfer end
- 20e5623df1aaa74301675122b910f063cdcabe7e # mmc: tmio: Add internal DMA transfer end
bsp51x:
- 1f8eaa32650a2f67cc318f39c603f2c8282831a4 # arm64: dts: r8a77980-v3hsk: Enable onboard eMMC
- ef716ad2e21ec228a138e1d22cc1c33e669e492b # arm64: dts: renesas: r8a77980-v3hsk: Disable MMC
- e533a0ea555e061170b4102d9085c70546fe4768 # mmc: core: Issue power off notification in mmc_remove()
- 15d7abbfc3f0dae379821824135d94a4f865a449 # mmc: renesas_sdhi: reset calibration register
- 53c3958c01961421cd2b70c3dfebc9f391e00192 # mmc: renesas_sdhi: Add internal DMA transfer end
- e54e9682fbc229e7a168d63b2e49bc174353caed # mmc: tmio: Add internal DMA transfer end
- 2d111ff70e13073395f33e989ca2ff63b4fb4d2e # mmc: renesas_sdhi: scc_ctl is always set in after R-Car Gen3
- ef6598cafe54825b537f47df7846dbcacbc73e88 # mmc: renesas_sdhi: Disable HS400 for r8a77995
- e741f08198c2973650cb8965a17337a126ea049e # arm64: dts: renesas: r8a77950-ulcb: disable eMMC
upstream:
- torvalds: 6af8dd53c36f3e400b60269d3b55bdcc0d0574f7 # mmc: renesas_sdhi: R-Car D3 also has no HS400
- torvalds: fc1fdbd94cabab0f647c80fbd5c41029f84735b4 # mmc: renesas_sdhi: R-Car V3M also has no HS400
- torvalds: f504dee2c63b93fddb2dc42f37971e9f36c021e7 # mmc: renesas_sdhi: R-Car V3H ES2.0 gained HS400 support
- next: f33261c369ba5b7e0de89a64146aaf6e62b1031f # mmc: renesas_sdhi: remove accessor function for internal_dmac
- next: 8da04ec403d22ab9e94fed1e76566cde4b2d311a # mmc: renesas_sdhi: improve naming of DMA struct
- next: dc0efb624b91fb70c4c500feb013d30d5f5060f2 # mmc: tmio: add callback for dma irq
- next: 8d95c9631faf79d4536fd1872a1da88781b4dc25 # mmc: renesas_sdhi: add quirk for broken register layout
- next: 8d901e2ba5667ea48b99b27a8d9c7faec37e6bb6 # mmc: renesas_sdhi: take DMA end interrupts into account
- next: dfcdf4a6defa1ef8e766158858a3e3e632c193eb # [PATCH v2 1/4] mmc: renesas_sdhi: alway populate SCC pointer
- next: 0ce6ff700b6706c6fe1d10f2b96ab1d8467b8077 # [PATCH v2 2/4] mmc: renesas_sdhi: better reset from HS400 mode
- next: 07904c0f974aa9931eaa344a36f6f667619bda2e # [PATCH v2 3/4] mmc: renesas_sdhi: add helper to access quirks
- next: f12925583f75053965af37cc0eb916653dd13be9 # [PATCH v2 4/4] mmc: renesas_sdhi: use new convenience macro from MMC core
comments:
- 0237478dc67b71ff92082e06323c015631098b71, 1f8eaa32650a2f67cc318f39c603f2c8282831a4, ef716ad2e21ec228a138e1d22cc1c33e669e492b
- do we have V3H hardware in Magnus lab?
- Magnus so far has only a Condor board, but not v3hsk
- BSP5.1x patch reverts because voltage specification of MMC is unclear
- abandoned unless we get HW ourselves
- done
- c2ca1ccb83afd7c790ae361c720d257e050483f2, e533a0ea555e061170b4102d9085c70546fe4768
- https://patchwork.kernel.org/project/linux-mmc/patch/1605005330-7178-1-git-send-email-yoshihiro.shimoda.uh@renesas.com/
- 5d60e36aaa96fa39d1a524cc4ff373c0f36616e0, 15d7abbfc3f0dae379821824135d94a4f865a449
- before calling 'renesas_sdhi_adjust_hs400_mode_disable()', change the if to 'if (gen3)'?
- refactored and sent v1
- sent v2
- 73405fef502d43737be9a50d29935bee133fe7ab, 53c3958c01961421cd2b70c3dfebc9f391e00192
- Only for H3/M3-W ES1.0, but why does mainline work?
- Shimoda-san said that old SoCs had issues with internal DMA end irq not at the same time as transfer end irq
- current HW does not have these issues but to be future-proof, we still want to handle them individually
- heavily refactored and RFC sent
- tested and merged
- done
- 20e5623df1aaa74301675122b910f063cdcabe7e, e54e9682fbc229e7a168d63b2e49bc174353caed
- Why does mainline work without it?
- Shimoda-san said that old SoCs had issues with internal DMA end irq not at the same time as transfer end irq
- current HW does not have these issues but to be future-proof, we still want to handle them individually
- heavily refactored and RFC sent
- tested and merged
- done
- 2d111ff70e13073395f33e989ca2ff63b4fb4d2e
- why is it needed?
- to allow resetting the SCC in any case
- refactored and sent with v2 of reset-calibration-register fix
- ef6598cafe54825b537f47df7846dbcacbc73e88
- can't find it in the docs that HS400 is not supported. But D3 has indeed no strobe pin which is needed
- v1 sent
- merged
- done
- e741f08198c2973650cb8965a17337a126ea049e
- commit message mentions silicon bug? Which one?
- commit is from 2017, though, and many improvements have been implemented for SDHI
- we are also not aware on SDHI issues on Salvator-X with H3 ES1.x
- abandoned
- done
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