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+title: "BSP 4.1.x upport: rcar-du: Conform to registers and operations documentation"
+team: MM
+key: 0871a69d-8cd4-4dae-af53-f4742586acaf
+status: New
+
+bsp41x:
+ - f9724fa36a9dddefd2f0ae9a4034cc2b9fe9f691 # drm: rcar-du: Add register access check
+ - cf6e2f83129837fd7501cef41c32a2864bf3f6fc # drm: rcar-du: Fix DPLL workaround for H3 ES1.x
+ - cf64351173c0fb4d44367f6e20880bb5ef5faf6f # drm: rcar-du: Fix LVDS stop sequence
+ - f55c6ceca6d9066cbb9d9dd9f2bda5ba19f8e60a # drm: rcar-du: Add CPG reset and release
+ - d2db7ee7b3a5141d161f614f748fdbce2ea11469 # rcar-fcp: Add FCPVD reset sequence for VSPD
+ - 4e290a3f392fe06b73d137054bda4ce4e4b237ea # vsp1: Add display interrupt wait after setting STRCMD bit
+
+comments:
+ - These commits bring the FCP, VSP, DU and LVDS drivers in conformance with
+ the registers and operations documentation. Some changes are likely not
+ required (in particular changes that skip writes to reserved bits of
+ existing registers), but getting an official acknowledgement that writing
+ reserved bits is safe is likely not possible. From a certification point of
+ view, Renesas likely requires these issues to be fixed.
+
+ - The changes affect readability, especially in the rcar-du driver. An
+ alternative approach to sprinkling lots of manual checks for SoC revisions
+ should be researched.