diff options
Diffstat (limited to 'projects/linux/core')
| -rw-r--r-- | projects/linux/core/bsp41x_clk_renesas.yaml | 24 |
1 files changed, 11 insertions, 13 deletions
diff --git a/projects/linux/core/bsp41x_clk_renesas.yaml b/projects/linux/core/bsp41x_clk_renesas.yaml index 176bc13..d6bb883 100644 --- a/projects/linux/core/bsp41x_clk_renesas.yaml +++ b/projects/linux/core/bsp41x_clk_renesas.yaml @@ -1,4 +1,4 @@ -title: "BSP 4.1.x upport clk: renesas" +title: "BSP 4.1.x, 5.1.x upport clk: renesas" team: Core key: 1641c746-661f-11eb-94be-d3d0dd2f1615 status: New @@ -9,19 +9,11 @@ bsp41x: - 630d6bce408c5955192de1053053572ccc66103c # clk: r8a779x: add IMP clock - de03f48327ebdb3c0bb30b4866e27ff158655cc6 # clk: r8a779x: add mlp clock - 8dc96a9c37919b41fbf48747a00cf003f0d00091 # clk: renesas: r8a7795: Add ADG clock - - 545a5ee67acb14b335f667068569edf568701f14 # clk: renesas: r8a7795: Add AVS clock - - b1dbacf27857e697fc45a32853a0731150151b6c # clk: renesas: r8a7795: Add iVDP1C clocks to ES1.x - - 5423c26953bbe5d689905fa75ab16e969eb73ba0 # clk: renesas: r8a7795: Add VCP4 clock - 83d2393cf2eb84ffb325984c0c74637f8e99966e # clk: renesas: r8a7795: Add ZG clock - 97a43e88563ea2b0ff55700c8c77b53d278807f4 # clk: renesas: r8a77965: Add ADG clock - - c597724fbac9091fc4cd6f5c3862992de9b033ff # clk: renesas: r8a77965: Add VCP4 clocks - f3302aefee22905ae55d5f0d6d72eebceab89b06 # clk: renesas: r8a77965: Add ZG clock - c2bb14d97eb238ae80fb704a23430a9c41a6ea12 # clk: renesas: r8a7796: Add ADG clock - - c86c8885c7071c01489567ecf155501d2a00042c # clk: renesas: r8a7796: Add AVS clock - - 64558129af10ee7d149538fc7ecffb4029800d0e # clk: renesas: r8a7796: Add iVDP1C clock - - c19b595e501379b8465559afe1f974c3ec8c64d6 # clk: renesas: r8a7796: Add VCP4 clocks - d6ec7401d973ca94d05ada3f536ea90a51ab49c7 # clk: renesas: r8a7796: Add ZG clock - - b95564845d3a41210863fc3528290cc2929e0062 # clk: renesas: r8a7796: Remove iVDP1C and FCPCI0 clocks on ES3.0 - cba445d7f22ba68ca439b51fb0dddc5c7374e73a # clk: renesas: r8a77970: cpg-mssr: Add IMP clocks - 4eff99dc18d7a4ee9897e20e56c6cc4848f8d14f # clk: renesas: r8a77970: cpg-mssr: Add IMR clocks - 40d7f7dbacbe3b2c0dee7dde7e6b8466211ac805 # clk: renesas: r8a77970: cpg-mssr: Add ISP clock @@ -35,7 +27,6 @@ bsp41x: - 9dd769eaf233351b5b9084e3376d13682d454954 # clk: renesas: r8a779a0: Extend number of supported module clocks - 6f778e4eee9560601931843f740dd43ab5f9c070 # clk: renesas: r8a77990: Add ADG clocks - 7072cab285d6beb707f76af0cbeb371aa246f23f # clk: renesas: r8a77990: Add FDP1 clock - - 2565115b47318a04f045a8569368aad74a9fa31e # clk: renesas: r8a77990: Add VCP4 clocks - ae24a9705d50622bde086f0ddfcb3130b0742078 # clk: renesas: r8a77990: Add ZG clock - cc77aca0e88791b0f679451cf67572d3d2df49fc # clk: renesas: r8a779a0: Add FBA clocks - 354dc784c78184ef4b5e2fbcd0408da331af4a4f # clk: renesas: r8a779a0: Add FBC clock @@ -48,11 +39,18 @@ bsp51x: - 5582d6cdb469f1b4bbab91166e0bff096ee4f610 # clk: renesas: rcar-gen3: Add support ZG clock divider for R8A77990 - ce47cc590b66d6aa4e2333daff4eb680a594be31 # clk: renesas: rcar-gen3: Fix revision of R8A7796 for applying SD_SKIP_FIRST - 282015509bbfc49836a2af6c3ba07242c6684310 # clk: renesas: r8a7795: Add ADG clock - - f1cd1c62af62c115d3de129c6012f34152ded002 # clk: renesas: r8a7795: Add iVDP1C clocks to ES1.x - - 369b8ac0bfe67c64eb5a5a2f1ce10304cf95da70 # clk: renesas: r8a7795: Add VCP4 clock - - 16e4543e163e2d127a98e542950de6c3ed29acc6 # clk: renesas: r8a7796: Add iVDP1C clock - 10ebbc065ddd9749f591017a3250c203819e6fb1 # clk: renesas: r8a77990: Add FDP1 clock - a297ad0ce10681616317e7e20933cecdd46b21de # clk: renesas: r8a779a0: Extend number of supported module clocks + - 3cd08492c5fd8449633bfe753bc8fa8c97696190 # clk: renesas: r8a779{70, 80}: Add IMR clocks + - 4b89a300f177d822dcd90733b105cecdb57fc601 # clk: renesas: r8a77990: Add IMR clock + - c1bae0eb563c53c6391dd0cc0b34380f38ea123a # clk: renesas: r8a77980: Add VIN clocks + - 532e2fea3e521ac26c24e792395d2aa59fb5fe7a # clk: renesas: r8a77980: Add VIP clocks + - 0fdb2882e6a74ea39ba775c84d65ad417c9729bc # clk: renesas: r8a77995: Add ADG clock for R8A77995 + - c9cd487c7891aed7767cc417fa8d56ef974ddb1a # clk: renesas: r8a779{5, 6, 70, 80}: add IMP clock + - 365d7c007742144187be3fcfa1124574913ba103 # clk: renesas: r8a779{70, 80}: Add ISP clock + - a27bdfbe3804f3b8b78894cf78766b3968ca0237 # clk: renesas: r8a77{95, 96, 965, 990}: Add ZG clock + - e7bcd75b2ab34b3535d568eb5f8a6042413a0677 # clk: renesas: r8a77{96, 965, 990}: Add ADG clock + - 9dfba43fd5dc1da1bfec66dadfb10c14cf4a72f9 # clk: renesas: rcar-gen3: Use max_rate as maximum rate for normal clock instead max_freq upstream: - torvalds: 2bd9feed23166f5ab67dec2ca02bd3f74c77b0ba # clk: renesas: r8a779[56]x: Add MLP clocks |