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author | Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> | 2019-12-23 14:27:52 +0900 |
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committer | Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> | 2019-12-23 14:27:52 +0900 |
commit | dc71f3518c95f8d9d306e8a4e53bc9bd2e9928e3 (patch) | |
tree | 54552f6ba6cec40e16cef5c22043d9f510087e00 /wiki/Chat_log/20180920-core-chatlog | |
parent | bb506a3f4c5441ecb212874077ad8b1bf335c936 (diff) | |
parent | 05040a728026b28ce7c6183d2adfa80218b306cb (diff) |
Merge remote-tracking branch 'gitlab/wiki' into HEAD
Diffstat (limited to 'wiki/Chat_log/20180920-core-chatlog')
-rw-r--r-- | wiki/Chat_log/20180920-core-chatlog | 180 |
1 files changed, 180 insertions, 0 deletions
diff --git a/wiki/Chat_log/20180920-core-chatlog b/wiki/Chat_log/20180920-core-chatlog new file mode 100644 index 0000000..8b7298e --- /dev/null +++ b/wiki/Chat_log/20180920-core-chatlog @@ -0,0 +1,180 @@ +Core-chat-meeting-2018-09-20 + +09:24 < Marex> wsa: besides the news that I finally managed to extract all the relevant info out of Lorenzo ... +09:24 < Marex> wsa: yet still, there's one last bit which he didn't answer fully and I have to read the PCIe spec for that +09:24 < Marex> wsa: that is, can a register other than PMCSR put a card into D3hot and thus link into L1 ? +09:24 < geertu> Marex: PCIe is core? +09:24 < Marex> wsa: and if so, is that PCIe compliant configuration +09:25 < Marex> geertu: PCIe is a bus :-) +09:25 < geertu> wsa: I'll wait 5 more minutes? +09:26 < wsa> Marex: I see. Thanks for keeping at it and diving into it. +09:26 < wsa> geertu: ok +09:26 < Marex> thing is, if PMCSR is the only register which can put a card into D3hot state, we can intercept such accesses in the PCIe code +09:26 < Marex> if not, we're doomed and need the ATF fixup +09:26 < wsa> understood +09:26 < Marex> I am afraid it's the later ... +09:26 < Marex> I mean, I can cook such a setup in an FPGA +09:27 < Marex> the question really is, does PCIe spec permit this +09:27 < Marex> and that neither me nor Lorenzo know ... and thus I need to read the spec again +09:27 < wsa> and what does hardware in reality really do +09:28 < Marex> wsa: what do you mean ? you can use setpci to write any register you want pretty much :) +09:28 < Marex> wsa: I don't know if such a card with custom register to enter D3hot exists, but I know it can be created with relative ease ... +09:28 < wsa> i mean specs are one thing, reality is another +09:28 < wsa> not more than that... +09:29 < Marex> wsa: there's too much hardware to know whether PMCSR is the only reg ever used to enter D3hot +09:30 < Marex> wsa: but if the spec says it is, then the certification checks it and we only support certified PCIe hardware +09:31 < wsa> we can do that +09:31 < Marex> wsa: ... and we can ignore hardware which doesn't use PMCSR to enter the D3hot as non-compliant +09:32 < damm> maybe non-compliant + non-compliant = success? +09:32 < damm> its like xor +09:32 < wsa> we only support non-compliant HW :D +09:32 < damm> =) +09:32 < geertu> damm: nah, it's like a CMOS gate with a floating input ;-) +09:33 < Marex> damm: isn't that more multiplicative operation ? +09:33 < wsa> Well, our HW semms broken, so if this is the best we can do, then OK +09:34 < wsa> but once we got more information about what to do (ATF or not), we should report again to the HW team +09:34 < damm> geertu: reminds me of sh7751 PCI power management +09:34 < damm> Marex: you are right +09:34 < wsa> ok, so now we are 5 minutes over time again :D +09:35 < geertu> So let's start? +09:35 < geertu> Welcome to today's Core Group Meeting! +09:35 < geertu> Agenda: +09:35 < geertu> 1. Status Updates +09:35 < geertu> 2. Discussion Topics +09:35 < geertu> Topic 1. Status updates +09:36 < geertu> A) What have we done since last time: +09:36 < geertu> Jacopo reviewed the RZ/N1 pinctrl driver, and discussed it with Phil +09:36 < geertu> Edworthy. +09:36 < geertu> Marek fixed various issues in U-Boot (DT memory node parsing, timer +09:36 < geertu> frequency, reset), resubmitted the R-Car Gen2 PMIC quirk handling patch, +09:36 < geertu> and continued working on fixing the PCIe L1 issue (ATF, JTAG, discussion +09:36 < geertu> with Lorenzo). +09:36 < geertu> Morimoto-san says BSP 3.7.0 will be handled using periupport, and has +09:36 < geertu> shipped an Ebisu-4D to Magnus. +09:36 < geertu> Morimoto-san and Shimoda-san provided BSP git commit description feedback +09:36 < geertu> to the BSP team, to improve descriptions. +09:36 < geertu> Shimoda-san says Renesas Vietnam started testing LTSI v4.14-rc1, and +09:36 < geertu> discussed power management support in the IPMMU driver with Magnus. +09:36 < geertu> Simon posted a backport of I2C fixes for v4.14-ltsi-rc2, and prepared a +09:36 < geertu> backport of an MSIOF fix. +09:36 < geertu> Wolfram worked on dma_params (subsystem, SYS-DMAC, SDHI-DMAC). +09:36 < geertu> Geert revisited VFIO and QEMU platform device pass-through patches, +09:36 < geertu> reviewed lots of patches. He also created two branches to assist GregKH +09:36 < geertu> with releasing v4.14-ltsi-rc1, tested v4.14.70-ltsi, and reviewed rcar-i2c +09:36 < geertu> fixes submitted for rc2. +09:38 < geertu> B) What we plan to do till next time: +09:38 < geertu> Magnus will prepare a plan for IPMMU PM development. +09:38 < geertu> Marek will continue workijg on the PCIe L1 issue. +09:38 < geertu> Niklas will aggregate different SDHI clocks settings user in aid of trying +09:38 < geertu> to solve the different setting between ES versions of H3. +09:38 < geertu> Shimoda-san says Renesas Vietnam will continue testing LTSI v4.14-rc1 until +09:38 < geertu> Sep 25th. He will submit v2 of the usb2.0 host/peripheral properties +09:38 < geertu> update. +09:38 < geertu> Geert will continue QEMU GPIO virtualization, handle SYSC and PFC errata, +09:38 < geertu> and review fixes to be submitted for v4.14-ltsi-rc2. +09:39 < geertu> C) Problems we have currently: +09:39 < geertu> Marek has problems with "the" PCI controller ;-) +09:39 < geertu> Geert reviewed too many(?) patches. +09:39 < geertu> --- +09:40 < geertu> Anything I missed? +09:41 < Marex> geertu: I got U-Boot test suite running on Gen2 Porter :) +09:41 < horms> I think it might be worth mentioning that there seem to be a lot of patches to review over the past few months. Not that this is a problem. But it does take some time fore review etc... +09:42 < horms> s/fore/for/ +09:42 < geertu> It's the penalty to pay for the RZ/G marketing decisions... +09:43 < geertu> Topic 2. Discussion Topics +09:43 < horms> Yes, a lot of them relate to that work +09:43 < geertu> We already had the PCIe stuff in the intermeeting period +09:44 < wsa> I just hope that does get recognized inside Renesas when it comes to "why do we need an upstream team"... +09:44 < damm> i'd like to report back about the process review +09:45 < damm> whenever is a good time +09:45 < geertu> wsa: AFAIK their original plan was to just use the existing compatible properties, and be done with it. +09:45 < geertu> damm: Yes please +09:46 < damm> so i sat down with the Rennesas guys and went over the chat log from earlier when pinchartl outlined stuff +09:46 < damm> and basically there are no objections at all +09:46 < damm> we had to zoom out quite a few times +09:47 < damm> the focus was tool vs process +09:47 < damm> to clarify focus and expected order from my side +09:48 < damm> and it became evident that some expectation existed from Renesas side to use some tool for the upcoming 6 month period +09:48 < pinchartl> did they define "some tool" ? +09:48 < damm> well, i basically gave some home work to make a 6 month plan +09:49 < damm> it should include teh following: +09:49 < damm> - when to discuss process with laurent +09:49 < damm> - which tool to use when +09:49 < damm> - which input format when (bsp format changes) +09:50 < damm> (also whenever new bsp releases are made those should be in there too) +09:50 < damm> this to make it clear which tool to use when and what the expected output of the process discussion is +09:51 < damm> i hope that morimoto-san can bring the plan to ELCE and discuss with pinchartl +09:51 < damm> for further feedback +09:51 < damm> and potential coutner prooposal +09:51 < pinchartl> I hope that the plan will start with a process discussion :-) +09:51 < damm> i asked to focus on this until next chat meeting +09:52 < damm> and lets see where that takes us +09:52 < damm> pinchartl: me too! =) +09:52 < damm> that's it from my side +09:54 * Marex afk , doctors' appointment , bye +09:54 -!- neg [~neg@unaffiliated/neg] has quit [Read error: Connection reset by peer] +09:54 < horms> do I understand correctly that there will be a follow-up discussion with Renesas before the next chat meeting? +09:54 < damm> correct +09:54 -!- neg [~neg@unaffiliated/neg] has joined #periperi +09:55 < wsa> so, Renesas wants to use "the tool" for Q4Q1 already? And we discuss about it at ELCE end of October? +09:55 < wsa> or did i get something wrong? +09:55 < horms> Is there also a dialog in progress regarding the value/role of the upstream team? +09:57 < damm> wsa: i want the plan to point out clarly which tool to use when +09:57 < damm> wsa: if you have any preference feel free to share that +09:57 < wsa> horms: I wonder about that, too. Especially since there I know of some good example recently where our good connections with upstream saved us some work (SCCB rework, irqless I2C transactions, DMA 32bit limitation) +09:58 < damm> horms: not yet +09:58 < pinchartl> damm: that's a very vague question... +09:58 < damm> horms: at this point it is just focusing on the interface/format for the up port work +09:58 < damm> so about "the tool" +09:59 < horms> damm: feel free to drag me into any conversation if you think I can be of assistance +09:59 < horms> But lets get back to the process/tool discussion - sorry for the noise +09:59 < damm> horms: thanks +09:59 < damm> np +09:59 < damm> so the way the tool was developed and the expected process order from my (and pinchartl) seems to mismatchhhh +10:00 < damm> so rolling in the tool urgently w/o a clear process seems rusing in the potentially wrong direction +10:00 < wsa> damm: I am fine with your plan to point that out clearly. I just was confused about the dates +10:00 < damm> ok +10:00 < pinchartl> from my side the problem is clear. I can't comment on tooling if I'm not told what the process is, in *details* +10:00 < damm> i want to clarify the expectation from each side +10:01 < pinchartl> (to use an analogy everybody here should be able to understand, I can't review an implementation if I'm not told what API it implements) +10:01 < damm> maybe we will see that we have different expectations =) +10:01 < damm> pinchartl: i'm with you +10:02 < damm> i want to help clarify expectation from renesas side first +10:02 < damm> then let you guys hash it out during ELCE +10:02 < wsa> damm: same as horms, I'd like to be assistance for that discussion if you think I could be useful. (and now back to "the tool") +10:02 < damm> while i am in hiding some place else +10:03 < damm> wsa: so you should join pinchartl for the process discussion topic +10:04 < damm> so i expect you guys to take the plan from renesas side and request minor updates or ask for major change with your own proposal if needed +10:04 < damm> this to make sure we have a healthy discussion +10:04 < damm> just accepting won't help anyone +10:04 < wsa> damm: you mean at ELCE, sure thing +10:05 < damm> (i don't expect that from pinchartl) =) +10:05 < damm> wsa: yep +10:05 < damm> is my expecation about this far ooff? +10:06 < damm> (thats how it gets when you live in your PJs most of the time) +10:06 < pinchartl> damm: if you expect me to make a major counter proposal, I may be able to live up to your expectations :-) +10:06 < damm> haha +10:06 < damm> i hope to give you some clear expectation to work with +10:07 < damm> perhaps you can adjust timing of tool change etc +10:07 < damm> depending on how much time you expect is needed for the process discussion +10:08 < damm> so let me report back next chat meeting about the plan so far +10:09 < pinchartl> sounds good to me +10:09 < damm> any questions that i ducked? +10:09 < damm> or new ones? +10:10 < damm> pinchartl: do you have any expected frequency of broken out process discussions? +10:10 < damm> for next 6 months +10:11 < pinchartl> damm: not really. ideally we'll have one good discussion, decide on a plan, and move forward +10:12 < damm> then do your best at ELCE timing and we can take minor increments from there? +10:12 < damm> shall we do one more process discussion meeting via HO or similar before ELCE? +10:13 < damm> maybe we can ponder a bit for now and book something next chat meeting? +10:13 < pinchartl> I think you know my position. if there's more information to share, we can have another discussion, otherwise I don't think it would be very useful +10:14 < damm> we will have some info in form of a plan next meeting +10:15 < damm> my point is that when we discussed last time we only got to touch part of the subject +10:15 < damm> but anyway +10:15 < damm> no questions? +10:16 < pinchartl> not from me +10:16 < damm> ok shall we close the topic? +10:16 < geertu> ok for now +10:17 < damm> thanks +10:18 < geertu> Anything else to discuss? +10:19 < geertu> Thanks for joining, and have a nice continued day! |