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authorGeert Uytterhoeven <geert+renesas@glider.be>2021-05-03 09:47:57 +0200
committerGeert Uytterhoeven <geert+renesas@glider.be>2021-05-03 14:42:18 +0200
commit4dce764e410b5906556434f85af96efa60e20da3 (patch)
treed8b25b27aff9dcabf3d517a930d48810038c4ddd /projects/linux
parent464afdbaa6204efb25ebcbaf89f3bc1454ee2b0c (diff)
projects: linux: core: Add task for R-Mobile APE6 SMP support
Patches were posted as RFC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'projects/linux')
-rw-r--r--projects/linux/core/r8a73a4_smp.yaml30
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diff --git a/projects/linux/core/r8a73a4_smp.yaml b/projects/linux/core/r8a73a4_smp.yaml
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+title: "R-Mobile APE6: Add SMP support"
+
+team: Core
+key: e06f8a62-abe3-11eb-bae6-5b3014b8c809
+status: Active
+assignee: Geert
+
+upstream:
+ - lore: 20210204135409.1652604-1-geert+renesas@glider.be # [PATCH/RFC 0/6] ARM: r8a73a4: Add SMP support
+
+comments:
+ - Known issues:
+ - While initial secondary CPU bring-up during boot works, CPU cores
+ fail to come online after offlining/onlining them using the sysfs
+ interface ("echo [01] > /sys/*/*/cpu/cpu[0-9]*{off,on}line").
+
+ - This breaks detection of the CFI FLASH. I traced this back to
+ setting the SBAR_BAREN bit in the SYSC.CA15BAR register.
+ Presumably this affects the LBSC in some way?
+
+ - To do:
+ - Call into rmobile-sysc instead of hardcoding the SYSC mapping,
+ - Describe CCI-400 in DT and call cci_enable_port_by_index()?
+ - Let pm-rcar-gen2.c call into rcar-rst instead of hardcoding the RST
+ mapping,
+ - Abstract SYSC vs. RST access and merge with pm-rcar-gen2.c?
+
+ - Questions:
+ - Do we want to bring up the Cortex-A7 cores, too? We don't on R-Car
+ H2 neither.