diff options
| author | Laurent Pinchart <laurent.pinchart@ideasonboard.com> | 2021-03-22 02:32:29 +0200 |
|---|---|---|
| committer | Laurent Pinchart <laurent.pinchart@ideasonboard.com> | 2021-03-31 13:43:21 +0300 |
| commit | a408aaef0709c40f4daa53a18c0e1a2386e02df7 (patch) | |
| tree | 8e3056894a38c4a8e0e745f70e7c6f065709c880 /projects/linux/io/done/SDHI-HW-busy-timeout.yaml | |
| parent | 54f5bd29ec86aee45994611cee69c10c7ddb3972 (diff) | |
linux: mm: Move max VGA dot clock validation from Abandoned to New
The ADV7123 VGA DAC has an upper pixel clock frequency limit. It may not
match the values set in the device tree in relevant BSP commits, but it
still has to be taken into account.
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Diffstat (limited to 'projects/linux/io/done/SDHI-HW-busy-timeout.yaml')
0 files changed, 0 insertions, 0 deletions