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| author | Wolfram Sang <wsa+renesas@sang-engineering.com> | 2019-02-06 21:27:09 +0100 |
|---|---|---|
| committer | Wolfram Sang <wsa+renesas@sang-engineering.com> | 2019-02-06 21:27:09 +0100 |
| commit | d5c115890a419f770c5e86e6c840d0f5e4a643ee (patch) | |
| tree | aa6c3a8db43fdd4fa861091a32b1c0acfc9f9f2a /projects/linux/io/bsp392_MSIOF.yaml | |
| parent | 36a0e7618eaeacd7f1ab01e11aaec32b912b012a (diff) | |
projects: add upport tasks from bsp392 for IO
First real data to play with \o/
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Diffstat (limited to 'projects/linux/io/bsp392_MSIOF.yaml')
| -rw-r--r-- | projects/linux/io/bsp392_MSIOF.yaml | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/projects/linux/io/bsp392_MSIOF.yaml b/projects/linux/io/bsp392_MSIOF.yaml new file mode 100644 index 0000000..4297e60 --- /dev/null +++ b/projects/linux/io/bsp392_MSIOF.yaml @@ -0,0 +1,19 @@ +title: "From bsp392, upport MSIOF patches" +team: IO +key: 1185bf87-d9d3-4cbf-a5fa-c46794018cba +status: Active +assignee: Geert + +relationships: + +bsp-commits: + - 0577dba6b377ff60fc5f284ea7bd3eeb28e781f5 # spi: sh-msiof: Add reset of registers before starting transfer + - 9312d43151d28307f527920dafbd7789eabdc63a # spi: sh-msiof: Add MSIOF module clock changing processing for R-Car Gen3 + - a14d0903968f1524304f5b4de3da584778dbdfde # spi: sh-msiof: Set 2 clock delay for R-Car H3 Ver.3.0 only + - f925bf9ef632042ebb32e52108cc97305c15183d # spi: sh-msiof: Add support for r8a7795 + +upstream: + +comments: + - "9312d43151d28307f527920dafbd7789eabdc63a: Proposing 'N': Should use ´assigned-clocks´ and ´assigned-clock-rates´ in board DTS file that actually uses MSIOF" + - "f925bf9ef632042ebb32e52108cc97305c15183d: Proposing 'N': not needed as the driver matches against ´renesas,rcar-gen3-msiof´" |