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| author | Wolfram Sang <wsa+renesas@sang-engineering.com> | 2022-08-22 12:57:39 +0200 |
|---|---|---|
| committer | Wolfram Sang <wsa+renesas@sang-engineering.com> | 2022-08-31 12:43:57 +0200 |
| commit | 78d15e2d3535e8c26663eb5a8e1d80aaec577b4e (patch) | |
| tree | 916c2a3acf1d2ccfb524e0cbcb71cd44e79bee01 /projects/linux/io/SDHI-upport-BSP-fixes.yaml | |
| parent | bcd4ddb77a3cea412d93f8bcb92d0519cbb75426 (diff) | |
projects: linux: io: updates up to W35
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Diffstat (limited to 'projects/linux/io/SDHI-upport-BSP-fixes.yaml')
| -rw-r--r-- | projects/linux/io/SDHI-upport-BSP-fixes.yaml | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/projects/linux/io/SDHI-upport-BSP-fixes.yaml b/projects/linux/io/SDHI-upport-BSP-fixes.yaml index 414cc61..936bdb4 100644 --- a/projects/linux/io/SDHI-upport-BSP-fixes.yaml +++ b/projects/linux/io/SDHI-upport-BSP-fixes.yaml @@ -40,9 +40,13 @@ comments: - 73405fef502d43737be9a50d29935bee133fe7ab, 53c3958c01961421cd2b70c3dfebc9f391e00192 - Only for H3/M3-W ES1.0, but why does mainline work? + - Shimoda-san said that old SoCs had issues with internal DMA end irq not at the same time as transfer end irq + - current HW does not have these issues but to be future-proof, we still want to handle them individually - 20e5623df1aaa74301675122b910f063cdcabe7e, e54e9682fbc229e7a168d63b2e49bc174353caed - Why does mainline work without it? + - Shimoda-san said that old SoCs had issues with internal DMA end irq not at the same time as transfer end irq + - current HW does not have these issues but to be future-proof, we still want to handle them individually - 2d111ff70e13073395f33e989ca2ff63b4fb4d2e - why is it needed? |