diff options
| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2021-05-10 11:55:13 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2021-05-10 12:04:26 +0200 |
| commit | fba71b599887a87df71704fa65f957ff5c0fcf79 (patch) | |
| tree | 618570066c13d7e6d3a945879e99a38bd381edd8 /projects/linux/core | |
| parent | 4dce764e410b5906556434f85af96efa60e20da3 (diff) | |
Auto-update sweep for v5.13-rc1
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'projects/linux/core')
| -rw-r--r-- | projects/linux/core/bsp41x_pinctrl_vin.yaml | 8 | ||||
| -rw-r--r-- | projects/linux/core/rcar3_cpufreq.yaml | 4 |
2 files changed, 6 insertions, 6 deletions
diff --git a/projects/linux/core/bsp41x_pinctrl_vin.yaml b/projects/linux/core/bsp41x_pinctrl_vin.yaml index bd13568..550e430 100644 --- a/projects/linux/core/bsp41x_pinctrl_vin.yaml +++ b/projects/linux/core/bsp41x_pinctrl_vin.yaml @@ -17,10 +17,10 @@ upstream: - torvalds: 8db6cbabac4f2a02ccbce1dbf6845245f38d11f4 # pinctrl: sh-pfc: r8a7796: Add VIN4, VIN5 pins, groups and functions - torvalds: a66b68ba7f288093ea17802442622ac7c0691c92 # pinctrl: sh-pfc: r8a7796: Correct VIN4 18-bit pins - torvalds: b538dc5bbb40dbf214987cc2f30915275057c948 # pinctrl: sh-pfc: r8a7795: Correct VIN4 18-bit pins - - next: f7adcca27edf05fc1f061a9e5de059fe179f0e1c # pinctrl: renesas: r8a77965: Add vin4_g8 and vin5_high8 pins - - next: 2a9e4f74cd57fb7091d4ad627ec58bfd75b50722 # pinctrl: renesas: r8a77990: Add vin4_g8 and vin5_high8 pins - - next: 3d250efb8c32bdcf29e307de624afd25b6c1bff7 # pinctrl: renesas: r8a7796: Add vin4_g8 and vin5_high8 pins - - next: 5f79bbb28be2f09e99ef3477179128af2d8e6f64 # pinctrl: renesas: r8a77951: Add vin4_g8 and vin5_high8 pins + - torvalds: f7adcca27edf05fc1f061a9e5de059fe179f0e1c # pinctrl: renesas: r8a77965: Add vin4_g8 and vin5_high8 pins + - torvalds: 2a9e4f74cd57fb7091d4ad627ec58bfd75b50722 # pinctrl: renesas: r8a77990: Add vin4_g8 and vin5_high8 pins + - torvalds: 3d250efb8c32bdcf29e307de624afd25b6c1bff7 # pinctrl: renesas: r8a7796: Add vin4_g8 and vin5_high8 pins + - torvalds: 5f79bbb28be2f09e99ef3477179128af2d8e6f64 # pinctrl: renesas: r8a77951: Add vin4_g8 and vin5_high8 pins comments: - Upstream has VIN pins, but data8_sft8 are missing diff --git a/projects/linux/core/rcar3_cpufreq.yaml b/projects/linux/core/rcar3_cpufreq.yaml index 45c9883..4899014 100644 --- a/projects/linux/core/rcar3_cpufreq.yaml +++ b/projects/linux/core/rcar3_cpufreq.yaml @@ -13,8 +13,8 @@ bsp41x: upstream: - lore: 20210326120100.1577596-7-geert+renesas@glider.be # [PATCH 6/7] clk: renesas: rcar-gen3: Add custom clock for PLLs - lore: 20210326120100.1577596-8-geert+renesas@glider.be # [PATCH 7/7] clk: renesas: rcar-gen3: Add boost support to Z clocks - - lore: 20210326105009.1574424-3-geert+renesas@glider.be # [PATCH 2/2] arm64: dts: renesas: ulcb: Add cpu-supply property to a57_0 node - - lore: 20210326105009.1574424-2-geert+renesas@glider.be # [PATCH 1/2] arm64: dts: renesas: salvator-common: Add cpu-supply property to a57_0 node + - torvalds: 2b35ca2fe605f85aa1a52c713571baf04a5f434a # [PATCH 2/2] arm64: dts: renesas: ulcb: Add cpu-supply property to a57_0 node + - torvalds: 35e732d7990ddae3ca759c09498dd2c049511297 # [PATCH 1/2] arm64: dts: renesas: salvator-common: Add cpu-supply property to a57_0 node comments: - "98599f0aa8efcf43299c95c392c868f74f69eda0: We need to upport with refactoring." |