diff options
| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2021-11-15 16:24:12 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2021-11-15 16:25:13 +0100 |
| commit | 5f5d8c2bb9c67766bf29192d983aa2096e7369ca (patch) | |
| tree | 9f5d6275810cd87b3c973cb9e7fc6c38ecbea0b2 /projects/linux/core | |
| parent | 519fbf597b624491f1e8c4688aa6d5b73b90d1bc (diff) | |
projects: linux: core: clk: MLP clocks are upstream
Hence no need to upport for bsp-51x.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'projects/linux/core')
| -rw-r--r-- | projects/linux/core/bsp41x_clk_renesas.yaml | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/projects/linux/core/bsp41x_clk_renesas.yaml b/projects/linux/core/bsp41x_clk_renesas.yaml index 736ef56..47584a3 100644 --- a/projects/linux/core/bsp41x_clk_renesas.yaml +++ b/projects/linux/core/bsp41x_clk_renesas.yaml @@ -44,3 +44,6 @@ bsp41x: - e7a6e866fad61e16703ab2433d848926a85f5a8b # clk: renesas: r8a779a0: Add RADSP clocks - 8a6d0d59a9d4d19a1853dd5d6b89b18bc635e348 # clk: renesas: r8a779a0: Add VCPL4 clock - 60151ad45b0ded0aacab6438fbf03631b0f1c14f # clk: renesas: r8a779a0: Add WWDT clocks + +upstream: + - torvalds: 2bd9feed23166f5ab67dec2ca02bd3f74c77b0ba # clk: renesas: r8a779[56]x: Add MLP clocks |