diff options
| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2021-05-03 10:05:12 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2021-05-11 11:00:12 +0200 |
| commit | 1e14f24f7a8fa5b4d88f5120c145d498459c7c5c (patch) | |
| tree | 9f035f3c17aed5d7c2c9761449b7445bba12a58f /projects/linux/core | |
| parent | 1f177090e9ea85d171573b78184650ef9d4d6ba6 (diff) | |
linux: bsp-41x: non-target: Move R-Car H3/M3-W/M3-N DDR2400/2800 support
Not documented in Hardware User's Manual Rev. 2.20.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Diffstat (limited to 'projects/linux/core')
| -rw-r--r-- | projects/linux/core/bsp41x_clk_renesas.yaml | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/projects/linux/core/bsp41x_clk_renesas.yaml b/projects/linux/core/bsp41x_clk_renesas.yaml index 02e8a6f..ebf79c5 100644 --- a/projects/linux/core/bsp41x_clk_renesas.yaml +++ b/projects/linux/core/bsp41x_clk_renesas.yaml @@ -15,18 +15,15 @@ bsp41x: - b1dbacf27857e697fc45a32853a0731150151b6c # clk: renesas: r8a7795: Add iVDP1C clocks to ES1.x - 5423c26953bbe5d689905fa75ab16e969eb73ba0 # clk: renesas: r8a7795: Add VCP4 clock - 83d2393cf2eb84ffb325984c0c74637f8e99966e # clk: renesas: r8a7795: Add ZG clock - - a94771bfac9edcf8b7ca3f4e5f1abe10d2f5b5b4 # clk: renesas: r8a7795: Replace PLL3 multiplication setting - 97a43e88563ea2b0ff55700c8c77b53d278807f4 # clk: renesas: r8a77965: Add ADG clock - c597724fbac9091fc4cd6f5c3862992de9b033ff # clk: renesas: r8a77965: Add VCP4 clocks - f3302aefee22905ae55d5f0d6d72eebceab89b06 # clk: renesas: r8a77965: Add ZG clock - - 03c680e8979f58ea0c0a256f749634a83cf5ddfb # clk: renesas: r8a77965: Replace PLL3 multiplication setting - c2bb14d97eb238ae80fb704a23430a9c41a6ea12 # clk: renesas: r8a7796: Add ADG clock - c86c8885c7071c01489567ecf155501d2a00042c # clk: renesas: r8a7796: Add AVS clock - 64558129af10ee7d149538fc7ecffb4029800d0e # clk: renesas: r8a7796: Add iVDP1C clock - c19b595e501379b8465559afe1f974c3ec8c64d6 # clk: renesas: r8a7796: Add VCP4 clocks - d6ec7401d973ca94d05ada3f536ea90a51ab49c7 # clk: renesas: r8a7796: Add ZG clock - b95564845d3a41210863fc3528290cc2929e0062 # clk: renesas: r8a7796: Remove iVDP1C and FCPCI0 clocks on ES3.0 - - 7129bd9f34f06cbca6221e9809ab522bf71e6abd # clk: renesas: r8a7796: Replace PLL3 multiplication setting - cba445d7f22ba68ca439b51fb0dddc5c7374e73a # clk: renesas: r8a77970: cpg-mssr: Add IMP clocks - 4eff99dc18d7a4ee9897e20e56c6cc4848f8d14f # clk: renesas: r8a77970: cpg-mssr: Add IMR clocks - 40d7f7dbacbe3b2c0dee7dde7e6b8466211ac805 # clk: renesas: r8a77970: cpg-mssr: Add ISP clock |