diff options
| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2021-11-25 09:13:39 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2021-11-25 09:13:39 +0100 |
| commit | 85f830063cfb8f388c5199eeb34fe3df3d8b5225 (patch) | |
| tree | ff72dfbea445cabfbd7d4a5876c0a59526c49489 /projects/linux/core/bsp41x_clk_renesas.yaml | |
| parent | b48cdad42c095978b483fe9fd712abdb583949d1 (diff) | |
linux: bsp-[45]1x: non-target: Move SCCG/Clean peripheral clocks definition
The parameter names of the DEF_GEN3_PE() macro are correct: the second
parent is the clean parent clock.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'projects/linux/core/bsp41x_clk_renesas.yaml')
| -rw-r--r-- | projects/linux/core/bsp41x_clk_renesas.yaml | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/projects/linux/core/bsp41x_clk_renesas.yaml b/projects/linux/core/bsp41x_clk_renesas.yaml index 47584a3..573abd8 100644 --- a/projects/linux/core/bsp41x_clk_renesas.yaml +++ b/projects/linux/core/bsp41x_clk_renesas.yaml @@ -6,7 +6,6 @@ status: New bsp41x: - 226e92814ca5b8ea1ce789869cee131c9bc2a819 # clk: renesas: rcar-gen3: Add support ZG clock divider for R8A77990 - 97a8cbaabb27ab9b53c345798e87ff5de155cf94 # clk: renesas: rcar-gen3: Fix revision of R8A7796 for applying SD_SKIP_FIRST - - 5a2c795936b78619f1f83ff89846efe7e63be2b3 # clk: renesas: rcar-gen3: Fix SCCG/Clean peripheral clocks definition - 630d6bce408c5955192de1053053572ccc66103c # clk: r8a779x: add IMP clock - de03f48327ebdb3c0bb30b4866e27ff158655cc6 # clk: r8a779x: add mlp clock - 8dc96a9c37919b41fbf48747a00cf003f0d00091 # clk: renesas: r8a7795: Add ADG clock |