linux: bsp-41x: core clk triage

Move core clk commits from bsp-41x to separate tasks.
Move upstreamed commits to non target.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

1 files changed, 57 insertions, 0 deletions

diff --git a/projects/linux/core/bsp41x_clk_renesas.yaml b/projects/linux/core/bsp41x_clk_renesas.yaml
new file mode 100644
index 0000000..26d2f2a
--- /dev/null
+++ b/projects/linux/core/bsp41x_clk_renesas.yaml
@@ -0,0 +1,57 @@
+title: "BSP 4.1.x upport clk: renesas"
+team: Core
+key: 1641c746-661f-11eb-94be-d3d0dd2f1615
+status: New
+
+bsp41x:
+ - 7a967a750a3409554d72d9bc3842722e86703125 # clk: Add support parent clock in set_phase
+ - 5e0b119a284593bbe5966da6049e2b5272830954 # clk: rcar-gen3: Add set_phase to set SDnCKCR in HS400
+ - 98599f0aa8efcf43299c95c392c868f74f69eda0 # clk: renesas: rcar-gen3: Add PLL clock and update z-clock for propagating frequency to parent
+ - ff6532cedf1b73081004e7f2b6e38e47e8234040 # clk: renesas: rcar-gen3: Add rounding for Z-clock frequency
+ - 8be3f69874d57fc2bd3563b47ebca7fe189673b2 # clk: renesas: rcar-gen3: Add support when frequency does not propagate to parent in z clock divider
+ - 226e92814ca5b8ea1ce789869cee131c9bc2a819 # clk: renesas: rcar-gen3: Add support ZG clock divider for R8A77990
+ - 97a8cbaabb27ab9b53c345798e87ff5de155cf94 # clk: renesas: rcar-gen3: Fix revision of R8A7796 for applying SD_SKIP_FIRST
+ - 5a2c795936b78619f1f83ff89846efe7e63be2b3 # clk: renesas: rcar-gen3: Fix SCCG/Clean peripheral clocks definition
+ - e2e29b30e3175bdb72d275fea28e1443e8301074 # clk: renesas: cpg-mssr: Fix Realtime Module Stop Control Register offsets
+ - 630d6bce408c5955192de1053053572ccc66103c # clk: r8a779x: add IMP clock
+ - de03f48327ebdb3c0bb30b4866e27ff158655cc6 # clk: r8a779x: add mlp clock
+ - 46fb258928ffef41dc12c818baa4dba083bcb119 # clk: renesas: r8a77{95,965,990}: Remove INTC-AP and INTC-EX clocks
+ - 8dc96a9c37919b41fbf48747a00cf003f0d00091 # clk: renesas: r8a7795: Add ADG clock
+ - 545a5ee67acb14b335f667068569edf568701f14 # clk: renesas: r8a7795: Add AVS clock
+ - b1dbacf27857e697fc45a32853a0731150151b6c # clk: renesas: r8a7795: Add iVDP1C clocks to ES1.x
+ - 5423c26953bbe5d689905fa75ab16e969eb73ba0 # clk: renesas: r8a7795: Add VCP4 clock
+ - 83d2393cf2eb84ffb325984c0c74637f8e99966e # clk: renesas: r8a7795: Add ZG clock
+ - a94771bfac9edcf8b7ca3f4e5f1abe10d2f5b5b4 # clk: renesas: r8a7795: Replace PLL3 multiplication setting
+ - 97a43e88563ea2b0ff55700c8c77b53d278807f4 # clk: renesas: r8a77965: Add ADG clock
+ - c597724fbac9091fc4cd6f5c3862992de9b033ff # clk: renesas: r8a77965: Add VCP4 clocks
+ - f3302aefee22905ae55d5f0d6d72eebceab89b06 # clk: renesas: r8a77965: Add ZG clock
+ - 03c680e8979f58ea0c0a256f749634a83cf5ddfb # clk: renesas: r8a77965: Replace PLL3 multiplication setting
+ - c2bb14d97eb238ae80fb704a23430a9c41a6ea12 # clk: renesas: r8a7796: Add ADG clock
+ - c86c8885c7071c01489567ecf155501d2a00042c # clk: renesas: r8a7796: Add AVS clock
+ - 64558129af10ee7d149538fc7ecffb4029800d0e # clk: renesas: r8a7796: Add iVDP1C clock
+ - c19b595e501379b8465559afe1f974c3ec8c64d6 # clk: renesas: r8a7796: Add VCP4 clocks
+ - d6ec7401d973ca94d05ada3f536ea90a51ab49c7 # clk: renesas: r8a7796: Add ZG clock
+ - 94748de35b7c5df994c8d5d98e0d727bd247fbe7 # clk: renesas: r8a7796: Remove INTC-AP and INTC-EX clocks
+ - b95564845d3a41210863fc3528290cc2929e0062 # clk: renesas: r8a7796: Remove iVDP1C and FCPCI0 clocks on ES3.0
+ - 7129bd9f34f06cbca6221e9809ab522bf71e6abd # clk: renesas: r8a7796: Replace PLL3 multiplication setting
+ - cba445d7f22ba68ca439b51fb0dddc5c7374e73a # clk: renesas: r8a77970: cpg-mssr: Add IMP clocks
+ - 4eff99dc18d7a4ee9897e20e56c6cc4848f8d14f # clk: renesas: r8a77970: cpg-mssr: Add IMR clocks
+ - 40d7f7dbacbe3b2c0dee7dde7e6b8466211ac805 # clk: renesas: r8a77970: cpg-mssr: Add ISP clock
+ - 5b105a78471e25945e5715d568a49bdd2cfb1e89 # clk: renesas: r8a77980: cpg-mssr: Add IMP clocks
+ - dec9d489679ecad3b60dd2e4a72bb6931d97f4eb # clk: renesas: r8a77980: cpg-mssr: Add IMR clocks
+ - da36de1008222ebbd1586c260dbbde0aa4d646c9 # clk: renesas: r8a77980: cpg-mssr: Add ISP clocks
+ - d03ad6826c7ad50104ad62c6ad1d686bfba58f27 # clk: renesas: r8a77980: cpg-mssr: Add VIN clocks
+ - ad35502368df983e59c04c7035d5dd4ad7b35b70 # r8a77980-cpg-mssr: Add VIN 8 - 15 clocks description
+ - d599608fc8c96af6e34c13c2a3ee5ef5b71dff60 # clk: renesas: r8a77980: cpg-mssr: Add VIP clocks
+ - f6165a863d6b73ee7464b7153d4db44b1a9f6389 # drivers: clk: r8a77980-cpg-mssr: Fix ISP parent clock
+ - 9dd769eaf233351b5b9084e3376d13682d454954 # clk: renesas: r8a779a0: Extend number of supported module clocks
+ - 6f778e4eee9560601931843f740dd43ab5f9c070 # clk: renesas: r8a77990: Add ADG clocks
+ - 7072cab285d6beb707f76af0cbeb371aa246f23f # clk: renesas: r8a77990: Add FDP1 clock
+ - 2565115b47318a04f045a8569368aad74a9fa31e # clk: renesas: r8a77990: Add VCP4 clocks
+ - ae24a9705d50622bde086f0ddfcb3130b0742078 # clk: renesas: r8a77990: Add ZG clock
+ - cc77aca0e88791b0f679451cf67572d3d2df49fc # clk: renesas: r8a779a0: Add FBA clocks
+ - 354dc784c78184ef4b5e2fbcd0408da331af4a4f # clk: renesas: r8a779a0: Add FBC clock
+ - 1828d34d7ccb84fc65fd911625ec51a35528e691 # clk: renesas: r8a779a0: Add FCPCS clock
+ - e7a6e866fad61e16703ab2433d848926a85f5a8b # clk: renesas: r8a779a0: Add RADSP clocks
+ - 8a6d0d59a9d4d19a1853dd5d6b89b18bc635e348 # clk: renesas: r8a779a0: Add VCPL4 clock
+ - 60151ad45b0ded0aacab6438fbf03631b0f1c14f # clk: renesas: r8a779a0: Add WWDT clocks