diff options
| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-03-02 09:47:06 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-03-04 09:30:43 +0100 |
| commit | f3f05c79b078bc9bec3fb0a96c39ff83e04e0022 (patch) | |
| tree | c6011e94057d7ab73eb01911f0406203376a6355 /projects/linux/bsp-51x-non-target.yaml | |
| parent | 21ed09c8fdb48a82dc72004e9614a32dc847d3b9 (diff) | |
bsp-[45]1x-upport-request: Move MLP to non-target (upstreamed)
MLP will be upstreamed in v5.18-rc1.
The fix is not applicable.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Diffstat (limited to 'projects/linux/bsp-51x-non-target.yaml')
| -rw-r--r-- | projects/linux/bsp-51x-non-target.yaml | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/projects/linux/bsp-51x-non-target.yaml b/projects/linux/bsp-51x-non-target.yaml index dc28943..56a468a 100644 --- a/projects/linux/bsp-51x-non-target.yaml +++ b/projects/linux/bsp-51x-non-target.yaml @@ -425,3 +425,5 @@ bsp51x: - 778715104029dfdea1dfd5f8d620e91b057c5faf # arm64: dts: renesas: r8a7799a0: Add MSIOF parent clock frequency settings support (Proposing 'N' Should use "assigned-clocks" and "assigned-clock-rates" in board DTS file that actually uses MSIOF) - be2cc95ab62e9f7a9970e50a4f31bda7c4ccc341 # arm64: dts: renesas: r8a779{51, 60, 61, 65, 90}: Add MSIOF parent clock frequency settings support (Proposing 'N' Should use "assigned-clocks" and "assigned-clock-rates" in board DTS file that actually uses MSIOF) - 8ba4541049d6d64a066c367e12a059ce8bcc9196 # spi: sh-msiof: Add MSIOF parent clock (Proposing 'N' Should use "assigned-clocks" and "assigned-clock-rates" in board DTS file that actually uses MSIOF) + - e4c24b1376594879732ce3ad6d5838d5122f036a # arm64: dts: renesas: r8a779x: add mlp nodes (next: fb912a1b474e6e3486f1a5057411fdbeec942ea0 # arm64: dts: renesas: rcar-gen3: Add MOST devices) + - 7becc2e9cfe487fc87e4589913562a361c7b66c2 # arm64: boot: dts: rcar-gen3: Fix MLP IRQ order (upstream never had the wrong order) |