wiki: Porting GMSL Configuration

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>

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+h1. GMSL Configuration
+
+The system is composed by three distinct entities, each one configured separately.
+
+Their configurations and operating modes are below summarized, along with some points that have to be clarified on each component operations.
+
+h2. OV10635
+
+*Relevant Pins and Configuration Parameters*
+
+|_. PIN |_. Function|
+|FSIN | frame sync input|
+|VSYNC |vertical sync output|
+|HREF | horizontal data valid output|
+|D [9:0]| data pins|
+|SIOD-SIOC | SCCB interface|
+
+*VSYNC/HREF Polarities*
+
+Register 0x4708 = 0x00
+
+0x4708 [2] = HREF Polarity
+0x4708 [1] = VSYNC Polarity
+0x4708 [0] = PCLK Polarity
+
+_The sensor datasheet does not report what bit value corresponds to what; Application note or support from OV may be required_
+
+As default value of 0x4708 register is 0x01, we may assume what is reported in timing diagrams in the sensor manual is respected with inverted pixel clock edge (rising instead of default falling).
+As the serializer is configured to latch data on the falling PCLK edge, this seems correct, as timing diagram of serializer operations show data are latched on the edge opposite to the one where pixel are emitted by the sensor)
+
+*Format configuration*
+
+0x4300 = 0x3a = UYVY components ordering
+0x4605 = 0x08 = 8-bit YUV422 mode
+
+*Timing diagram*
+
+!GMSL_Configuration/ov10635_timings.png!
+
+*Note*
+HREF != HSYNC
+HREF (or DE Data Enable) stays high while valid data are output, for the whole line length.
+VSYNC pulses at beginning of a new sensor scanout and stays low during the whole frame output duration.
+
+h2. MAX9271 Serializer
+
+*Relevant Pin and Configuration Parameters*
+
+_LCCEN_: Enable/disable local control channel pins
+         When LCCEN pin is high the serializer operating parameters are configured through register 0x07. Alternatively if LCCEN is    low, pin 14/15/22 and 23 values are used to configure the serializer
+
+Pull-up to Vdd in RDACM20 configuration: register 0x07 is used to configure the following parameters
+
+_DBL_ : Double input mode
+In single input mode, pixel data are latched to PCLK falling/rising edge and their value stored one at the time in LATCH A to be then serialized on GMSL serial link.
+In double input mode, pixel data are read at PCLK/2 frequency and stored in LATCH B two at the time to be then serialized on GMSL serial link.
+Double input mode is required to have the serializer work with higher PCLK frequencies ( in the [33,3 - 100]MHz range in RDACM20).
+
+_HEVN_: Enable HS/VS encoding
+Timing signals generated by the image sensor (VSYNC/HSYNC) are encoded in serial data sent on GSML link.
+
+_BWS_: Serial link bus width. 1 = 32bit bus width; 0 = 24bit bus width;
+
+_EDC_: Error correction enable/disable
+
+_ES_: Specifies if data are latched on rising/falling PCLK edge. 1 = falling edge; 0 = rising edge
+
+*RDACM20 Configuration*
+|_. Parameter |_. Value|
+|DBL | 1|
+|BWS | 0|
+|HVEN | 1|
+|EDC | 0|
+|ES | 1|
+
+RDACM20 uses double input mode, with a 24 bit serial link bus width, HSYNC/VSYNC encoding enabled and error correction disabled (one parity bit per word is used). Data are latched on falling PCLK edge and serialized at PCLK/2 frequency as we're using double input mode.
+
+The 24 bit encoded on the GMSL serial link are:
+
+<pre>
+0:21  = 2 * 11 bit pixel data (LATCH B content, or DIN-A + DIN-B in sensor manual)
+22 = Forward control channel bit
+23 = parity bit
+</pre>
+
+*Note* see Table 2 (input map) because it reports HS and VS signals in DIN-A and DIN-B but they're not part of the data sent on serial link.
+
+*Serial link data output*
+!GMSL_Configuration/IMG_20170822_214808.jpg!
+
+From the serializer manual, same image
+!GMSL_Configuration/max9271-serialization.png!
+
+*Questions*
+There are some ambiguities in the serializer manual.
+
+1) with HVEN enabled, synchronization signals are said to be encoded in data sent on the serial link.
+
+Page 33, _HS/VS Encoding and/or Tracking_ paragraph:
+
+<pre>
+    HS/VS encoding by a GMSL serializer allows horizontal
+    and vertical synchronization signals to be transmitted
+    while conserving pixel data bandwidth. With HS/VS
+    encoding enabled, 10-bit pixel data with a clock up to
+    100MHz can be transmitted using one video pixel of
+    data per HS/VS transition, versus 8-bit data with a clock
+    up to 100MHz without HS/VS encoding.
+</pre>
+
+From this statement it seems that each time VSYNC/HSYNC is detected (see below for what "detected" means) a special packet containing no pixel data but a "code" to indicate VS/HS is sent on the serial link ("code" as in something "GMSL proprietary" and part of the GSML protocol, not described in serializer/deserializer manual).
+
+From MAX9286 de-serializer manual instead, specifically in  the HVSRC parameter description, it seems like the de-serializer expects HS/VS encoded in bits 14:15 (or 16:17) of the data sent on the serial link, along with pixel data.
+
+Possible answer:
+According to information provided by the manual of a different Maxim GMSL serializer (MAX96705) [manual[https://datasheets.maximintegrated.com/en/ds/MAX96705.pdf]], when HS/VS encoding is used, a packet with no pixel data but only informations about synchronism signals are sent during blank periods. Alternatively, if no HS/VS encoding is used, 2 bit of pixel data are reserved for HS/VS tracking. This seems to match the "10-bit vs 8-bit" reported in the above quote from serializer manual.
+
+2) The following statement is not clear to me.
+Page 33, _HS/VS Encoding and/or Tracking_ paragraph
+
+<pre>
+    HS/VS encoding sends packets when HSYNC or VSYNC is low, use H/V
+    inversion register bits if input HSYNC and VSYNC signals
+    use an active-low convention to send data packets during the
+    inactive pixel clock periods.
+</pre>
+
+It seems from this statement that the serializer expects VSYNC to behave as Data Valid (stay high during the whole frame duration) and low during frame blanking (which is basically the inverted logic compared to what the image sensor does).
+If this is true, we should receive VSYNC packets during the whole frame duration, but that's not possible, as we actually receive data. Also, VSYNC polarity is inverted on de-serializer side, not on serializer one.
+
+Possible answer:
+The above quote from the serializer manual may be interpreted simply as the confirmation that packets containing encoded HS/VS information (now that another serializer manual confirmed that actual packets are sent for this purpose) are sent on the serial link when the synch signal is low, to guarantee no active pixel data are sent by the sensor during this "inactive" periods (this allows to connect HREF signal to HSYNC, as it happens in rdacm20 configuration).
+
+It is legit to assume the encoded HS/VS signals are sent recording transactions of falling and rising edges
+
+*Synchronism signal timings*
+To be verified in image sensor configuration if the following constraints are respected
+
+With DBL=1:
+* HS/VS low pulse duration >= 5 PCLK cycles
+* HS/VS high pulse duration >= 2 PCLK cycles
+* Active duration of HS/VS + Blankings must be an even multiple of PCLK pulses
+
+h2. MAX9286 De-Serializer
+
+*De-serializer Configuration Parameters*
+
+*general configuration*
+Register 0x12
+|DBL | 1|
+|EDC | 0|
+|BWS |0 (pull down to ground)|
+
+*FSYNC and VSYNC signal configuration*
+
+The de-serializer run by default with inverted VSYNC
+Register 0x0c
+|HVEN  |1|
+|INVS  |1|
+|HVSRC | 01|
+
+FSYNC parameters
+
+|_. Parameter |_. Register |_. Bits |_.Default value |_.max9286 setting|_. Comment |
+|MSTLINKSEL | 0x00 | 7:5 | 111 | 111| Autodetect link used for CSI clock source |
+|EN_VS_GEN| 0x00 | 4 | 0 | 0 | Disable internal VSYNC (comes from Cameras) |
+|FSYNCMODE | 0x01 | 7:6 | 00 | 00 | Internally generate FSYNC|
+|FSYNCMETH | 0x01 | 1:0 | 10 | 10 | Auto mode: fsync follows slowest link |
+|FSYNC_PERDIV | 0x02 | 7:4 | 0000 | 0000 | FSYNC generated after 1 VSYNC pulse (on slowest link: auto mode) |
+|KVALSIGN | 0x03 | 4 | 0 | 0 | Positive KVAL value |
+|KVAL| 0x03 | 3:0 | 0001 | 0001 | 2us margin respect to rising edge of sloweset (auto mode) link |
+|PVALL|0x04 | 7:0 | 00000000 | 00000000 | Desired margin in PCLK cycles from rising edge of slowest (auto mode) link; Low byte |
+|PVALH| 0x05 | 4:0 | 0000 | 0000 | Desired margin in PCLK cycles from rising edge of slowest (auto mode) link; High byte |
+|PVALSIGN| 0x05 | 5 | 0 | 0 | Positive PVAL value |
+|FRMDIFFTHRL| 0x61 | 7:0 | 0 | 0 | Low byte of error threshold between the earliest and latest
+VSYNC (in pixel clock cycles) |
+|FRMDIFFTHRL| 0x62 | 4:0 | 01111 | 01111 | High byte of error threshold between the earliest and latest
+VSYNC (in pixel clock cycles). Disabled if all 13 bits are 0s|
+|ENFSINLAST | 0x64 | 5 | 0 | 0 |  FSIN occurs anytime between VS rising edges (alternative is: FSIN occurs after all VS rising edges|
+
+KVAL and PVAL not configured in max9286 setup :/
+
+The previously values determinate how frame synchronization is performed
+
+!GMSL_Configuration/fsync.png!
+
+
+*HS/VS location*/
+
+HVSRC parameter description in register 0x0c (page 66) reports that the de-serializer expects HS/VS in bit 14:15
+
+<pre>
+    Use D14/D15 for HSYNC/VSYNC (D[19:16] shifted to D[17:14]).
+    For use with the MAX9271 when DBL = 0 or when HVEN = 1._
+</pre>
+
+The following image describing the input map expected by deserializer for yuv8 format confirms that
+
+!GMSL_Configuration/de-serializer-input-map.png!
+
+This seems pretty different from what the serializer sends on the serial link, as bit 0:21 are reserved for two 11bit pixel data word, and there is no mention of HS/VS encoding in bits 14:15 (or 16:17).
+So, HS/VS are either encoded in special packets with no pixel data (something like CSI-2 short packets) or their bits part of the data sent on the serial link along with pixel data (but in that case, it seems all the 24 bits used by the serializer are actually used by two pixel data word)
+
+*VSYNC inversion*
+The deserializer is configured to run with inverted VSYNC output on CSI bus.
+See below what it can possibly mean (inversion of short packet vertical synchronization codes?)
+
+h2. Open issues and testing
+
+A list of open issues and performed testing is reported in the following page
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