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authorWolfram Sang <wsa+renesas@sang-engineering.com>2021-11-04 14:02:38 +0100
committerWolfram Sang <wsa+renesas@sang-engineering.com>2021-11-04 14:02:38 +0100
commit501b031615e0559c53d60a8a0c00d278cd9707a4 (patch)
tree27322dd65f671529a6b89440c7cff7eb1005d426
parentf5c3fceb5911adde86b44d3a914143e5af032024 (diff)
projects: linux: io: update tasks after meeting 20211104
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
-rw-r--r--projects/linux/io/RPC-enable-burst.yaml12
-rw-r--r--projects/linux/io/SDHI-refactor-SDHn.yaml1
-rw-r--r--projects/linux/io/SDHI-refactor-abort-tuning.yaml2
-rw-r--r--projects/linux/io/V3U-enable_CAN.yaml2
-rw-r--r--projects/linux/io/V3U-enable_PWM.yaml3
-rw-r--r--projects/linux/io/V3U-enable_RPC.yaml14
-rw-r--r--projects/linux/io/V3U-enable_TPU.yaml5
7 files changed, 30 insertions, 9 deletions
diff --git a/projects/linux/io/RPC-enable-burst.yaml b/projects/linux/io/RPC-enable-burst.yaml
new file mode 100644
index 0000000..426946f
--- /dev/null
+++ b/projects/linux/io/RPC-enable-burst.yaml
@@ -0,0 +1,12 @@
+title: RPC; enable burst read operation
+team: IO
+key: 7c83dec2-3d6f-11ec-bbab-9b62e2056cce
+status: New
+
+bsp41x:
+ - c419cfd7766efb7bbc95d964586ca3668b61cdb7 # memory: renesas-rpc-if: Use burst read operation
+
+upstream:
+
+comments:
+ - needs more investigation if burst read support needs more driver updates than this commit
diff --git a/projects/linux/io/SDHI-refactor-SDHn.yaml b/projects/linux/io/SDHI-refactor-SDHn.yaml
index 8d8f337..0cd55e5 100644
--- a/projects/linux/io/SDHI-refactor-SDHn.yaml
+++ b/projects/linux/io/SDHI-refactor-SDHn.yaml
@@ -17,3 +17,4 @@ comments:
- "This allows us to handle proper frequency settings from the SDHI driver"
- "Wolfram has a sketch with two clocks using generic divider and gate combined"
- "rfc v1: https://lore.kernel.org/r/20210928200804.50922-1-wsa+renesas@sang-engineering.com"
+ - "rfc v2 in progress; working out details for the DT binding scheme"
diff --git a/projects/linux/io/SDHI-refactor-abort-tuning.yaml b/projects/linux/io/SDHI-refactor-abort-tuning.yaml
index 9cc71ed..765483e 100644
--- a/projects/linux/io/SDHI-refactor-abort-tuning.yaml
+++ b/projects/linux/io/SDHI-refactor-abort-tuning.yaml
@@ -14,3 +14,5 @@ comments:
- for Wolfram's setup, the issue only happens with 4tap devices and a SanDisk card
- another alternative seems to use the 1:4 divider instead of the 2:2
- needs further investigation
+ - BSP team reports that the 1:4 divider doesn't work for them
+ - next step is discover why the 100ms delay works and if we can find a better condition to wait for
diff --git a/projects/linux/io/V3U-enable_CAN.yaml b/projects/linux/io/V3U-enable_CAN.yaml
index 647237e..71844c4 100644
--- a/projects/linux/io/V3U-enable_CAN.yaml
+++ b/projects/linux/io/V3U-enable_CAN.yaml
@@ -24,3 +24,5 @@ comments:
- v1; https://lore.kernel.org/r/20210924153113.10046-1-uli+renesas@fpond.eu
- Renesas Japan cannot test these changes, we have to find our own way
- discussing with Kieran and Ulrich how to accomplish this
+ - Kieran can connect CAN interfaces of the Falcon board now
+ - Uli is working on scripts to ease testing
diff --git a/projects/linux/io/V3U-enable_PWM.yaml b/projects/linux/io/V3U-enable_PWM.yaml
index 3489c64..f62a781 100644
--- a/projects/linux/io/V3U-enable_PWM.yaml
+++ b/projects/linux/io/V3U-enable_PWM.yaml
@@ -17,5 +17,8 @@ comments:
- however, unlike other Gen3 SoCs the V3U doesn't allow GPIO sniffing by default
- asking HW team if this can be achieved somehow
+ - d9dbda2f774c38dd60f3b17b7e3dac11bb0e3a97, 73d8a0fb46ab4f822f953ad20e5fbdb5998352c1, 91284dd61b7c36fe536d8ad6c473bbc04b4328da
+ - prototype patches made, only testing needed
+
- e9369406a0e148ddf941519ad7c4f54e4c8bdaec
- won't be upported because there are no users on the boards
diff --git a/projects/linux/io/V3U-enable_RPC.yaml b/projects/linux/io/V3U-enable_RPC.yaml
index 653df63..68abcaf 100644
--- a/projects/linux/io/V3U-enable_RPC.yaml
+++ b/projects/linux/io/V3U-enable_RPC.yaml
@@ -5,7 +5,6 @@ status: Active
assignee: Wolfram
bsp41x:
- - c419cfd7766efb7bbc95d964586ca3668b61cdb7 # memory: renesas-rpc-if: Use burst read operation
- f817442ce56d351a2c69515570ca750edb54622b # memory: renesas-rpc-if: Do not write to reserved bits
- 3612986e5109c4de99cd3f75caf5bf6c756ef0f0 # memory: renesas-rpc-if: Correct data transfer in Manual mode
- 85f41a8a4d61f366d1591516349ba2447a59e06f # Revert "memory: renesas-rpc-if: Correct data transfer in Manual mode"
@@ -15,8 +14,12 @@ bsp41x:
- 44c210c0fa36a53c3fb08e95e5a6dad8ad9b345d # arm64: dts: renesas: falcon: Add QSPI flash support
upstream:
- - next: fff53a551db50f5edecaa0b29a64056ab8d2bbca # memory: renesas-rpc-if: Correct QSPI data transfer in Manual mode
- - next: 797f082738b10ff397c8d3b7804b747d766e62e6 # dt-bindings: rpc: renesas-rpc-if: Add support for the R8A779A0 RPC-IF
+ - torvalds: fff53a551db50f5edecaa0b29a64056ab8d2bbca # memory: renesas-rpc-if: Correct QSPI data transfer in Manual mode
+ - torvalds: 797f082738b10ff397c8d3b7804b747d766e62e6 # dt-bindings: rpc: renesas-rpc-if: Add support for the R8A779A0 RPC-IF
+ - torvalds: 6f21d145b90f3f5769eb6615af601a973e365a64 # clk: renesas: cpg-lib: Move RPC clock registration to the library
+ - torvalds: 27c9d7635d23416f5e791508882f34157dde23f5 # clk: renesas: r8a779a0: Add RPC support
+ - torvalds: 5de968a25a30302c7714ae1c80b0eaff6834e2ed # arm64: dts: renesas: r8a779a0: Add RPC node
+ - torvalds: f28daeedd7f920e172d60a97341be42430175a42 # arm64: dts: renesas: falcon-cpu: Add SPI flash via RPC
comments:
- because HW access to V3U is still very limited, it is suggested to upport/refactor the driver fixes using locally available boards first
@@ -24,10 +27,6 @@ comments:
- another option is to use Eagle/Condor boards remotely with JFFS2 and check for CRC failures
- using the user-partition on an Eagle board turned out to be sufficient
- - c419cfd7766efb7bbc95d964586ca3668b61cdb7
- - not a bugfix, no need to upport now
- - needs more investigation if burst read support needs more driver updates
- - will be refactored to seperate task
- f817442ce56d351a2c69515570ca750edb54622b
- needs more information why the undocumented bits were needed previously
- further investigation showed that the patch is okay, but maybe one bitfield was accidently removed
@@ -48,6 +47,7 @@ comments:
- rfc v1; https://lore.kernel.org/r/20210913065317.2297-1-wsa+renesas@sang-engineering.com
- v1; https://lore.kernel.org/r/20210929064924.1997-1-wsa+renesas@sang-engineering.com
- v2; https://lore.kernel.org/r/20211006085836.42155-1-wsa+renesas@sang-engineering.com
+ - merged
- b587ed1d5e129cc32ab3c69b9489377bf158b9b6
- v1; https://lore.kernel.org/r/20210922085831.5375-1-wsa+renesas@sang-engineering.com
- merged
diff --git a/projects/linux/io/V3U-enable_TPU.yaml b/projects/linux/io/V3U-enable_TPU.yaml
index 0c2cd99..939da88 100644
--- a/projects/linux/io/V3U-enable_TPU.yaml
+++ b/projects/linux/io/V3U-enable_TPU.yaml
@@ -12,8 +12,9 @@ bsp41x:
- e3552b314c8c27c57868f38f257ea1a0a0cf66ee # arm64: dts: r8a779a0-falcon: Add TPU support
upstream:
- - next: bdd8b0053f4ff0df889bd849f0789580e9faea3a # arm64: dts: renesas: r8a779a0: Add TPU device node
- - next: 3e9dd11db00119001a1d05413f51804a35559956 # arm64: defconfig: Add Renesas TPU as module
+ - torvalds: c6d387612b6659d6ea183cede83bb1635f62d117 # arm64: dts: renesas: r8a77961: Add TPU device node
+ - torvalds: bdd8b0053f4ff0df889bd849f0789580e9faea3a # arm64: dts: renesas: r8a779a0: Add TPU device node
+ - torvalds: 3e9dd11db00119001a1d05413f51804a35559956 # arm64: defconfig: Add Renesas TPU as module
comments:
- TPU can probably be tested using GPIO_CN with the GPIO logic analyzer