diff options
| author | Laurent Pinchart <laurent.pinchart@ideasonboard.com> | 2013-03-01 17:08:40 +0100 |
|---|---|---|
| committer | Laurent Pinchart <laurent.pinchart@ideasonboard.com> | 2013-03-01 17:08:40 +0100 |
| commit | c8998259fd683e7cc7c6dee88067baa9af477a03 (patch) | |
| tree | 2dd7840302b795bebaee4852ba92e064d6ecb855 /bionic | |
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Diffstat (limited to 'bionic')
| -rw-r--r-- | bionic/0001-bionic-Add-kernel-drm-headers.patch | 6247 |
1 files changed, 6247 insertions, 0 deletions
diff --git a/bionic/0001-bionic-Add-kernel-drm-headers.patch b/bionic/0001-bionic-Add-kernel-drm-headers.patch new file mode 100644 index 0000000..b9c7fca --- /dev/null +++ b/bionic/0001-bionic-Add-kernel-drm-headers.patch @@ -0,0 +1,6247 @@ +From 0778bf808f246a6962cc17e15a13d42714d8a420 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Date: Sat, 15 Sep 2012 04:23:37 +0200 +Subject: [PATCH] bionic: Add kernel drm headers + +Import kernel headers from Linux v3.6. + +Change-Id: I21b4aa3931f42e3547cb70d2f96493b6a82a8471 +Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +--- + libc/kernel/common/drm/drm.h | 828 ++++++++++++++++++++++++++++ + libc/kernel/common/drm/drm_fourcc.h | 133 +++++ + libc/kernel/common/drm/drm_mode.h | 463 ++++++++++++++++ + libc/kernel/common/drm/drm_sarea.h | 82 +++ + libc/kernel/common/drm/exynos_drm.h | 203 +++++++ + libc/kernel/common/drm/i810_drm.h | 281 ++++++++++ + libc/kernel/common/drm/i915_drm.h | 913 +++++++++++++++++++++++++++++++ + libc/kernel/common/drm/mga_drm.h | 419 +++++++++++++++ + libc/kernel/common/drm/nouveau_drm.h | 138 +++++ + libc/kernel/common/drm/r128_drm.h | 326 ++++++++++++ + libc/kernel/common/drm/radeon_drm.h | 976 ++++++++++++++++++++++++++++++++++ + libc/kernel/common/drm/savage_drm.h | 210 ++++++++ + libc/kernel/common/drm/sis_drm.h | 71 +++ + libc/kernel/common/drm/via_drm.h | 279 ++++++++++ + libc/kernel/common/drm/vmwgfx_drm.h | 790 +++++++++++++++++++++++++++ + 15 files changed, 6112 insertions(+), 0 deletions(-) + create mode 100644 libc/kernel/common/drm/drm.h + create mode 100644 libc/kernel/common/drm/drm_fourcc.h + create mode 100644 libc/kernel/common/drm/drm_mode.h + create mode 100644 libc/kernel/common/drm/drm_sarea.h + create mode 100644 libc/kernel/common/drm/exynos_drm.h + create mode 100644 libc/kernel/common/drm/i810_drm.h + create mode 100644 libc/kernel/common/drm/i915_drm.h + create mode 100644 libc/kernel/common/drm/mga_drm.h + create mode 100644 libc/kernel/common/drm/nouveau_drm.h + create mode 100644 libc/kernel/common/drm/r128_drm.h + create mode 100644 libc/kernel/common/drm/radeon_drm.h + create mode 100644 libc/kernel/common/drm/savage_drm.h + create mode 100644 libc/kernel/common/drm/sis_drm.h + create mode 100644 libc/kernel/common/drm/via_drm.h + create mode 100644 libc/kernel/common/drm/vmwgfx_drm.h + +diff --git a/libc/kernel/common/drm/drm.h b/libc/kernel/common/drm/drm.h +new file mode 100644 +index 0000000..9be8203 +--- /dev/null ++++ b/libc/kernel/common/drm/drm.h +@@ -0,0 +1,828 @@ ++/** ++ * \file drm.h ++ * Header for the Direct Rendering Manager ++ * ++ * \author Rickard E. (Rik) Faith <faith@valinux.com> ++ * ++ * \par Acknowledgments: ++ * Dec 1999, Richard Henderson <rth@twiddle.net>, move to generic \c cmpxchg. ++ */ ++ ++/* ++ * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. ++ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. ++ * All rights reserved. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice (including the next ++ * paragraph) shall be included in all copies or substantial portions of the ++ * Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++#ifndef _DRM_H_ ++#define _DRM_H_ ++ ++#if defined(__linux__) ++ ++#include <linux/types.h> ++#include <asm/ioctl.h> ++typedef unsigned int drm_handle_t; ++ ++#else /* One of the BSDs */ ++ ++#include <sys/ioccom.h> ++#include <sys/types.h> ++typedef int8_t __s8; ++typedef uint8_t __u8; ++typedef int16_t __s16; ++typedef uint16_t __u16; ++typedef int32_t __s32; ++typedef uint32_t __u32; ++typedef int64_t __s64; ++typedef uint64_t __u64; ++typedef unsigned long drm_handle_t; ++ ++#endif ++ ++#define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */ ++#define DRM_MIN_ORDER 5 /**< At least 2^5 bytes = 32 bytes */ ++#define DRM_MAX_ORDER 22 /**< Up to 2^22 bytes = 4MB */ ++#define DRM_RAM_PERCENT 10 /**< How much system ram can we lock? */ ++ ++#define _DRM_LOCK_HELD 0x80000000U /**< Hardware lock is held */ ++#define _DRM_LOCK_CONT 0x40000000U /**< Hardware lock is contended */ ++#define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD) ++#define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT) ++#define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT)) ++ ++typedef unsigned int drm_context_t; ++typedef unsigned int drm_drawable_t; ++typedef unsigned int drm_magic_t; ++ ++/** ++ * Cliprect. ++ * ++ * \warning: If you change this structure, make sure you change ++ * XF86DRIClipRectRec in the server as well ++ * ++ * \note KW: Actually it's illegal to change either for ++ * backwards-compatibility reasons. ++ */ ++struct drm_clip_rect { ++ unsigned short x1; ++ unsigned short y1; ++ unsigned short x2; ++ unsigned short y2; ++}; ++ ++/** ++ * Drawable information. ++ */ ++struct drm_drawable_info { ++ unsigned int num_rects; ++ struct drm_clip_rect *rects; ++}; ++ ++/** ++ * Texture region, ++ */ ++struct drm_tex_region { ++ unsigned char next; ++ unsigned char prev; ++ unsigned char in_use; ++ unsigned char padding; ++ unsigned int age; ++}; ++ ++/** ++ * Hardware lock. ++ * ++ * The lock structure is a simple cache-line aligned integer. To avoid ++ * processor bus contention on a multiprocessor system, there should not be any ++ * other data stored in the same cache line. ++ */ ++struct drm_hw_lock { ++ __volatile__ unsigned int lock; /**< lock variable */ ++ char padding[60]; /**< Pad to cache line */ ++}; ++ ++/** ++ * DRM_IOCTL_VERSION ioctl argument type. ++ * ++ * \sa drmGetVersion(). ++ */ ++struct drm_version { ++ int version_major; /**< Major version */ ++ int version_minor; /**< Minor version */ ++ int version_patchlevel; /**< Patch level */ ++ size_t name_len; /**< Length of name buffer */ ++ char *name; /**< Name of driver */ ++ size_t date_len; /**< Length of date buffer */ ++ char *date; /**< User-space buffer to hold date */ ++ size_t desc_len; /**< Length of desc buffer */ ++ char *desc; /**< User-space buffer to hold desc */ ++}; ++ ++/** ++ * DRM_IOCTL_GET_UNIQUE ioctl argument type. ++ * ++ * \sa drmGetBusid() and drmSetBusId(). ++ */ ++struct drm_unique { ++ size_t unique_len; /**< Length of unique */ ++ char *unique; /**< Unique name for driver instantiation */ ++}; ++ ++struct drm_list { ++ int count; /**< Length of user-space structures */ ++ struct drm_version *version; ++}; ++ ++struct drm_block { ++ int unused; ++}; ++ ++/** ++ * DRM_IOCTL_CONTROL ioctl argument type. ++ * ++ * \sa drmCtlInstHandler() and drmCtlUninstHandler(). ++ */ ++struct drm_control { ++ enum { ++ DRM_ADD_COMMAND, ++ DRM_RM_COMMAND, ++ DRM_INST_HANDLER, ++ DRM_UNINST_HANDLER ++ } func; ++ int irq; ++}; ++ ++/** ++ * Type of memory to map. ++ */ ++enum drm_map_type { ++ _DRM_FRAME_BUFFER = 0, /**< WC (no caching), no core dump */ ++ _DRM_REGISTERS = 1, /**< no caching, no core dump */ ++ _DRM_SHM = 2, /**< shared, cached */ ++ _DRM_AGP = 3, /**< AGP/GART */ ++ _DRM_SCATTER_GATHER = 4, /**< Scatter/gather memory for PCI DMA */ ++ _DRM_CONSISTENT = 5, /**< Consistent memory for PCI DMA */ ++ _DRM_GEM = 6, /**< GEM object */ ++}; ++ ++/** ++ * Memory mapping flags. ++ */ ++enum drm_map_flags { ++ _DRM_RESTRICTED = 0x01, /**< Cannot be mapped to user-virtual */ ++ _DRM_READ_ONLY = 0x02, ++ _DRM_LOCKED = 0x04, /**< shared, cached, locked */ ++ _DRM_KERNEL = 0x08, /**< kernel requires access */ ++ _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */ ++ _DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */ ++ _DRM_REMOVABLE = 0x40, /**< Removable mapping */ ++ _DRM_DRIVER = 0x80 /**< Managed by driver */ ++}; ++ ++struct drm_ctx_priv_map { ++ unsigned int ctx_id; /**< Context requesting private mapping */ ++ void *handle; /**< Handle of map */ ++}; ++ ++/** ++ * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls ++ * argument type. ++ * ++ * \sa drmAddMap(). ++ */ ++struct drm_map { ++ unsigned long offset; /**< Requested physical address (0 for SAREA)*/ ++ unsigned long size; /**< Requested physical size (bytes) */ ++ enum drm_map_type type; /**< Type of memory to map */ ++ enum drm_map_flags flags; /**< Flags */ ++ void *handle; /**< User-space: "Handle" to pass to mmap() */ ++ /**< Kernel-space: kernel-virtual address */ ++ int mtrr; /**< MTRR slot used */ ++ /* Private data */ ++}; ++ ++/** ++ * DRM_IOCTL_GET_CLIENT ioctl argument type. ++ */ ++struct drm_client { ++ int idx; /**< Which client desired? */ ++ int auth; /**< Is client authenticated? */ ++ unsigned long pid; /**< Process ID */ ++ unsigned long uid; /**< User ID */ ++ unsigned long magic; /**< Magic */ ++ unsigned long iocs; /**< Ioctl count */ ++}; ++ ++enum drm_stat_type { ++ _DRM_STAT_LOCK, ++ _DRM_STAT_OPENS, ++ _DRM_STAT_CLOSES, ++ _DRM_STAT_IOCTLS, ++ _DRM_STAT_LOCKS, ++ _DRM_STAT_UNLOCKS, ++ _DRM_STAT_VALUE, /**< Generic value */ ++ _DRM_STAT_BYTE, /**< Generic byte counter (1024bytes/K) */ ++ _DRM_STAT_COUNT, /**< Generic non-byte counter (1000/k) */ ++ ++ _DRM_STAT_IRQ, /**< IRQ */ ++ _DRM_STAT_PRIMARY, /**< Primary DMA bytes */ ++ _DRM_STAT_SECONDARY, /**< Secondary DMA bytes */ ++ _DRM_STAT_DMA, /**< DMA */ ++ _DRM_STAT_SPECIAL, /**< Special DMA (e.g., priority or polled) */ ++ _DRM_STAT_MISSED /**< Missed DMA opportunity */ ++ /* Add to the *END* of the list */ ++}; ++ ++/** ++ * DRM_IOCTL_GET_STATS ioctl argument type. ++ */ ++struct drm_stats { ++ unsigned long count; ++ struct { ++ unsigned long value; ++ enum drm_stat_type type; ++ } data[15]; ++}; ++ ++/** ++ * Hardware locking flags. ++ */ ++enum drm_lock_flags { ++ _DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */ ++ _DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */ ++ _DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */ ++ _DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */ ++ /* These *HALT* flags aren't supported yet ++ -- they will be used to support the ++ full-screen DGA-like mode. */ ++ _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */ ++ _DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */ ++}; ++ ++/** ++ * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type. ++ * ++ * \sa drmGetLock() and drmUnlock(). ++ */ ++struct drm_lock { ++ int context; ++ enum drm_lock_flags flags; ++}; ++ ++/** ++ * DMA flags ++ * ++ * \warning ++ * These values \e must match xf86drm.h. ++ * ++ * \sa drm_dma. ++ */ ++enum drm_dma_flags { ++ /* Flags for DMA buffer dispatch */ ++ _DRM_DMA_BLOCK = 0x01, /**< ++ * Block until buffer dispatched. ++ * ++ * \note The buffer may not yet have ++ * been processed by the hardware -- ++ * getting a hardware lock with the ++ * hardware quiescent will ensure ++ * that the buffer has been ++ * processed. ++ */ ++ _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */ ++ _DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */ ++ ++ /* Flags for DMA buffer request */ ++ _DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */ ++ _DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */ ++ _DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */ ++}; ++ ++/** ++ * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type. ++ * ++ * \sa drmAddBufs(). ++ */ ++struct drm_buf_desc { ++ int count; /**< Number of buffers of this size */ ++ int size; /**< Size in bytes */ ++ int low_mark; /**< Low water mark */ ++ int high_mark; /**< High water mark */ ++ enum { ++ _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */ ++ _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */ ++ _DRM_SG_BUFFER = 0x04, /**< Scatter/gather memory buffer */ ++ _DRM_FB_BUFFER = 0x08, /**< Buffer is in frame buffer */ ++ _DRM_PCI_BUFFER_RO = 0x10 /**< Map PCI DMA buffer read-only */ ++ } flags; ++ unsigned long agp_start; /**< ++ * Start address of where the AGP buffers are ++ * in the AGP aperture ++ */ ++}; ++ ++/** ++ * DRM_IOCTL_INFO_BUFS ioctl argument type. ++ */ ++struct drm_buf_info { ++ int count; /**< Entries in list */ ++ struct drm_buf_desc *list; ++}; ++ ++/** ++ * DRM_IOCTL_FREE_BUFS ioctl argument type. ++ */ ++struct drm_buf_free { ++ int count; ++ int *list; ++}; ++ ++/** ++ * Buffer information ++ * ++ * \sa drm_buf_map. ++ */ ++struct drm_buf_pub { ++ int idx; /**< Index into the master buffer list */ ++ int total; /**< Buffer size */ ++ int used; /**< Amount of buffer in use (for DMA) */ ++ void *address; /**< Address of buffer */ ++}; ++ ++/** ++ * DRM_IOCTL_MAP_BUFS ioctl argument type. ++ */ ++struct drm_buf_map { ++ int count; /**< Length of the buffer list */ ++ void *virtual; /**< Mmap'd area in user-virtual */ ++ struct drm_buf_pub *list; /**< Buffer information */ ++}; ++ ++/** ++ * DRM_IOCTL_DMA ioctl argument type. ++ * ++ * Indices here refer to the offset into the buffer list in drm_buf_get. ++ * ++ * \sa drmDMA(). ++ */ ++struct drm_dma { ++ int context; /**< Context handle */ ++ int send_count; /**< Number of buffers to send */ ++ int *send_indices; /**< List of handles to buffers */ ++ int *send_sizes; /**< Lengths of data to send */ ++ enum drm_dma_flags flags; /**< Flags */ ++ int request_count; /**< Number of buffers requested */ ++ int request_size; /**< Desired size for buffers */ ++ int *request_indices; /**< Buffer information */ ++ int *request_sizes; ++ int granted_count; /**< Number of buffers granted */ ++}; ++ ++enum drm_ctx_flags { ++ _DRM_CONTEXT_PRESERVED = 0x01, ++ _DRM_CONTEXT_2DONLY = 0x02 ++}; ++ ++/** ++ * DRM_IOCTL_ADD_CTX ioctl argument type. ++ * ++ * \sa drmCreateContext() and drmDestroyContext(). ++ */ ++struct drm_ctx { ++ drm_context_t handle; ++ enum drm_ctx_flags flags; ++}; ++ ++/** ++ * DRM_IOCTL_RES_CTX ioctl argument type. ++ */ ++struct drm_ctx_res { ++ int count; ++ struct drm_ctx *contexts; ++}; ++ ++/** ++ * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type. ++ */ ++struct drm_draw { ++ drm_drawable_t handle; ++}; ++ ++/** ++ * DRM_IOCTL_UPDATE_DRAW ioctl argument type. ++ */ ++typedef enum { ++ DRM_DRAWABLE_CLIPRECTS, ++} drm_drawable_info_type_t; ++ ++struct drm_update_draw { ++ drm_drawable_t handle; ++ unsigned int type; ++ unsigned int num; ++ unsigned long long data; ++}; ++ ++/** ++ * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type. ++ */ ++struct drm_auth { ++ drm_magic_t magic; ++}; ++ ++/** ++ * DRM_IOCTL_IRQ_BUSID ioctl argument type. ++ * ++ * \sa drmGetInterruptFromBusID(). ++ */ ++struct drm_irq_busid { ++ int irq; /**< IRQ number */ ++ int busnum; /**< bus number */ ++ int devnum; /**< device number */ ++ int funcnum; /**< function number */ ++}; ++ ++enum drm_vblank_seq_type { ++ _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */ ++ _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */ ++ /* bits 1-6 are reserved for high crtcs */ ++ _DRM_VBLANK_HIGH_CRTC_MASK = 0x0000003e, ++ _DRM_VBLANK_EVENT = 0x4000000, /**< Send event instead of blocking */ ++ _DRM_VBLANK_FLIP = 0x8000000, /**< Scheduled buffer swap should flip */ ++ _DRM_VBLANK_NEXTONMISS = 0x10000000, /**< If missed, wait for next vblank */ ++ _DRM_VBLANK_SECONDARY = 0x20000000, /**< Secondary display controller */ ++ _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking, unsupported */ ++}; ++#define _DRM_VBLANK_HIGH_CRTC_SHIFT 1 ++ ++#define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE) ++#define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_EVENT | _DRM_VBLANK_SIGNAL | \ ++ _DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS) ++ ++struct drm_wait_vblank_request { ++ enum drm_vblank_seq_type type; ++ unsigned int sequence; ++ unsigned long signal; ++}; ++ ++struct drm_wait_vblank_reply { ++ enum drm_vblank_seq_type type; ++ unsigned int sequence; ++ long tval_sec; ++ long tval_usec; ++}; ++ ++/** ++ * DRM_IOCTL_WAIT_VBLANK ioctl argument type. ++ * ++ * \sa drmWaitVBlank(). ++ */ ++union drm_wait_vblank { ++ struct drm_wait_vblank_request request; ++ struct drm_wait_vblank_reply reply; ++}; ++ ++#define _DRM_PRE_MODESET 1 ++#define _DRM_POST_MODESET 2 ++ ++/** ++ * DRM_IOCTL_MODESET_CTL ioctl argument type ++ * ++ * \sa drmModesetCtl(). ++ */ ++struct drm_modeset_ctl { ++ __u32 crtc; ++ __u32 cmd; ++}; ++ ++/** ++ * DRM_IOCTL_AGP_ENABLE ioctl argument type. ++ * ++ * \sa drmAgpEnable(). ++ */ ++struct drm_agp_mode { ++ unsigned long mode; /**< AGP mode */ ++}; ++ ++/** ++ * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type. ++ * ++ * \sa drmAgpAlloc() and drmAgpFree(). ++ */ ++struct drm_agp_buffer { ++ unsigned long size; /**< In bytes -- will round to page boundary */ ++ unsigned long handle; /**< Used for binding / unbinding */ ++ unsigned long type; /**< Type of memory to allocate */ ++ unsigned long physical; /**< Physical used by i810 */ ++}; ++ ++/** ++ * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type. ++ * ++ * \sa drmAgpBind() and drmAgpUnbind(). ++ */ ++struct drm_agp_binding { ++ unsigned long handle; /**< From drm_agp_buffer */ ++ unsigned long offset; /**< In bytes -- will round to page boundary */ ++}; ++ ++/** ++ * DRM_IOCTL_AGP_INFO ioctl argument type. ++ * ++ * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(), ++ * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(), ++ * drmAgpVendorId() and drmAgpDeviceId(). ++ */ ++struct drm_agp_info { ++ int agp_version_major; ++ int agp_version_minor; ++ unsigned long mode; ++ unsigned long aperture_base; /* physical address */ ++ unsigned long aperture_size; /* bytes */ ++ unsigned long memory_allowed; /* bytes */ ++ unsigned long memory_used; ++ ++ /* PCI information */ ++ unsigned short id_vendor; ++ unsigned short id_device; ++}; ++ ++/** ++ * DRM_IOCTL_SG_ALLOC ioctl argument type. ++ */ ++struct drm_scatter_gather { ++ unsigned long size; /**< In bytes -- will round to page boundary */ ++ unsigned long handle; /**< Used for mapping / unmapping */ ++}; ++ ++/** ++ * DRM_IOCTL_SET_VERSION ioctl argument type. ++ */ ++struct drm_set_version { ++ int drm_di_major; ++ int drm_di_minor; ++ int drm_dd_major; ++ int drm_dd_minor; ++}; ++ ++/** DRM_IOCTL_GEM_CLOSE ioctl argument type */ ++struct drm_gem_close { ++ /** Handle of the object to be closed. */ ++ __u32 handle; ++ __u32 pad; ++}; ++ ++/** DRM_IOCTL_GEM_FLINK ioctl argument type */ ++struct drm_gem_flink { ++ /** Handle for the object being named */ ++ __u32 handle; ++ ++ /** Returned global name */ ++ __u32 name; ++}; ++ ++/** DRM_IOCTL_GEM_OPEN ioctl argument type */ ++struct drm_gem_open { ++ /** Name of object being opened */ ++ __u32 name; ++ ++ /** Returned handle for the object */ ++ __u32 handle; ++ ++ /** Returned size of the object */ ++ __u64 size; ++}; ++ ++/** DRM_IOCTL_GET_CAP ioctl argument type */ ++struct drm_get_cap { ++ __u64 capability; ++ __u64 value; ++}; ++ ++#define DRM_CLOEXEC O_CLOEXEC ++struct drm_prime_handle { ++ __u32 handle; ++ ++ /** Flags.. only applicable for handle->fd */ ++ __u32 flags; ++ ++ /** Returned dmabuf file descriptor */ ++ __s32 fd; ++}; ++ ++#include "drm_mode.h" ++ ++#define DRM_IOCTL_BASE 'd' ++#define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr) ++#define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type) ++#define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type) ++#define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type) ++ ++#define DRM_IOCTL_VERSION DRM_IOWR(0x00, struct drm_version) ++#define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, struct drm_unique) ++#define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, struct drm_auth) ++#define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, struct drm_irq_busid) ++#define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, struct drm_map) ++#define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, struct drm_client) ++#define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, struct drm_stats) ++#define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, struct drm_set_version) ++#define DRM_IOCTL_MODESET_CTL DRM_IOW(0x08, struct drm_modeset_ctl) ++#define DRM_IOCTL_GEM_CLOSE DRM_IOW (0x09, struct drm_gem_close) ++#define DRM_IOCTL_GEM_FLINK DRM_IOWR(0x0a, struct drm_gem_flink) ++#define DRM_IOCTL_GEM_OPEN DRM_IOWR(0x0b, struct drm_gem_open) ++#define DRM_IOCTL_GET_CAP DRM_IOWR(0x0c, struct drm_get_cap) ++ ++#define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, struct drm_unique) ++#define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, struct drm_auth) ++#define DRM_IOCTL_BLOCK DRM_IOWR(0x12, struct drm_block) ++#define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, struct drm_block) ++#define DRM_IOCTL_CONTROL DRM_IOW( 0x14, struct drm_control) ++#define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, struct drm_map) ++#define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, struct drm_buf_desc) ++#define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, struct drm_buf_desc) ++#define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, struct drm_buf_info) ++#define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, struct drm_buf_map) ++#define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, struct drm_buf_free) ++ ++#define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, struct drm_map) ++ ++#define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, struct drm_ctx_priv_map) ++#define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, struct drm_ctx_priv_map) ++ ++#define DRM_IOCTL_SET_MASTER DRM_IO(0x1e) ++#define DRM_IOCTL_DROP_MASTER DRM_IO(0x1f) ++ ++#define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, struct drm_ctx) ++#define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, struct drm_ctx) ++#define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, struct drm_ctx) ++#define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, struct drm_ctx) ++#define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, struct drm_ctx) ++#define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, struct drm_ctx) ++#define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, struct drm_ctx_res) ++#define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, struct drm_draw) ++#define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, struct drm_draw) ++#define DRM_IOCTL_DMA DRM_IOWR(0x29, struct drm_dma) ++#define DRM_IOCTL_LOCK DRM_IOW( 0x2a, struct drm_lock) ++#define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, struct drm_lock) ++#define DRM_IOCTL_FINISH DRM_IOW( 0x2c, struct drm_lock) ++ ++#define DRM_IOCTL_PRIME_HANDLE_TO_FD DRM_IOWR(0x2d, struct drm_prime_handle) ++#define DRM_IOCTL_PRIME_FD_TO_HANDLE DRM_IOWR(0x2e, struct drm_prime_handle) ++ ++#define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30) ++#define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31) ++#define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, struct drm_agp_mode) ++#define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, struct drm_agp_info) ++#define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, struct drm_agp_buffer) ++#define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, struct drm_agp_buffer) ++#define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, struct drm_agp_binding) ++#define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, struct drm_agp_binding) ++ ++#define DRM_IOCTL_SG_ALLOC DRM_IOWR(0x38, struct drm_scatter_gather) ++#define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, struct drm_scatter_gather) ++ ++#define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank) ++ ++#define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, struct drm_update_draw) ++ ++#define DRM_IOCTL_MODE_GETRESOURCES DRM_IOWR(0xA0, struct drm_mode_card_res) ++#define DRM_IOCTL_MODE_GETCRTC DRM_IOWR(0xA1, struct drm_mode_crtc) ++#define DRM_IOCTL_MODE_SETCRTC DRM_IOWR(0xA2, struct drm_mode_crtc) ++#define DRM_IOCTL_MODE_CURSOR DRM_IOWR(0xA3, struct drm_mode_cursor) ++#define DRM_IOCTL_MODE_GETGAMMA DRM_IOWR(0xA4, struct drm_mode_crtc_lut) ++#define DRM_IOCTL_MODE_SETGAMMA DRM_IOWR(0xA5, struct drm_mode_crtc_lut) ++#define DRM_IOCTL_MODE_GETENCODER DRM_IOWR(0xA6, struct drm_mode_get_encoder) ++#define DRM_IOCTL_MODE_GETCONNECTOR DRM_IOWR(0xA7, struct drm_mode_get_connector) ++#define DRM_IOCTL_MODE_ATTACHMODE DRM_IOWR(0xA8, struct drm_mode_mode_cmd) ++#define DRM_IOCTL_MODE_DETACHMODE DRM_IOWR(0xA9, struct drm_mode_mode_cmd) ++ ++#define DRM_IOCTL_MODE_GETPROPERTY DRM_IOWR(0xAA, struct drm_mode_get_property) ++#define DRM_IOCTL_MODE_SETPROPERTY DRM_IOWR(0xAB, struct drm_mode_connector_set_property) ++#define DRM_IOCTL_MODE_GETPROPBLOB DRM_IOWR(0xAC, struct drm_mode_get_blob) ++#define DRM_IOCTL_MODE_GETFB DRM_IOWR(0xAD, struct drm_mode_fb_cmd) ++#define DRM_IOCTL_MODE_ADDFB DRM_IOWR(0xAE, struct drm_mode_fb_cmd) ++#define DRM_IOCTL_MODE_RMFB DRM_IOWR(0xAF, unsigned int) ++#define DRM_IOCTL_MODE_PAGE_FLIP DRM_IOWR(0xB0, struct drm_mode_crtc_page_flip) ++#define DRM_IOCTL_MODE_DIRTYFB DRM_IOWR(0xB1, struct drm_mode_fb_dirty_cmd) ++ ++#define DRM_IOCTL_MODE_CREATE_DUMB DRM_IOWR(0xB2, struct drm_mode_create_dumb) ++#define DRM_IOCTL_MODE_MAP_DUMB DRM_IOWR(0xB3, struct drm_mode_map_dumb) ++#define DRM_IOCTL_MODE_DESTROY_DUMB DRM_IOWR(0xB4, struct drm_mode_destroy_dumb) ++#define DRM_IOCTL_MODE_GETPLANERESOURCES DRM_IOWR(0xB5, struct drm_mode_get_plane_res) ++#define DRM_IOCTL_MODE_GETPLANE DRM_IOWR(0xB6, struct drm_mode_get_plane) ++#define DRM_IOCTL_MODE_SETPLANE DRM_IOWR(0xB7, struct drm_mode_set_plane) ++#define DRM_IOCTL_MODE_ADDFB2 DRM_IOWR(0xB8, struct drm_mode_fb_cmd2) ++#define DRM_IOCTL_MODE_OBJ_GETPROPERTIES DRM_IOWR(0xB9, struct drm_mode_obj_get_properties) ++#define DRM_IOCTL_MODE_OBJ_SETPROPERTY DRM_IOWR(0xBA, struct drm_mode_obj_set_property) ++ ++/** ++ * Device specific ioctls should only be in their respective headers ++ * The device specific ioctl range is from 0x40 to 0x99. ++ * Generic IOCTLS restart at 0xA0. ++ * ++ * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and ++ * drmCommandReadWrite(). ++ */ ++#define DRM_COMMAND_BASE 0x40 ++#define DRM_COMMAND_END 0xA0 ++ ++/** ++ * Header for events written back to userspace on the drm fd. The ++ * type defines the type of event, the length specifies the total ++ * length of the event (including the header), and user_data is ++ * typically a 64 bit value passed with the ioctl that triggered the ++ * event. A read on the drm fd will always only return complete ++ * events, that is, if for example the read buffer is 100 bytes, and ++ * there are two 64 byte events pending, only one will be returned. ++ * ++ * Event types 0 - 0x7fffffff are generic drm events, 0x80000000 and ++ * up are chipset specific. ++ */ ++struct drm_event { ++ __u32 type; ++ __u32 length; ++}; ++ ++#define DRM_EVENT_VBLANK 0x01 ++#define DRM_EVENT_FLIP_COMPLETE 0x02 ++ ++struct drm_event_vblank { ++ struct drm_event base; ++ __u64 user_data; ++ __u32 tv_sec; ++ __u32 tv_usec; ++ __u32 sequence; ++ __u32 reserved; ++}; ++ ++#define DRM_CAP_DUMB_BUFFER 0x1 ++#define DRM_CAP_VBLANK_HIGH_CRTC 0x2 ++#define DRM_CAP_DUMB_PREFERRED_DEPTH 0x3 ++#define DRM_CAP_DUMB_PREFER_SHADOW 0x4 ++#define DRM_CAP_PRIME 0x5 ++ ++#define DRM_PRIME_CAP_IMPORT 0x1 ++#define DRM_PRIME_CAP_EXPORT 0x2 ++ ++/* typedef area */ ++typedef struct drm_clip_rect drm_clip_rect_t; ++typedef struct drm_drawable_info drm_drawable_info_t; ++typedef struct drm_tex_region drm_tex_region_t; ++typedef struct drm_hw_lock drm_hw_lock_t; ++typedef struct drm_version drm_version_t; ++typedef struct drm_unique drm_unique_t; ++typedef struct drm_list drm_list_t; ++typedef struct drm_block drm_block_t; ++typedef struct drm_control drm_control_t; ++typedef enum drm_map_type drm_map_type_t; ++typedef enum drm_map_flags drm_map_flags_t; ++typedef struct drm_ctx_priv_map drm_ctx_priv_map_t; ++typedef struct drm_map drm_map_t; ++typedef struct drm_client drm_client_t; ++typedef enum drm_stat_type drm_stat_type_t; ++typedef struct drm_stats drm_stats_t; ++typedef enum drm_lock_flags drm_lock_flags_t; ++typedef struct drm_lock drm_lock_t; ++typedef enum drm_dma_flags drm_dma_flags_t; ++typedef struct drm_buf_desc drm_buf_desc_t; ++typedef struct drm_buf_info drm_buf_info_t; ++typedef struct drm_buf_free drm_buf_free_t; ++typedef struct drm_buf_pub drm_buf_pub_t; ++typedef struct drm_buf_map drm_buf_map_t; ++typedef struct drm_dma drm_dma_t; ++typedef union drm_wait_vblank drm_wait_vblank_t; ++typedef struct drm_agp_mode drm_agp_mode_t; ++typedef enum drm_ctx_flags drm_ctx_flags_t; ++typedef struct drm_ctx drm_ctx_t; ++typedef struct drm_ctx_res drm_ctx_res_t; ++typedef struct drm_draw drm_draw_t; ++typedef struct drm_update_draw drm_update_draw_t; ++typedef struct drm_auth drm_auth_t; ++typedef struct drm_irq_busid drm_irq_busid_t; ++typedef enum drm_vblank_seq_type drm_vblank_seq_type_t; ++ ++typedef struct drm_agp_buffer drm_agp_buffer_t; ++typedef struct drm_agp_binding drm_agp_binding_t; ++typedef struct drm_agp_info drm_agp_info_t; ++typedef struct drm_scatter_gather drm_scatter_gather_t; ++typedef struct drm_set_version drm_set_version_t; ++ ++#endif +diff --git a/libc/kernel/common/drm/drm_fourcc.h b/libc/kernel/common/drm/drm_fourcc.h +new file mode 100644 +index 0000000..f462118 +--- /dev/null ++++ b/libc/kernel/common/drm/drm_fourcc.h +@@ -0,0 +1,133 @@ ++/* ++ * Copyright 2011 Intel Corporation ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice (including the next ++ * paragraph) shall be included in all copies or substantial portions of the ++ * Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++#ifndef DRM_FOURCC_H ++#define DRM_FOURCC_H ++ ++#include <linux/types.h> ++ ++#define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \ ++ ((__u32)(c) << 16) | ((__u32)(d) << 24)) ++ ++#define DRM_FORMAT_BIG_ENDIAN (1<<31) /* format is big endian instead of little endian */ ++ ++/* color index */ ++#define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */ ++ ++/* 8 bpp RGB */ ++#define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */ ++#define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */ ++ ++/* 16 bpp RGB */ ++#define DRM_FORMAT_XRGB4444 fourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian */ ++#define DRM_FORMAT_XBGR4444 fourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian */ ++#define DRM_FORMAT_RGBX4444 fourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian */ ++#define DRM_FORMAT_BGRX4444 fourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian */ ++ ++#define DRM_FORMAT_ARGB4444 fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian */ ++#define DRM_FORMAT_ABGR4444 fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian */ ++#define DRM_FORMAT_RGBA4444 fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian */ ++#define DRM_FORMAT_BGRA4444 fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian */ ++ ++#define DRM_FORMAT_XRGB1555 fourcc_code('X', 'R', '1', '5') /* [15:0] x:R:G:B 1:5:5:5 little endian */ ++#define DRM_FORMAT_XBGR1555 fourcc_code('X', 'B', '1', '5') /* [15:0] x:B:G:R 1:5:5:5 little endian */ ++#define DRM_FORMAT_RGBX5551 fourcc_code('R', 'X', '1', '5') /* [15:0] R:G:B:x 5:5:5:1 little endian */ ++#define DRM_FORMAT_BGRX5551 fourcc_code('B', 'X', '1', '5') /* [15:0] B:G:R:x 5:5:5:1 little endian */ ++ ++#define DRM_FORMAT_ARGB1555 fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian */ ++#define DRM_FORMAT_ABGR1555 fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian */ ++#define DRM_FORMAT_RGBA5551 fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian */ ++#define DRM_FORMAT_BGRA5551 fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian */ ++ ++#define DRM_FORMAT_RGB565 fourcc_code('R', 'G', '1', '6') /* [15:0] R:G:B 5:6:5 little endian */ ++#define DRM_FORMAT_BGR565 fourcc_code('B', 'G', '1', '6') /* [15:0] B:G:R 5:6:5 little endian */ ++ ++/* 24 bpp RGB */ ++#define DRM_FORMAT_RGB888 fourcc_code('R', 'G', '2', '4') /* [23:0] R:G:B little endian */ ++#define DRM_FORMAT_BGR888 fourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */ ++ ++/* 32 bpp RGB */ ++#define DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian */ ++#define DRM_FORMAT_XBGR8888 fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian */ ++#define DRM_FORMAT_RGBX8888 fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian */ ++#define DRM_FORMAT_BGRX8888 fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian */ ++ ++#define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian */ ++#define DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian */ ++#define DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian */ ++#define DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian */ ++ ++#define DRM_FORMAT_XRGB2101010 fourcc_code('X', 'R', '3', '0') /* [31:0] x:R:G:B 2:10:10:10 little endian */ ++#define DRM_FORMAT_XBGR2101010 fourcc_code('X', 'B', '3', '0') /* [31:0] x:B:G:R 2:10:10:10 little endian */ ++#define DRM_FORMAT_RGBX1010102 fourcc_code('R', 'X', '3', '0') /* [31:0] R:G:B:x 10:10:10:2 little endian */ ++#define DRM_FORMAT_BGRX1010102 fourcc_code('B', 'X', '3', '0') /* [31:0] B:G:R:x 10:10:10:2 little endian */ ++ ++#define DRM_FORMAT_ARGB2101010 fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little endian */ ++#define DRM_FORMAT_ABGR2101010 fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little endian */ ++#define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */ ++#define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */ ++ ++/* packed YCbCr */ ++#define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */ ++#define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */ ++#define DRM_FORMAT_UYVY fourcc_code('U', 'Y', 'V', 'Y') /* [31:0] Y1:Cr0:Y0:Cb0 8:8:8:8 little endian */ ++#define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */ ++ ++#define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */ ++ ++/* ++ * 2 plane YCbCr ++ * index 0 = Y plane, [7:0] Y ++ * index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian ++ * or ++ * index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian ++ */ ++#define DRM_FORMAT_NV12 fourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */ ++#define DRM_FORMAT_NV21 fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */ ++#define DRM_FORMAT_NV16 fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */ ++#define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */ ++ ++/* special NV12 tiled format */ ++#define DRM_FORMAT_NV12MT fourcc_code('T', 'M', '1', '2') /* 2x2 subsampled Cr:Cb plane 64x32 macroblocks */ ++ ++/* ++ * 3 plane YCbCr ++ * index 0: Y plane, [7:0] Y ++ * index 1: Cb plane, [7:0] Cb ++ * index 2: Cr plane, [7:0] Cr ++ * or ++ * index 1: Cr plane, [7:0] Cr ++ * index 2: Cb plane, [7:0] Cb ++ */ ++#define DRM_FORMAT_YUV410 fourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) planes */ ++#define DRM_FORMAT_YVU410 fourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) planes */ ++#define DRM_FORMAT_YUV411 fourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) planes */ ++#define DRM_FORMAT_YVU411 fourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) planes */ ++#define DRM_FORMAT_YUV420 fourcc_code('Y', 'U', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes */ ++#define DRM_FORMAT_YVU420 fourcc_code('Y', 'V', '1', '2') /* 2x2 subsampled Cr (1) and Cb (2) planes */ ++#define DRM_FORMAT_YUV422 fourcc_code('Y', 'U', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes */ ++#define DRM_FORMAT_YVU422 fourcc_code('Y', 'V', '1', '6') /* 2x1 subsampled Cr (1) and Cb (2) planes */ ++#define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */ ++#define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */ ++ ++#endif /* DRM_FOURCC_H */ +diff --git a/libc/kernel/common/drm/drm_mode.h b/libc/kernel/common/drm/drm_mode.h +new file mode 100644 +index 0000000..3d6301b +--- /dev/null ++++ b/libc/kernel/common/drm/drm_mode.h +@@ -0,0 +1,463 @@ ++/* ++ * Copyright (c) 2007 Dave Airlie <airlied@linux.ie> ++ * Copyright (c) 2007 Jakob Bornecrantz <wallbraker@gmail.com> ++ * Copyright (c) 2008 Red Hat Inc. ++ * Copyright (c) 2007-2008 Tungsten Graphics, Inc., Cedar Park, TX., USA ++ * Copyright (c) 2007-2008 Intel Corporation ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE ++ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER ++ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS ++ * IN THE SOFTWARE. ++ */ ++ ++#ifndef _DRM_MODE_H ++#define _DRM_MODE_H ++ ++#include <linux/types.h> ++ ++#define DRM_DISPLAY_INFO_LEN 32 ++#define DRM_CONNECTOR_NAME_LEN 32 ++#define DRM_DISPLAY_MODE_LEN 32 ++#define DRM_PROP_NAME_LEN 32 ++ ++#define DRM_MODE_TYPE_BUILTIN (1<<0) ++#define DRM_MODE_TYPE_CLOCK_C ((1<<1) | DRM_MODE_TYPE_BUILTIN) ++#define DRM_MODE_TYPE_CRTC_C ((1<<2) | DRM_MODE_TYPE_BUILTIN) ++#define DRM_MODE_TYPE_PREFERRED (1<<3) ++#define DRM_MODE_TYPE_DEFAULT (1<<4) ++#define DRM_MODE_TYPE_USERDEF (1<<5) ++#define DRM_MODE_TYPE_DRIVER (1<<6) ++ ++/* Video mode flags */ ++/* bit compatible with the xorg definitions. */ ++#define DRM_MODE_FLAG_PHSYNC (1<<0) ++#define DRM_MODE_FLAG_NHSYNC (1<<1) ++#define DRM_MODE_FLAG_PVSYNC (1<<2) ++#define DRM_MODE_FLAG_NVSYNC (1<<3) ++#define DRM_MODE_FLAG_INTERLACE (1<<4) ++#define DRM_MODE_FLAG_DBLSCAN (1<<5) ++#define DRM_MODE_FLAG_CSYNC (1<<6) ++#define DRM_MODE_FLAG_PCSYNC (1<<7) ++#define DRM_MODE_FLAG_NCSYNC (1<<8) ++#define DRM_MODE_FLAG_HSKEW (1<<9) /* hskew provided */ ++#define DRM_MODE_FLAG_BCAST (1<<10) ++#define DRM_MODE_FLAG_PIXMUX (1<<11) ++#define DRM_MODE_FLAG_DBLCLK (1<<12) ++#define DRM_MODE_FLAG_CLKDIV2 (1<<13) ++ ++/* DPMS flags */ ++/* bit compatible with the xorg definitions. */ ++#define DRM_MODE_DPMS_ON 0 ++#define DRM_MODE_DPMS_STANDBY 1 ++#define DRM_MODE_DPMS_SUSPEND 2 ++#define DRM_MODE_DPMS_OFF 3 ++ ++/* Scaling mode options */ ++#define DRM_MODE_SCALE_NONE 0 /* Unmodified timing (display or ++ software can still scale) */ ++#define DRM_MODE_SCALE_FULLSCREEN 1 /* Full screen, ignore aspect */ ++#define DRM_MODE_SCALE_CENTER 2 /* Centered, no scaling */ ++#define DRM_MODE_SCALE_ASPECT 3 /* Full screen, preserve aspect */ ++ ++/* Dithering mode options */ ++#define DRM_MODE_DITHERING_OFF 0 ++#define DRM_MODE_DITHERING_ON 1 ++#define DRM_MODE_DITHERING_AUTO 2 ++ ++/* Dirty info options */ ++#define DRM_MODE_DIRTY_OFF 0 ++#define DRM_MODE_DIRTY_ON 1 ++#define DRM_MODE_DIRTY_ANNOTATE 2 ++ ++struct drm_mode_modeinfo { ++ __u32 clock; ++ __u16 hdisplay, hsync_start, hsync_end, htotal, hskew; ++ __u16 vdisplay, vsync_start, vsync_end, vtotal, vscan; ++ ++ __u32 vrefresh; ++ ++ __u32 flags; ++ __u32 type; ++ char name[DRM_DISPLAY_MODE_LEN]; ++}; ++ ++struct drm_mode_card_res { ++ __u64 fb_id_ptr; ++ __u64 crtc_id_ptr; ++ __u64 connector_id_ptr; ++ __u64 encoder_id_ptr; ++ __u32 count_fbs; ++ __u32 count_crtcs; ++ __u32 count_connectors; ++ __u32 count_encoders; ++ __u32 min_width, max_width; ++ __u32 min_height, max_height; ++}; ++ ++struct drm_mode_crtc { ++ __u64 set_connectors_ptr; ++ __u32 count_connectors; ++ ++ __u32 crtc_id; /**< Id */ ++ __u32 fb_id; /**< Id of framebuffer */ ++ ++ __u32 x, y; /**< Position on the frameuffer */ ++ ++ __u32 gamma_size; ++ __u32 mode_valid; ++ struct drm_mode_modeinfo mode; ++}; ++ ++#define DRM_MODE_PRESENT_TOP_FIELD (1<<0) ++#define DRM_MODE_PRESENT_BOTTOM_FIELD (1<<1) ++ ++/* Planes blend with or override other bits on the CRTC */ ++struct drm_mode_set_plane { ++ __u32 plane_id; ++ __u32 crtc_id; ++ __u32 fb_id; /* fb object contains surface format type */ ++ __u32 flags; /* see above flags */ ++ ++ /* Signed dest location allows it to be partially off screen */ ++ __s32 crtc_x, crtc_y; ++ __u32 crtc_w, crtc_h; ++ ++ /* Source values are 16.16 fixed point */ ++ __u32 src_x, src_y; ++ __u32 src_h, src_w; ++}; ++ ++struct drm_mode_get_plane { ++ __u32 plane_id; ++ ++ __u32 crtc_id; ++ __u32 fb_id; ++ ++ __u32 possible_crtcs; ++ __u32 gamma_size; ++ ++ __u32 count_format_types; ++ __u64 format_type_ptr; ++}; ++ ++struct drm_mode_get_plane_res { ++ __u64 plane_id_ptr; ++ __u32 count_planes; ++}; ++ ++#define DRM_MODE_ENCODER_NONE 0 ++#define DRM_MODE_ENCODER_DAC 1 ++#define DRM_MODE_ENCODER_TMDS 2 ++#define DRM_MODE_ENCODER_LVDS 3 ++#define DRM_MODE_ENCODER_TVDAC 4 ++#define DRM_MODE_ENCODER_VIRTUAL 5 ++ ++struct drm_mode_get_encoder { ++ __u32 encoder_id; ++ __u32 encoder_type; ++ ++ __u32 crtc_id; /**< Id of crtc */ ++ ++ __u32 possible_crtcs; ++ __u32 possible_clones; ++}; ++ ++/* This is for connectors with multiple signal types. */ ++/* Try to match DRM_MODE_CONNECTOR_X as closely as possible. */ ++#define DRM_MODE_SUBCONNECTOR_Automatic 0 ++#define DRM_MODE_SUBCONNECTOR_Unknown 0 ++#define DRM_MODE_SUBCONNECTOR_DVID 3 ++#define DRM_MODE_SUBCONNECTOR_DVIA 4 ++#define DRM_MODE_SUBCONNECTOR_Composite 5 ++#define DRM_MODE_SUBCONNECTOR_SVIDEO 6 ++#define DRM_MODE_SUBCONNECTOR_Component 8 ++#define DRM_MODE_SUBCONNECTOR_SCART 9 ++ ++#define DRM_MODE_CONNECTOR_Unknown 0 ++#define DRM_MODE_CONNECTOR_VGA 1 ++#define DRM_MODE_CONNECTOR_DVII 2 ++#define DRM_MODE_CONNECTOR_DVID 3 ++#define DRM_MODE_CONNECTOR_DVIA 4 ++#define DRM_MODE_CONNECTOR_Composite 5 ++#define DRM_MODE_CONNECTOR_SVIDEO 6 ++#define DRM_MODE_CONNECTOR_LVDS 7 ++#define DRM_MODE_CONNECTOR_Component 8 ++#define DRM_MODE_CONNECTOR_9PinDIN 9 ++#define DRM_MODE_CONNECTOR_DisplayPort 10 ++#define DRM_MODE_CONNECTOR_HDMIA 11 ++#define DRM_MODE_CONNECTOR_HDMIB 12 ++#define DRM_MODE_CONNECTOR_TV 13 ++#define DRM_MODE_CONNECTOR_eDP 14 ++#define DRM_MODE_CONNECTOR_VIRTUAL 15 ++ ++struct drm_mode_get_connector { ++ ++ __u64 encoders_ptr; ++ __u64 modes_ptr; ++ __u64 props_ptr; ++ __u64 prop_values_ptr; ++ ++ __u32 count_modes; ++ __u32 count_props; ++ __u32 count_encoders; ++ ++ __u32 encoder_id; /**< Current Encoder */ ++ __u32 connector_id; /**< Id */ ++ __u32 connector_type; ++ __u32 connector_type_id; ++ ++ __u32 connection; ++ __u32 mm_width, mm_height; /**< HxW in millimeters */ ++ __u32 subpixel; ++}; ++ ++#define DRM_MODE_PROP_PENDING (1<<0) ++#define DRM_MODE_PROP_RANGE (1<<1) ++#define DRM_MODE_PROP_IMMUTABLE (1<<2) ++#define DRM_MODE_PROP_ENUM (1<<3) /* enumerated type with text strings */ ++#define DRM_MODE_PROP_BLOB (1<<4) ++#define DRM_MODE_PROP_BITMASK (1<<5) /* bitmask of enumerated types */ ++ ++struct drm_mode_property_enum { ++ __u64 value; ++ char name[DRM_PROP_NAME_LEN]; ++}; ++ ++struct drm_mode_get_property { ++ __u64 values_ptr; /* values and blob lengths */ ++ __u64 enum_blob_ptr; /* enum and blob id ptrs */ ++ ++ __u32 prop_id; ++ __u32 flags; ++ char name[DRM_PROP_NAME_LEN]; ++ ++ __u32 count_values; ++ __u32 count_enum_blobs; ++}; ++ ++struct drm_mode_connector_set_property { ++ __u64 value; ++ __u32 prop_id; ++ __u32 connector_id; ++}; ++ ++struct drm_mode_obj_get_properties { ++ __u64 props_ptr; ++ __u64 prop_values_ptr; ++ __u32 count_props; ++ __u32 obj_id; ++ __u32 obj_type; ++}; ++ ++struct drm_mode_obj_set_property { ++ __u64 value; ++ __u32 prop_id; ++ __u32 obj_id; ++ __u32 obj_type; ++}; ++ ++struct drm_mode_get_blob { ++ __u32 blob_id; ++ __u32 length; ++ __u64 data; ++}; ++ ++struct drm_mode_fb_cmd { ++ __u32 fb_id; ++ __u32 width, height; ++ __u32 pitch; ++ __u32 bpp; ++ __u32 depth; ++ /* driver specific handle */ ++ __u32 handle; ++}; ++ ++#define DRM_MODE_FB_INTERLACED (1<<0) /* for interlaced framebuffers */ ++ ++struct drm_mode_fb_cmd2 { ++ __u32 fb_id; ++ __u32 width, height; ++ __u32 pixel_format; /* fourcc code from drm_fourcc.h */ ++ __u32 flags; /* see above flags */ ++ ++ /* ++ * In case of planar formats, this ioctl allows up to 4 ++ * buffer objects with offets and pitches per plane. ++ * The pitch and offset order is dictated by the fourcc, ++ * e.g. NV12 (http://fourcc.org/yuv.php#NV12) is described as: ++ * ++ * YUV 4:2:0 image with a plane of 8 bit Y samples ++ * followed by an interleaved U/V plane containing ++ * 8 bit 2x2 subsampled colour difference samples. ++ * ++ * So it would consist of Y as offset[0] and UV as ++ * offeset[1]. Note that offset[0] will generally ++ * be 0. ++ */ ++ __u32 handles[4]; ++ __u32 pitches[4]; /* pitch for each plane */ ++ __u32 offsets[4]; /* offset of each plane */ ++}; ++ ++#define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01 ++#define DRM_MODE_FB_DIRTY_ANNOTATE_FILL 0x02 ++#define DRM_MODE_FB_DIRTY_FLAGS 0x03 ++ ++#define DRM_MODE_FB_DIRTY_MAX_CLIPS 256 ++ ++/* ++ * Mark a region of a framebuffer as dirty. ++ * ++ * Some hardware does not automatically update display contents ++ * as a hardware or software draw to a framebuffer. This ioctl ++ * allows userspace to tell the kernel and the hardware what ++ * regions of the framebuffer have changed. ++ * ++ * The kernel or hardware is free to update more then just the ++ * region specified by the clip rects. The kernel or hardware ++ * may also delay and/or coalesce several calls to dirty into a ++ * single update. ++ * ++ * Userspace may annotate the updates, the annotates are a ++ * promise made by the caller that the change is either a copy ++ * of pixels or a fill of a single color in the region specified. ++ * ++ * If the DRM_MODE_FB_DIRTY_ANNOTATE_COPY flag is given then ++ * the number of updated regions are half of num_clips given, ++ * where the clip rects are paired in src and dst. The width and ++ * height of each one of the pairs must match. ++ * ++ * If the DRM_MODE_FB_DIRTY_ANNOTATE_FILL flag is given the caller ++ * promises that the region specified of the clip rects is filled ++ * completely with a single color as given in the color argument. ++ */ ++ ++struct drm_mode_fb_dirty_cmd { ++ __u32 fb_id; ++ __u32 flags; ++ __u32 color; ++ __u32 num_clips; ++ __u64 clips_ptr; ++}; ++ ++struct drm_mode_mode_cmd { ++ __u32 connector_id; ++ struct drm_mode_modeinfo mode; ++}; ++ ++#define DRM_MODE_CURSOR_BO 0x01 ++#define DRM_MODE_CURSOR_MOVE 0x02 ++#define DRM_MODE_CURSOR_FLAGS 0x03 ++ ++/* ++ * depending on the value in flags different members are used. ++ * ++ * CURSOR_BO uses ++ * crtc ++ * width ++ * height ++ * handle - if 0 turns the cursor of ++ * ++ * CURSOR_MOVE uses ++ * crtc ++ * x ++ * y ++ */ ++struct drm_mode_cursor { ++ __u32 flags; ++ __u32 crtc_id; ++ __s32 x; ++ __s32 y; ++ __u32 width; ++ __u32 height; ++ /* driver specific handle */ ++ __u32 handle; ++}; ++ ++struct drm_mode_crtc_lut { ++ __u32 crtc_id; ++ __u32 gamma_size; ++ ++ /* pointers to arrays */ ++ __u64 red; ++ __u64 green; ++ __u64 blue; ++}; ++ ++#define DRM_MODE_PAGE_FLIP_EVENT 0x01 ++#define DRM_MODE_PAGE_FLIP_FLAGS DRM_MODE_PAGE_FLIP_EVENT ++ ++/* ++ * Request a page flip on the specified crtc. ++ * ++ * This ioctl will ask KMS to schedule a page flip for the specified ++ * crtc. Once any pending rendering targeting the specified fb (as of ++ * ioctl time) has completed, the crtc will be reprogrammed to display ++ * that fb after the next vertical refresh. The ioctl returns ++ * immediately, but subsequent rendering to the current fb will block ++ * in the execbuffer ioctl until the page flip happens. If a page ++ * flip is already pending as the ioctl is called, EBUSY will be ++ * returned. ++ * ++ * The ioctl supports one flag, DRM_MODE_PAGE_FLIP_EVENT, which will ++ * request that drm sends back a vblank event (see drm.h: struct ++ * drm_event_vblank) when the page flip is done. The user_data field ++ * passed in with this ioctl will be returned as the user_data field ++ * in the vblank event struct. ++ * ++ * The reserved field must be zero until we figure out something ++ * clever to use it for. ++ */ ++ ++struct drm_mode_crtc_page_flip { ++ __u32 crtc_id; ++ __u32 fb_id; ++ __u32 flags; ++ __u32 reserved; ++ __u64 user_data; ++}; ++ ++/* create a dumb scanout buffer */ ++struct drm_mode_create_dumb { ++ uint32_t height; ++ uint32_t width; ++ uint32_t bpp; ++ uint32_t flags; ++ /* handle, pitch, size will be returned */ ++ uint32_t handle; ++ uint32_t pitch; ++ uint64_t size; ++}; ++ ++/* set up for mmap of a dumb scanout buffer */ ++struct drm_mode_map_dumb { ++ /** Handle for the object being mapped. */ ++ __u32 handle; ++ __u32 pad; ++ /** ++ * Fake offset to use for subsequent mmap call ++ * ++ * This is a fixed-size type for 32/64 compatibility. ++ */ ++ __u64 offset; ++}; ++ ++struct drm_mode_destroy_dumb { ++ uint32_t handle; ++}; ++ ++#endif +diff --git a/libc/kernel/common/drm/drm_sarea.h b/libc/kernel/common/drm/drm_sarea.h +new file mode 100644 +index 0000000..7325558 +--- /dev/null ++++ b/libc/kernel/common/drm/drm_sarea.h +@@ -0,0 +1,82 @@ ++/** ++ * \file drm_sarea.h ++ * \brief SAREA definitions ++ * ++ * \author Michel Dänzer <michel@daenzer.net> ++ */ ++ ++/* ++ * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. ++ * All Rights Reserved. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice (including the next ++ * paragraph) shall be included in all copies or substantial portions of the ++ * Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++#ifndef _DRM_SAREA_H_ ++#define _DRM_SAREA_H_ ++ ++#include "drm.h" ++ ++/* SAREA area needs to be at least a page */ ++#if defined(__alpha__) ++#define SAREA_MAX 0x2000U ++#elif defined(__ia64__) ++#define SAREA_MAX 0x10000U /* 64kB */ ++#else ++/* Intel 830M driver needs at least 8k SAREA */ ++#define SAREA_MAX 0x2000U ++#endif ++ ++/** Maximum number of drawables in the SAREA */ ++#define SAREA_MAX_DRAWABLES 256 ++ ++#define SAREA_DRAWABLE_CLAIMED_ENTRY 0x80000000 ++ ++/** SAREA drawable */ ++struct drm_sarea_drawable { ++ unsigned int stamp; ++ unsigned int flags; ++}; ++ ++/** SAREA frame */ ++struct drm_sarea_frame { ++ unsigned int x; ++ unsigned int y; ++ unsigned int width; ++ unsigned int height; ++ unsigned int fullscreen; ++}; ++ ++/** SAREA */ ++struct drm_sarea { ++ /** first thing is always the DRM locking structure */ ++ struct drm_hw_lock lock; ++ /** \todo Use readers/writer lock for drm_sarea::drawable_lock */ ++ struct drm_hw_lock drawable_lock; ++ struct drm_sarea_drawable drawableTable[SAREA_MAX_DRAWABLES]; /**< drawables */ ++ struct drm_sarea_frame frame; /**< frame */ ++ drm_context_t dummy_context; ++}; ++ ++typedef struct drm_sarea_drawable drm_sarea_drawable_t; ++typedef struct drm_sarea_frame drm_sarea_frame_t; ++typedef struct drm_sarea drm_sarea_t; ++ ++#endif /* _DRM_SAREA_H_ */ +diff --git a/libc/kernel/common/drm/exynos_drm.h b/libc/kernel/common/drm/exynos_drm.h +new file mode 100644 +index 0000000..a2aa0c1 +--- /dev/null ++++ b/libc/kernel/common/drm/exynos_drm.h +@@ -0,0 +1,203 @@ ++/* exynos_drm.h ++ * ++ * Copyright (c) 2011 Samsung Electronics Co., Ltd. ++ * Authors: ++ * Inki Dae <inki.dae@samsung.com> ++ * Joonyoung Shim <jy0922.shim@samsung.com> ++ * Seung-Woo Kim <sw0312.kim@samsung.com> ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice (including the next ++ * paragraph) shall be included in all copies or substantial portions of the ++ * Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++#ifndef _EXYNOS_DRM_H_ ++#define _EXYNOS_DRM_H_ ++ ++#include "drm.h" ++ ++/** ++ * User-desired buffer creation information structure. ++ * ++ * @size: user-desired memory allocation size. ++ * - this size value would be page-aligned internally. ++ * @flags: user request for setting memory type or cache attributes. ++ * @handle: returned a handle to created gem object. ++ * - this handle will be set by gem module of kernel side. ++ */ ++struct drm_exynos_gem_create { ++ uint64_t size; ++ unsigned int flags; ++ unsigned int handle; ++}; ++ ++/** ++ * A structure for getting buffer offset. ++ * ++ * @handle: a pointer to gem object created. ++ * @pad: just padding to be 64-bit aligned. ++ * @offset: relatived offset value of the memory region allocated. ++ * - this value should be set by user. ++ */ ++struct drm_exynos_gem_map_off { ++ unsigned int handle; ++ unsigned int pad; ++ uint64_t offset; ++}; ++ ++/** ++ * A structure for mapping buffer. ++ * ++ * @handle: a handle to gem object created. ++ * @pad: just padding to be 64-bit aligned. ++ * @size: memory size to be mapped. ++ * @mapped: having user virtual address mmaped. ++ * - this variable would be filled by exynos gem module ++ * of kernel side with user virtual address which is allocated ++ * by do_mmap(). ++ */ ++struct drm_exynos_gem_mmap { ++ unsigned int handle; ++ unsigned int pad; ++ uint64_t size; ++ uint64_t mapped; ++}; ++ ++/** ++ * A structure to gem information. ++ * ++ * @handle: a handle to gem object created. ++ * @flags: flag value including memory type and cache attribute and ++ * this value would be set by driver. ++ * @size: size to memory region allocated by gem and this size would ++ * be set by driver. ++ */ ++struct drm_exynos_gem_info { ++ unsigned int handle; ++ unsigned int flags; ++ uint64_t size; ++}; ++ ++/** ++ * A structure for user connection request of virtual display. ++ * ++ * @connection: indicate whether doing connetion or not by user. ++ * @extensions: if this value is 1 then the vidi driver would need additional ++ * 128bytes edid data. ++ * @edid: the edid data pointer from user side. ++ */ ++struct drm_exynos_vidi_connection { ++ unsigned int connection; ++ unsigned int extensions; ++ uint64_t edid; ++}; ++ ++/* memory type definitions. */ ++enum e_drm_exynos_gem_mem_type { ++ /* Physically Continuous memory and used as default. */ ++ EXYNOS_BO_CONTIG = 0 << 0, ++ /* Physically Non-Continuous memory. */ ++ EXYNOS_BO_NONCONTIG = 1 << 0, ++ /* non-cachable mapping and used as default. */ ++ EXYNOS_BO_NONCACHABLE = 0 << 1, ++ /* cachable mapping. */ ++ EXYNOS_BO_CACHABLE = 1 << 1, ++ /* write-combine mapping. */ ++ EXYNOS_BO_WC = 1 << 2, ++ EXYNOS_BO_MASK = EXYNOS_BO_NONCONTIG | EXYNOS_BO_CACHABLE | ++ EXYNOS_BO_WC ++}; ++ ++struct drm_exynos_g2d_get_ver { ++ __u32 major; ++ __u32 minor; ++}; ++ ++struct drm_exynos_g2d_cmd { ++ __u32 offset; ++ __u32 data; ++}; ++ ++enum drm_exynos_g2d_event_type { ++ G2D_EVENT_NOT, ++ G2D_EVENT_NONSTOP, ++ G2D_EVENT_STOP, /* not yet */ ++}; ++ ++struct drm_exynos_g2d_set_cmdlist { ++ __u64 cmd; ++ __u64 cmd_gem; ++ __u32 cmd_nr; ++ __u32 cmd_gem_nr; ++ ++ /* for g2d event */ ++ __u64 event_type; ++ __u64 user_data; ++}; ++ ++struct drm_exynos_g2d_exec { ++ __u64 async; ++}; ++ ++#define DRM_EXYNOS_GEM_CREATE 0x00 ++#define DRM_EXYNOS_GEM_MAP_OFFSET 0x01 ++#define DRM_EXYNOS_GEM_MMAP 0x02 ++/* Reserved 0x03 ~ 0x05 for exynos specific gem ioctl */ ++#define DRM_EXYNOS_GEM_GET 0x04 ++#define DRM_EXYNOS_VIDI_CONNECTION 0x07 ++ ++/* G2D */ ++#define DRM_EXYNOS_G2D_GET_VER 0x20 ++#define DRM_EXYNOS_G2D_SET_CMDLIST 0x21 ++#define DRM_EXYNOS_G2D_EXEC 0x22 ++ ++#define DRM_IOCTL_EXYNOS_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + \ ++ DRM_EXYNOS_GEM_CREATE, struct drm_exynos_gem_create) ++ ++#define DRM_IOCTL_EXYNOS_GEM_MAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + \ ++ DRM_EXYNOS_GEM_MAP_OFFSET, struct drm_exynos_gem_map_off) ++ ++#define DRM_IOCTL_EXYNOS_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + \ ++ DRM_EXYNOS_GEM_MMAP, struct drm_exynos_gem_mmap) ++ ++#define DRM_IOCTL_EXYNOS_GEM_GET DRM_IOWR(DRM_COMMAND_BASE + \ ++ DRM_EXYNOS_GEM_GET, struct drm_exynos_gem_info) ++ ++#define DRM_IOCTL_EXYNOS_VIDI_CONNECTION DRM_IOWR(DRM_COMMAND_BASE + \ ++ DRM_EXYNOS_VIDI_CONNECTION, struct drm_exynos_vidi_connection) ++ ++#define DRM_IOCTL_EXYNOS_G2D_GET_VER DRM_IOWR(DRM_COMMAND_BASE + \ ++ DRM_EXYNOS_G2D_GET_VER, struct drm_exynos_g2d_get_ver) ++#define DRM_IOCTL_EXYNOS_G2D_SET_CMDLIST DRM_IOWR(DRM_COMMAND_BASE + \ ++ DRM_EXYNOS_G2D_SET_CMDLIST, struct drm_exynos_g2d_set_cmdlist) ++#define DRM_IOCTL_EXYNOS_G2D_EXEC DRM_IOWR(DRM_COMMAND_BASE + \ ++ DRM_EXYNOS_G2D_EXEC, struct drm_exynos_g2d_exec) ++ ++/* EXYNOS specific events */ ++#define DRM_EXYNOS_G2D_EVENT 0x80000000 ++ ++struct drm_exynos_g2d_event { ++ struct drm_event base; ++ __u64 user_data; ++ __u32 tv_sec; ++ __u32 tv_usec; ++ __u32 cmdlist_no; ++ __u32 reserved; ++}; ++ ++#endif /* _EXYNOS_DRM_H_ */ +diff --git a/libc/kernel/common/drm/i810_drm.h b/libc/kernel/common/drm/i810_drm.h +new file mode 100644 +index 0000000..7a10bb6 +--- /dev/null ++++ b/libc/kernel/common/drm/i810_drm.h +@@ -0,0 +1,281 @@ ++#ifndef _I810_DRM_H_ ++#define _I810_DRM_H_ ++ ++/* WARNING: These defines must be the same as what the Xserver uses. ++ * if you change them, you must change the defines in the Xserver. ++ */ ++ ++#ifndef _I810_DEFINES_ ++#define _I810_DEFINES_ ++ ++#define I810_DMA_BUF_ORDER 12 ++#define I810_DMA_BUF_SZ (1<<I810_DMA_BUF_ORDER) ++#define I810_DMA_BUF_NR 256 ++#define I810_NR_SAREA_CLIPRECTS 8 ++ ++/* Each region is a minimum of 64k, and there are at most 64 of them. ++ */ ++#define I810_NR_TEX_REGIONS 64 ++#define I810_LOG_MIN_TEX_REGION_SIZE 16 ++#endif ++ ++#define I810_UPLOAD_TEX0IMAGE 0x1 /* handled clientside */ ++#define I810_UPLOAD_TEX1IMAGE 0x2 /* handled clientside */ ++#define I810_UPLOAD_CTX 0x4 ++#define I810_UPLOAD_BUFFERS 0x8 ++#define I810_UPLOAD_TEX0 0x10 ++#define I810_UPLOAD_TEX1 0x20 ++#define I810_UPLOAD_CLIPRECTS 0x40 ++ ++/* Indices into buf.Setup where various bits of state are mirrored per ++ * context and per buffer. These can be fired at the card as a unit, ++ * or in a piecewise fashion as required. ++ */ ++ ++/* Destbuffer state ++ * - backbuffer linear offset and pitch -- invarient in the current dri ++ * - zbuffer linear offset and pitch -- also invarient ++ * - drawing origin in back and depth buffers. ++ * ++ * Keep the depth/back buffer state here to accommodate private buffers ++ * in the future. ++ */ ++#define I810_DESTREG_DI0 0 /* CMD_OP_DESTBUFFER_INFO (2 dwords) */ ++#define I810_DESTREG_DI1 1 ++#define I810_DESTREG_DV0 2 /* GFX_OP_DESTBUFFER_VARS (2 dwords) */ ++#define I810_DESTREG_DV1 3 ++#define I810_DESTREG_DR0 4 /* GFX_OP_DRAWRECT_INFO (4 dwords) */ ++#define I810_DESTREG_DR1 5 ++#define I810_DESTREG_DR2 6 ++#define I810_DESTREG_DR3 7 ++#define I810_DESTREG_DR4 8 ++#define I810_DEST_SETUP_SIZE 10 ++ ++/* Context state ++ */ ++#define I810_CTXREG_CF0 0 /* GFX_OP_COLOR_FACTOR */ ++#define I810_CTXREG_CF1 1 ++#define I810_CTXREG_ST0 2 /* GFX_OP_STIPPLE */ ++#define I810_CTXREG_ST1 3 ++#define I810_CTXREG_VF 4 /* GFX_OP_VERTEX_FMT */ ++#define I810_CTXREG_MT 5 /* GFX_OP_MAP_TEXELS */ ++#define I810_CTXREG_MC0 6 /* GFX_OP_MAP_COLOR_STAGES - stage 0 */ ++#define I810_CTXREG_MC1 7 /* GFX_OP_MAP_COLOR_STAGES - stage 1 */ ++#define I810_CTXREG_MC2 8 /* GFX_OP_MAP_COLOR_STAGES - stage 2 */ ++#define I810_CTXREG_MA0 9 /* GFX_OP_MAP_ALPHA_STAGES - stage 0 */ ++#define I810_CTXREG_MA1 10 /* GFX_OP_MAP_ALPHA_STAGES - stage 1 */ ++#define I810_CTXREG_MA2 11 /* GFX_OP_MAP_ALPHA_STAGES - stage 2 */ ++#define I810_CTXREG_SDM 12 /* GFX_OP_SRC_DEST_MONO */ ++#define I810_CTXREG_FOG 13 /* GFX_OP_FOG_COLOR */ ++#define I810_CTXREG_B1 14 /* GFX_OP_BOOL_1 */ ++#define I810_CTXREG_B2 15 /* GFX_OP_BOOL_2 */ ++#define I810_CTXREG_LCS 16 /* GFX_OP_LINEWIDTH_CULL_SHADE_MODE */ ++#define I810_CTXREG_PV 17 /* GFX_OP_PV_RULE -- Invarient! */ ++#define I810_CTXREG_ZA 18 /* GFX_OP_ZBIAS_ALPHAFUNC */ ++#define I810_CTXREG_AA 19 /* GFX_OP_ANTIALIAS */ ++#define I810_CTX_SETUP_SIZE 20 ++ ++/* Texture state (per tex unit) ++ */ ++#define I810_TEXREG_MI0 0 /* GFX_OP_MAP_INFO (4 dwords) */ ++#define I810_TEXREG_MI1 1 ++#define I810_TEXREG_MI2 2 ++#define I810_TEXREG_MI3 3 ++#define I810_TEXREG_MF 4 /* GFX_OP_MAP_FILTER */ ++#define I810_TEXREG_MLC 5 /* GFX_OP_MAP_LOD_CTL */ ++#define I810_TEXREG_MLL 6 /* GFX_OP_MAP_LOD_LIMITS */ ++#define I810_TEXREG_MCS 7 /* GFX_OP_MAP_COORD_SETS ??? */ ++#define I810_TEX_SETUP_SIZE 8 ++ ++/* Flags for clear ioctl ++ */ ++#define I810_FRONT 0x1 ++#define I810_BACK 0x2 ++#define I810_DEPTH 0x4 ++ ++typedef enum _drm_i810_init_func { ++ I810_INIT_DMA = 0x01, ++ I810_CLEANUP_DMA = 0x02, ++ I810_INIT_DMA_1_4 = 0x03 ++} drm_i810_init_func_t; ++ ++/* This is the init structure after v1.2 */ ++typedef struct _drm_i810_init { ++ drm_i810_init_func_t func; ++ unsigned int mmio_offset; ++ unsigned int buffers_offset; ++ int sarea_priv_offset; ++ unsigned int ring_start; ++ unsigned int ring_end; ++ unsigned int ring_size; ++ unsigned int front_offset; ++ unsigned int back_offset; ++ unsigned int depth_offset; ++ unsigned int overlay_offset; ++ unsigned int overlay_physical; ++ unsigned int w; ++ unsigned int h; ++ unsigned int pitch; ++ unsigned int pitch_bits; ++} drm_i810_init_t; ++ ++/* This is the init structure prior to v1.2 */ ++typedef struct _drm_i810_pre12_init { ++ drm_i810_init_func_t func; ++ unsigned int mmio_offset; ++ unsigned int buffers_offset; ++ int sarea_priv_offset; ++ unsigned int ring_start; ++ unsigned int ring_end; ++ unsigned int ring_size; ++ unsigned int front_offset; ++ unsigned int back_offset; ++ unsigned int depth_offset; ++ unsigned int w; ++ unsigned int h; ++ unsigned int pitch; ++ unsigned int pitch_bits; ++} drm_i810_pre12_init_t; ++ ++/* Warning: If you change the SAREA structure you must change the Xserver ++ * structure as well */ ++ ++typedef struct _drm_i810_tex_region { ++ unsigned char next, prev; /* indices to form a circular LRU */ ++ unsigned char in_use; /* owned by a client, or free? */ ++ int age; /* tracked by clients to update local LRU's */ ++} drm_i810_tex_region_t; ++ ++typedef struct _drm_i810_sarea { ++ unsigned int ContextState[I810_CTX_SETUP_SIZE]; ++ unsigned int BufferState[I810_DEST_SETUP_SIZE]; ++ unsigned int TexState[2][I810_TEX_SETUP_SIZE]; ++ unsigned int dirty; ++ ++ unsigned int nbox; ++ struct drm_clip_rect boxes[I810_NR_SAREA_CLIPRECTS]; ++ ++ /* Maintain an LRU of contiguous regions of texture space. If ++ * you think you own a region of texture memory, and it has an ++ * age different to the one you set, then you are mistaken and ++ * it has been stolen by another client. If global texAge ++ * hasn't changed, there is no need to walk the list. ++ * ++ * These regions can be used as a proxy for the fine-grained ++ * texture information of other clients - by maintaining them ++ * in the same lru which is used to age their own textures, ++ * clients have an approximate lru for the whole of global ++ * texture space, and can make informed decisions as to which ++ * areas to kick out. There is no need to choose whether to ++ * kick out your own texture or someone else's - simply eject ++ * them all in LRU order. ++ */ ++ ++ drm_i810_tex_region_t texList[I810_NR_TEX_REGIONS + 1]; ++ /* Last elt is sentinal */ ++ int texAge; /* last time texture was uploaded */ ++ int last_enqueue; /* last time a buffer was enqueued */ ++ int last_dispatch; /* age of the most recently dispatched buffer */ ++ int last_quiescent; /* */ ++ int ctxOwner; /* last context to upload state */ ++ ++ int vertex_prim; ++ ++ int pf_enabled; /* is pageflipping allowed? */ ++ int pf_active; ++ int pf_current_page; /* which buffer is being displayed? */ ++} drm_i810_sarea_t; ++ ++/* WARNING: If you change any of these defines, make sure to change the ++ * defines in the Xserver file (xf86drmMga.h) ++ */ ++ ++/* i810 specific ioctls ++ * The device specific ioctl range is 0x40 to 0x79. ++ */ ++#define DRM_I810_INIT 0x00 ++#define DRM_I810_VERTEX 0x01 ++#define DRM_I810_CLEAR 0x02 ++#define DRM_I810_FLUSH 0x03 ++#define DRM_I810_GETAGE 0x04 ++#define DRM_I810_GETBUF 0x05 ++#define DRM_I810_SWAP 0x06 ++#define DRM_I810_COPY 0x07 ++#define DRM_I810_DOCOPY 0x08 ++#define DRM_I810_OV0INFO 0x09 ++#define DRM_I810_FSTATUS 0x0a ++#define DRM_I810_OV0FLIP 0x0b ++#define DRM_I810_MC 0x0c ++#define DRM_I810_RSTATUS 0x0d ++#define DRM_I810_FLIP 0x0e ++ ++#define DRM_IOCTL_I810_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I810_INIT, drm_i810_init_t) ++#define DRM_IOCTL_I810_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_I810_VERTEX, drm_i810_vertex_t) ++#define DRM_IOCTL_I810_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_I810_CLEAR, drm_i810_clear_t) ++#define DRM_IOCTL_I810_FLUSH DRM_IO( DRM_COMMAND_BASE + DRM_I810_FLUSH) ++#define DRM_IOCTL_I810_GETAGE DRM_IO( DRM_COMMAND_BASE + DRM_I810_GETAGE) ++#define DRM_IOCTL_I810_GETBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_I810_GETBUF, drm_i810_dma_t) ++#define DRM_IOCTL_I810_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_I810_SWAP) ++#define DRM_IOCTL_I810_COPY DRM_IOW( DRM_COMMAND_BASE + DRM_I810_COPY, drm_i810_copy_t) ++#define DRM_IOCTL_I810_DOCOPY DRM_IO( DRM_COMMAND_BASE + DRM_I810_DOCOPY) ++#define DRM_IOCTL_I810_OV0INFO DRM_IOR( DRM_COMMAND_BASE + DRM_I810_OV0INFO, drm_i810_overlay_t) ++#define DRM_IOCTL_I810_FSTATUS DRM_IO ( DRM_COMMAND_BASE + DRM_I810_FSTATUS) ++#define DRM_IOCTL_I810_OV0FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I810_OV0FLIP) ++#define DRM_IOCTL_I810_MC DRM_IOW( DRM_COMMAND_BASE + DRM_I810_MC, drm_i810_mc_t) ++#define DRM_IOCTL_I810_RSTATUS DRM_IO ( DRM_COMMAND_BASE + DRM_I810_RSTATUS) ++#define DRM_IOCTL_I810_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I810_FLIP) ++ ++typedef struct _drm_i810_clear { ++ int clear_color; ++ int clear_depth; ++ int flags; ++} drm_i810_clear_t; ++ ++/* These may be placeholders if we have more cliprects than ++ * I810_NR_SAREA_CLIPRECTS. In that case, the client sets discard to ++ * false, indicating that the buffer will be dispatched again with a ++ * new set of cliprects. ++ */ ++typedef struct _drm_i810_vertex { ++ int idx; /* buffer index */ ++ int used; /* nr bytes in use */ ++ int discard; /* client is finished with the buffer? */ ++} drm_i810_vertex_t; ++ ++typedef struct _drm_i810_copy_t { ++ int idx; /* buffer index */ ++ int used; /* nr bytes in use */ ++ void *address; /* Address to copy from */ ++} drm_i810_copy_t; ++ ++#define PR_TRIANGLES (0x0<<18) ++#define PR_TRISTRIP_0 (0x1<<18) ++#define PR_TRISTRIP_1 (0x2<<18) ++#define PR_TRIFAN (0x3<<18) ++#define PR_POLYGON (0x4<<18) ++#define PR_LINES (0x5<<18) ++#define PR_LINESTRIP (0x6<<18) ++#define PR_RECTS (0x7<<18) ++#define PR_MASK (0x7<<18) ++ ++typedef struct drm_i810_dma { ++ void *virtual; ++ int request_idx; ++ int request_size; ++ int granted; ++} drm_i810_dma_t; ++ ++typedef struct _drm_i810_overlay_t { ++ unsigned int offset; /* Address of the Overlay Regs */ ++ unsigned int physical; ++} drm_i810_overlay_t; ++ ++typedef struct _drm_i810_mc { ++ int idx; /* buffer index */ ++ int used; /* nr bytes in use */ ++ int num_blocks; /* number of GFXBlocks */ ++ int *length; /* List of lengths for GFXBlocks (FUTURE) */ ++ unsigned int last_render; /* Last Render Request */ ++} drm_i810_mc_t; ++ ++#endif /* _I810_DRM_H_ */ +diff --git a/libc/kernel/common/drm/i915_drm.h b/libc/kernel/common/drm/i915_drm.h +new file mode 100644 +index 0000000..5c8fabe +--- /dev/null ++++ b/libc/kernel/common/drm/i915_drm.h +@@ -0,0 +1,913 @@ ++/* ++ * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. ++ * All Rights Reserved. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the ++ * "Software"), to deal in the Software without restriction, including ++ * without limitation the rights to use, copy, modify, merge, publish, ++ * distribute, sub license, and/or sell copies of the Software, and to ++ * permit persons to whom the Software is furnished to do so, subject to ++ * the following conditions: ++ * ++ * The above copyright notice and this permission notice (including the ++ * next paragraph) shall be included in all copies or substantial portions ++ * of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF ++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ++ * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR ++ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, ++ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE ++ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ * ++ */ ++ ++#ifndef _I915_DRM_H_ ++#define _I915_DRM_H_ ++ ++#include "drm.h" ++ ++/* Please note that modifications to all structs defined here are ++ * subject to backwards-compatibility constraints. ++ */ ++ ++ ++/* Each region is a minimum of 16k, and there are at most 255 of them. ++ */ ++#define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use ++ * of chars for next/prev indices */ ++#define I915_LOG_MIN_TEX_REGION_SIZE 14 ++ ++typedef struct _drm_i915_init { ++ enum { ++ I915_INIT_DMA = 0x01, ++ I915_CLEANUP_DMA = 0x02, ++ I915_RESUME_DMA = 0x03 ++ } func; ++ unsigned int mmio_offset; ++ int sarea_priv_offset; ++ unsigned int ring_start; ++ unsigned int ring_end; ++ unsigned int ring_size; ++ unsigned int front_offset; ++ unsigned int back_offset; ++ unsigned int depth_offset; ++ unsigned int w; ++ unsigned int h; ++ unsigned int pitch; ++ unsigned int pitch_bits; ++ unsigned int back_pitch; ++ unsigned int depth_pitch; ++ unsigned int cpp; ++ unsigned int chipset; ++} drm_i915_init_t; ++ ++typedef struct _drm_i915_sarea { ++ struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; ++ int last_upload; /* last time texture was uploaded */ ++ int last_enqueue; /* last time a buffer was enqueued */ ++ int last_dispatch; /* age of the most recently dispatched buffer */ ++ int ctxOwner; /* last context to upload state */ ++ int texAge; ++ int pf_enabled; /* is pageflipping allowed? */ ++ int pf_active; ++ int pf_current_page; /* which buffer is being displayed? */ ++ int perf_boxes; /* performance boxes to be displayed */ ++ int width, height; /* screen size in pixels */ ++ ++ drm_handle_t front_handle; ++ int front_offset; ++ int front_size; ++ ++ drm_handle_t back_handle; ++ int back_offset; ++ int back_size; ++ ++ drm_handle_t depth_handle; ++ int depth_offset; ++ int depth_size; ++ ++ drm_handle_t tex_handle; ++ int tex_offset; ++ int tex_size; ++ int log_tex_granularity; ++ int pitch; ++ int rotation; /* 0, 90, 180 or 270 */ ++ int rotated_offset; ++ int rotated_size; ++ int rotated_pitch; ++ int virtualX, virtualY; ++ ++ unsigned int front_tiled; ++ unsigned int back_tiled; ++ unsigned int depth_tiled; ++ unsigned int rotated_tiled; ++ unsigned int rotated2_tiled; ++ ++ int pipeA_x; ++ int pipeA_y; ++ int pipeA_w; ++ int pipeA_h; ++ int pipeB_x; ++ int pipeB_y; ++ int pipeB_w; ++ int pipeB_h; ++ ++ /* fill out some space for old userspace triple buffer */ ++ drm_handle_t unused_handle; ++ __u32 unused1, unused2, unused3; ++ ++ /* buffer object handles for static buffers. May change ++ * over the lifetime of the client. ++ */ ++ __u32 front_bo_handle; ++ __u32 back_bo_handle; ++ __u32 unused_bo_handle; ++ __u32 depth_bo_handle; ++ ++} drm_i915_sarea_t; ++ ++/* due to userspace building against these headers we need some compat here */ ++#define planeA_x pipeA_x ++#define planeA_y pipeA_y ++#define planeA_w pipeA_w ++#define planeA_h pipeA_h ++#define planeB_x pipeB_x ++#define planeB_y pipeB_y ++#define planeB_w pipeB_w ++#define planeB_h pipeB_h ++ ++/* Flags for perf_boxes ++ */ ++#define I915_BOX_RING_EMPTY 0x1 ++#define I915_BOX_FLIP 0x2 ++#define I915_BOX_WAIT 0x4 ++#define I915_BOX_TEXTURE_LOAD 0x8 ++#define I915_BOX_LOST_CONTEXT 0x10 ++ ++/* I915 specific ioctls ++ * The device specific ioctl range is 0x40 to 0x79. ++ */ ++#define DRM_I915_INIT 0x00 ++#define DRM_I915_FLUSH 0x01 ++#define DRM_I915_FLIP 0x02 ++#define DRM_I915_BATCHBUFFER 0x03 ++#define DRM_I915_IRQ_EMIT 0x04 ++#define DRM_I915_IRQ_WAIT 0x05 ++#define DRM_I915_GETPARAM 0x06 ++#define DRM_I915_SETPARAM 0x07 ++#define DRM_I915_ALLOC 0x08 ++#define DRM_I915_FREE 0x09 ++#define DRM_I915_INIT_HEAP 0x0a ++#define DRM_I915_CMDBUFFER 0x0b ++#define DRM_I915_DESTROY_HEAP 0x0c ++#define DRM_I915_SET_VBLANK_PIPE 0x0d ++#define DRM_I915_GET_VBLANK_PIPE 0x0e ++#define DRM_I915_VBLANK_SWAP 0x0f ++#define DRM_I915_HWS_ADDR 0x11 ++#define DRM_I915_GEM_INIT 0x13 ++#define DRM_I915_GEM_EXECBUFFER 0x14 ++#define DRM_I915_GEM_PIN 0x15 ++#define DRM_I915_GEM_UNPIN 0x16 ++#define DRM_I915_GEM_BUSY 0x17 ++#define DRM_I915_GEM_THROTTLE 0x18 ++#define DRM_I915_GEM_ENTERVT 0x19 ++#define DRM_I915_GEM_LEAVEVT 0x1a ++#define DRM_I915_GEM_CREATE 0x1b ++#define DRM_I915_GEM_PREAD 0x1c ++#define DRM_I915_GEM_PWRITE 0x1d ++#define DRM_I915_GEM_MMAP 0x1e ++#define DRM_I915_GEM_SET_DOMAIN 0x1f ++#define DRM_I915_GEM_SW_FINISH 0x20 ++#define DRM_I915_GEM_SET_TILING 0x21 ++#define DRM_I915_GEM_GET_TILING 0x22 ++#define DRM_I915_GEM_GET_APERTURE 0x23 ++#define DRM_I915_GEM_MMAP_GTT 0x24 ++#define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 ++#define DRM_I915_GEM_MADVISE 0x26 ++#define DRM_I915_OVERLAY_PUT_IMAGE 0x27 ++#define DRM_I915_OVERLAY_ATTRS 0x28 ++#define DRM_I915_GEM_EXECBUFFER2 0x29 ++#define DRM_I915_GET_SPRITE_COLORKEY 0x2a ++#define DRM_I915_SET_SPRITE_COLORKEY 0x2b ++#define DRM_I915_GEM_WAIT 0x2c ++#define DRM_I915_GEM_CONTEXT_CREATE 0x2d ++#define DRM_I915_GEM_CONTEXT_DESTROY 0x2e ++ ++#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) ++#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) ++#define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP) ++#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) ++#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) ++#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) ++#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) ++#define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) ++#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) ++#define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) ++#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) ++#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) ++#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) ++#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) ++#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) ++#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) ++#define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init) ++#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) ++#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) ++#define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2) ++#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) ++#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) ++#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) ++#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) ++#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) ++#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) ++#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) ++#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) ++#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) ++#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) ++#define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt) ++#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) ++#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) ++#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) ++#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) ++#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) ++#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id) ++#define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) ++#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image) ++#define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) ++#define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) ++#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) ++#define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait) ++#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) ++#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) ++ ++/* Allow drivers to submit batchbuffers directly to hardware, relying ++ * on the security mechanisms provided by hardware. ++ */ ++typedef struct drm_i915_batchbuffer { ++ int start; /* agp offset */ ++ int used; /* nr bytes in use */ ++ int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ ++ int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ ++ int num_cliprects; /* mulitpass with multiple cliprects? */ ++ struct drm_clip_rect *cliprects; /* pointer to userspace cliprects */ ++} drm_i915_batchbuffer_t; ++ ++/* As above, but pass a pointer to userspace buffer which can be ++ * validated by the kernel prior to sending to hardware. ++ */ ++typedef struct _drm_i915_cmdbuffer { ++ char *buf; /* pointer to userspace command buffer */ ++ int sz; /* nr bytes in buf */ ++ int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ ++ int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ ++ int num_cliprects; /* mulitpass with multiple cliprects? */ ++ struct drm_clip_rect *cliprects; /* pointer to userspace cliprects */ ++} drm_i915_cmdbuffer_t; ++ ++/* Userspace can request & wait on irq's: ++ */ ++typedef struct drm_i915_irq_emit { ++ int *irq_seq; ++} drm_i915_irq_emit_t; ++ ++typedef struct drm_i915_irq_wait { ++ int irq_seq; ++} drm_i915_irq_wait_t; ++ ++/* Ioctl to query kernel params: ++ */ ++#define I915_PARAM_IRQ_ACTIVE 1 ++#define I915_PARAM_ALLOW_BATCHBUFFER 2 ++#define I915_PARAM_LAST_DISPATCH 3 ++#define I915_PARAM_CHIPSET_ID 4 ++#define I915_PARAM_HAS_GEM 5 ++#define I915_PARAM_NUM_FENCES_AVAIL 6 ++#define I915_PARAM_HAS_OVERLAY 7 ++#define I915_PARAM_HAS_PAGEFLIPPING 8 ++#define I915_PARAM_HAS_EXECBUF2 9 ++#define I915_PARAM_HAS_BSD 10 ++#define I915_PARAM_HAS_BLT 11 ++#define I915_PARAM_HAS_RELAXED_FENCING 12 ++#define I915_PARAM_HAS_COHERENT_RINGS 13 ++#define I915_PARAM_HAS_EXEC_CONSTANTS 14 ++#define I915_PARAM_HAS_RELAXED_DELTA 15 ++#define I915_PARAM_HAS_GEN7_SOL_RESET 16 ++#define I915_PARAM_HAS_LLC 17 ++#define I915_PARAM_HAS_ALIASING_PPGTT 18 ++#define I915_PARAM_HAS_WAIT_TIMEOUT 19 ++ ++typedef struct drm_i915_getparam { ++ int param; ++ int *value; ++} drm_i915_getparam_t; ++ ++/* Ioctl to set kernel params: ++ */ ++#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 ++#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 ++#define I915_SETPARAM_ALLOW_BATCHBUFFER 3 ++#define I915_SETPARAM_NUM_USED_FENCES 4 ++ ++typedef struct drm_i915_setparam { ++ int param; ++ int value; ++} drm_i915_setparam_t; ++ ++/* A memory manager for regions of shared memory: ++ */ ++#define I915_MEM_REGION_AGP 1 ++ ++typedef struct drm_i915_mem_alloc { ++ int region; ++ int alignment; ++ int size; ++ int *region_offset; /* offset from start of fb or agp */ ++} drm_i915_mem_alloc_t; ++ ++typedef struct drm_i915_mem_free { ++ int region; ++ int region_offset; ++} drm_i915_mem_free_t; ++ ++typedef struct drm_i915_mem_init_heap { ++ int region; ++ int size; ++ int start; ++} drm_i915_mem_init_heap_t; ++ ++/* Allow memory manager to be torn down and re-initialized (eg on ++ * rotate): ++ */ ++typedef struct drm_i915_mem_destroy_heap { ++ int region; ++} drm_i915_mem_destroy_heap_t; ++ ++/* Allow X server to configure which pipes to monitor for vblank signals ++ */ ++#define DRM_I915_VBLANK_PIPE_A 1 ++#define DRM_I915_VBLANK_PIPE_B 2 ++ ++typedef struct drm_i915_vblank_pipe { ++ int pipe; ++} drm_i915_vblank_pipe_t; ++ ++/* Schedule buffer swap at given vertical blank: ++ */ ++typedef struct drm_i915_vblank_swap { ++ drm_drawable_t drawable; ++ enum drm_vblank_seq_type seqtype; ++ unsigned int sequence; ++} drm_i915_vblank_swap_t; ++ ++typedef struct drm_i915_hws_addr { ++ __u64 addr; ++} drm_i915_hws_addr_t; ++ ++struct drm_i915_gem_init { ++ /** ++ * Beginning offset in the GTT to be managed by the DRM memory ++ * manager. ++ */ ++ __u64 gtt_start; ++ /** ++ * Ending offset in the GTT to be managed by the DRM memory ++ * manager. ++ */ ++ __u64 gtt_end; ++}; ++ ++struct drm_i915_gem_create { ++ /** ++ * Requested size for the object. ++ * ++ * The (page-aligned) allocated size for the object will be returned. ++ */ ++ __u64 size; ++ /** ++ * Returned handle for the object. ++ * ++ * Object handles are nonzero. ++ */ ++ __u32 handle; ++ __u32 pad; ++}; ++ ++struct drm_i915_gem_pread { ++ /** Handle for the object being read. */ ++ __u32 handle; ++ __u32 pad; ++ /** Offset into the object to read from */ ++ __u64 offset; ++ /** Length of data to read */ ++ __u64 size; ++ /** ++ * Pointer to write the data into. ++ * ++ * This is a fixed-size type for 32/64 compatibility. ++ */ ++ __u64 data_ptr; ++}; ++ ++struct drm_i915_gem_pwrite { ++ /** Handle for the object being written to. */ ++ __u32 handle; ++ __u32 pad; ++ /** Offset into the object to write to */ ++ __u64 offset; ++ /** Length of data to write */ ++ __u64 size; ++ /** ++ * Pointer to read the data from. ++ * ++ * This is a fixed-size type for 32/64 compatibility. ++ */ ++ __u64 data_ptr; ++}; ++ ++struct drm_i915_gem_mmap { ++ /** Handle for the object being mapped. */ ++ __u32 handle; ++ __u32 pad; ++ /** Offset in the object to map. */ ++ __u64 offset; ++ /** ++ * Length of data to map. ++ * ++ * The value will be page-aligned. ++ */ ++ __u64 size; ++ /** ++ * Returned pointer the data was mapped at. ++ * ++ * This is a fixed-size type for 32/64 compatibility. ++ */ ++ __u64 addr_ptr; ++}; ++ ++struct drm_i915_gem_mmap_gtt { ++ /** Handle for the object being mapped. */ ++ __u32 handle; ++ __u32 pad; ++ /** ++ * Fake offset to use for subsequent mmap call ++ * ++ * This is a fixed-size type for 32/64 compatibility. ++ */ ++ __u64 offset; ++}; ++ ++struct drm_i915_gem_set_domain { ++ /** Handle for the object */ ++ __u32 handle; ++ ++ /** New read domains */ ++ __u32 read_domains; ++ ++ /** New write domain */ ++ __u32 write_domain; ++}; ++ ++struct drm_i915_gem_sw_finish { ++ /** Handle for the object */ ++ __u32 handle; ++}; ++ ++struct drm_i915_gem_relocation_entry { ++ /** ++ * Handle of the buffer being pointed to by this relocation entry. ++ * ++ * It's appealing to make this be an index into the mm_validate_entry ++ * list to refer to the buffer, but this allows the driver to create ++ * a relocation list for state buffers and not re-write it per ++ * exec using the buffer. ++ */ ++ __u32 target_handle; ++ ++ /** ++ * Value to be added to the offset of the target buffer to make up ++ * the relocation entry. ++ */ ++ __u32 delta; ++ ++ /** Offset in the buffer the relocation entry will be written into */ ++ __u64 offset; ++ ++ /** ++ * Offset value of the target buffer that the relocation entry was last ++ * written as. ++ * ++ * If the buffer has the same offset as last time, we can skip syncing ++ * and writing the relocation. This value is written back out by ++ * the execbuffer ioctl when the relocation is written. ++ */ ++ __u64 presumed_offset; ++ ++ /** ++ * Target memory domains read by this operation. ++ */ ++ __u32 read_domains; ++ ++ /** ++ * Target memory domains written by this operation. ++ * ++ * Note that only one domain may be written by the whole ++ * execbuffer operation, so that where there are conflicts, ++ * the application will get -EINVAL back. ++ */ ++ __u32 write_domain; ++}; ++ ++/** @{ ++ * Intel memory domains ++ * ++ * Most of these just align with the various caches in ++ * the system and are used to flush and invalidate as ++ * objects end up cached in different domains. ++ */ ++/** CPU cache */ ++#define I915_GEM_DOMAIN_CPU 0x00000001 ++/** Render cache, used by 2D and 3D drawing */ ++#define I915_GEM_DOMAIN_RENDER 0x00000002 ++/** Sampler cache, used by texture engine */ ++#define I915_GEM_DOMAIN_SAMPLER 0x00000004 ++/** Command queue, used to load batch buffers */ ++#define I915_GEM_DOMAIN_COMMAND 0x00000008 ++/** Instruction cache, used by shader programs */ ++#define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 ++/** Vertex address cache */ ++#define I915_GEM_DOMAIN_VERTEX 0x00000020 ++/** GTT domain - aperture and scanout */ ++#define I915_GEM_DOMAIN_GTT 0x00000040 ++/** @} */ ++ ++struct drm_i915_gem_exec_object { ++ /** ++ * User's handle for a buffer to be bound into the GTT for this ++ * operation. ++ */ ++ __u32 handle; ++ ++ /** Number of relocations to be performed on this buffer */ ++ __u32 relocation_count; ++ /** ++ * Pointer to array of struct drm_i915_gem_relocation_entry containing ++ * the relocations to be performed in this buffer. ++ */ ++ __u64 relocs_ptr; ++ ++ /** Required alignment in graphics aperture */ ++ __u64 alignment; ++ ++ /** ++ * Returned value of the updated offset of the object, for future ++ * presumed_offset writes. ++ */ ++ __u64 offset; ++}; ++ ++struct drm_i915_gem_execbuffer { ++ /** ++ * List of buffers to be validated with their relocations to be ++ * performend on them. ++ * ++ * This is a pointer to an array of struct drm_i915_gem_validate_entry. ++ * ++ * These buffers must be listed in an order such that all relocations ++ * a buffer is performing refer to buffers that have already appeared ++ * in the validate list. ++ */ ++ __u64 buffers_ptr; ++ __u32 buffer_count; ++ ++ /** Offset in the batchbuffer to start execution from. */ ++ __u32 batch_start_offset; ++ /** Bytes used in batchbuffer from batch_start_offset */ ++ __u32 batch_len; ++ __u32 DR1; ++ __u32 DR4; ++ __u32 num_cliprects; ++ /** This is a struct drm_clip_rect *cliprects */ ++ __u64 cliprects_ptr; ++}; ++ ++struct drm_i915_gem_exec_object2 { ++ /** ++ * User's handle for a buffer to be bound into the GTT for this ++ * operation. ++ */ ++ __u32 handle; ++ ++ /** Number of relocations to be performed on this buffer */ ++ __u32 relocation_count; ++ /** ++ * Pointer to array of struct drm_i915_gem_relocation_entry containing ++ * the relocations to be performed in this buffer. ++ */ ++ __u64 relocs_ptr; ++ ++ /** Required alignment in graphics aperture */ ++ __u64 alignment; ++ ++ /** ++ * Returned value of the updated offset of the object, for future ++ * presumed_offset writes. ++ */ ++ __u64 offset; ++ ++#define EXEC_OBJECT_NEEDS_FENCE (1<<0) ++ __u64 flags; ++ __u64 rsvd1; ++ __u64 rsvd2; ++}; ++ ++struct drm_i915_gem_execbuffer2 { ++ /** ++ * List of gem_exec_object2 structs ++ */ ++ __u64 buffers_ptr; ++ __u32 buffer_count; ++ ++ /** Offset in the batchbuffer to start execution from. */ ++ __u32 batch_start_offset; ++ /** Bytes used in batchbuffer from batch_start_offset */ ++ __u32 batch_len; ++ __u32 DR1; ++ __u32 DR4; ++ __u32 num_cliprects; ++ /** This is a struct drm_clip_rect *cliprects */ ++ __u64 cliprects_ptr; ++#define I915_EXEC_RING_MASK (7<<0) ++#define I915_EXEC_DEFAULT (0<<0) ++#define I915_EXEC_RENDER (1<<0) ++#define I915_EXEC_BSD (2<<0) ++#define I915_EXEC_BLT (3<<0) ++ ++/* Used for switching the constants addressing mode on gen4+ RENDER ring. ++ * Gen6+ only supports relative addressing to dynamic state (default) and ++ * absolute addressing. ++ * ++ * These flags are ignored for the BSD and BLT rings. ++ */ ++#define I915_EXEC_CONSTANTS_MASK (3<<6) ++#define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */ ++#define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6) ++#define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */ ++ __u64 flags; ++ __u64 rsvd1; /* now used for context info */ ++ __u64 rsvd2; ++}; ++ ++/** Resets the SO write offset registers for transform feedback on gen7. */ ++#define I915_EXEC_GEN7_SOL_RESET (1<<8) ++ ++#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) ++#define i915_execbuffer2_set_context_id(eb2, context) \ ++ (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK ++#define i915_execbuffer2_get_context_id(eb2) \ ++ ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK) ++ ++struct drm_i915_gem_pin { ++ /** Handle of the buffer to be pinned. */ ++ __u32 handle; ++ __u32 pad; ++ ++ /** alignment required within the aperture */ ++ __u64 alignment; ++ ++ /** Returned GTT offset of the buffer. */ ++ __u64 offset; ++}; ++ ++struct drm_i915_gem_unpin { ++ /** Handle of the buffer to be unpinned. */ ++ __u32 handle; ++ __u32 pad; ++}; ++ ++struct drm_i915_gem_busy { ++ /** Handle of the buffer to check for busy */ ++ __u32 handle; ++ ++ /** Return busy status (1 if busy, 0 if idle) */ ++ __u32 busy; ++}; ++ ++#define I915_TILING_NONE 0 ++#define I915_TILING_X 1 ++#define I915_TILING_Y 2 ++ ++#define I915_BIT_6_SWIZZLE_NONE 0 ++#define I915_BIT_6_SWIZZLE_9 1 ++#define I915_BIT_6_SWIZZLE_9_10 2 ++#define I915_BIT_6_SWIZZLE_9_11 3 ++#define I915_BIT_6_SWIZZLE_9_10_11 4 ++/* Not seen by userland */ ++#define I915_BIT_6_SWIZZLE_UNKNOWN 5 ++/* Seen by userland. */ ++#define I915_BIT_6_SWIZZLE_9_17 6 ++#define I915_BIT_6_SWIZZLE_9_10_17 7 ++ ++struct drm_i915_gem_set_tiling { ++ /** Handle of the buffer to have its tiling state updated */ ++ __u32 handle; ++ ++ /** ++ * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X, ++ * I915_TILING_Y). ++ * ++ * This value is to be set on request, and will be updated by the ++ * kernel on successful return with the actual chosen tiling layout. ++ * ++ * The tiling mode may be demoted to I915_TILING_NONE when the system ++ * has bit 6 swizzling that can't be managed correctly by GEM. ++ * ++ * Buffer contents become undefined when changing tiling_mode. ++ */ ++ __u32 tiling_mode; ++ ++ /** ++ * Stride in bytes for the object when in I915_TILING_X or ++ * I915_TILING_Y. ++ */ ++ __u32 stride; ++ ++ /** ++ * Returned address bit 6 swizzling required for CPU access through ++ * mmap mapping. ++ */ ++ __u32 swizzle_mode; ++}; ++ ++struct drm_i915_gem_get_tiling { ++ /** Handle of the buffer to get tiling state for. */ ++ __u32 handle; ++ ++ /** ++ * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X, ++ * I915_TILING_Y). ++ */ ++ __u32 tiling_mode; ++ ++ /** ++ * Returned address bit 6 swizzling required for CPU access through ++ * mmap mapping. ++ */ ++ __u32 swizzle_mode; ++}; ++ ++struct drm_i915_gem_get_aperture { ++ /** Total size of the aperture used by i915_gem_execbuffer, in bytes */ ++ __u64 aper_size; ++ ++ /** ++ * Available space in the aperture used by i915_gem_execbuffer, in ++ * bytes ++ */ ++ __u64 aper_available_size; ++}; ++ ++struct drm_i915_get_pipe_from_crtc_id { ++ /** ID of CRTC being requested **/ ++ __u32 crtc_id; ++ ++ /** pipe of requested CRTC **/ ++ __u32 pipe; ++}; ++ ++#define I915_MADV_WILLNEED 0 ++#define I915_MADV_DONTNEED 1 ++#define __I915_MADV_PURGED 2 /* internal state */ ++ ++struct drm_i915_gem_madvise { ++ /** Handle of the buffer to change the backing store advice */ ++ __u32 handle; ++ ++ /* Advice: either the buffer will be needed again in the near future, ++ * or wont be and could be discarded under memory pressure. ++ */ ++ __u32 madv; ++ ++ /** Whether the backing store still exists. */ ++ __u32 retained; ++}; ++ ++/* flags */ ++#define I915_OVERLAY_TYPE_MASK 0xff ++#define I915_OVERLAY_YUV_PLANAR 0x01 ++#define I915_OVERLAY_YUV_PACKED 0x02 ++#define I915_OVERLAY_RGB 0x03 ++ ++#define I915_OVERLAY_DEPTH_MASK 0xff00 ++#define I915_OVERLAY_RGB24 0x1000 ++#define I915_OVERLAY_RGB16 0x2000 ++#define I915_OVERLAY_RGB15 0x3000 ++#define I915_OVERLAY_YUV422 0x0100 ++#define I915_OVERLAY_YUV411 0x0200 ++#define I915_OVERLAY_YUV420 0x0300 ++#define I915_OVERLAY_YUV410 0x0400 ++ ++#define I915_OVERLAY_SWAP_MASK 0xff0000 ++#define I915_OVERLAY_NO_SWAP 0x000000 ++#define I915_OVERLAY_UV_SWAP 0x010000 ++#define I915_OVERLAY_Y_SWAP 0x020000 ++#define I915_OVERLAY_Y_AND_UV_SWAP 0x030000 ++ ++#define I915_OVERLAY_FLAGS_MASK 0xff000000 ++#define I915_OVERLAY_ENABLE 0x01000000 ++ ++struct drm_intel_overlay_put_image { ++ /* various flags and src format description */ ++ __u32 flags; ++ /* source picture description */ ++ __u32 bo_handle; ++ /* stride values and offsets are in bytes, buffer relative */ ++ __u16 stride_Y; /* stride for packed formats */ ++ __u16 stride_UV; ++ __u32 offset_Y; /* offset for packet formats */ ++ __u32 offset_U; ++ __u32 offset_V; ++ /* in pixels */ ++ __u16 src_width; ++ __u16 src_height; ++ /* to compensate the scaling factors for partially covered surfaces */ ++ __u16 src_scan_width; ++ __u16 src_scan_height; ++ /* output crtc description */ ++ __u32 crtc_id; ++ __u16 dst_x; ++ __u16 dst_y; ++ __u16 dst_width; ++ __u16 dst_height; ++}; ++ ++/* flags */ ++#define I915_OVERLAY_UPDATE_ATTRS (1<<0) ++#define I915_OVERLAY_UPDATE_GAMMA (1<<1) ++struct drm_intel_overlay_attrs { ++ __u32 flags; ++ __u32 color_key; ++ __s32 brightness; ++ __u32 contrast; ++ __u32 saturation; ++ __u32 gamma0; ++ __u32 gamma1; ++ __u32 gamma2; ++ __u32 gamma3; ++ __u32 gamma4; ++ __u32 gamma5; ++}; ++ ++/* ++ * Intel sprite handling ++ * ++ * Color keying works with a min/mask/max tuple. Both source and destination ++ * color keying is allowed. ++ * ++ * Source keying: ++ * Sprite pixels within the min & max values, masked against the color channels ++ * specified in the mask field, will be transparent. All other pixels will ++ * be displayed on top of the primary plane. For RGB surfaces, only the min ++ * and mask fields will be used; ranged compares are not allowed. ++ * ++ * Destination keying: ++ * Primary plane pixels that match the min value, masked against the color ++ * channels specified in the mask field, will be replaced by corresponding ++ * pixels from the sprite plane. ++ * ++ * Note that source & destination keying are exclusive; only one can be ++ * active on a given plane. ++ */ ++ ++#define I915_SET_COLORKEY_NONE (1<<0) /* disable color key matching */ ++#define I915_SET_COLORKEY_DESTINATION (1<<1) ++#define I915_SET_COLORKEY_SOURCE (1<<2) ++struct drm_intel_sprite_colorkey { ++ __u32 plane_id; ++ __u32 min_value; ++ __u32 channel_mask; ++ __u32 max_value; ++ __u32 flags; ++}; ++ ++struct drm_i915_gem_wait { ++ /** Handle of BO we shall wait on */ ++ __u32 bo_handle; ++ __u32 flags; ++ /** Number of nanoseconds to wait, Returns time remaining. */ ++ __s64 timeout_ns; ++}; ++ ++struct drm_i915_gem_context_create { ++ /* output: id of new context*/ ++ __u32 ctx_id; ++ __u32 pad; ++}; ++ ++struct drm_i915_gem_context_destroy { ++ __u32 ctx_id; ++ __u32 pad; ++}; ++ ++#endif /* _I915_DRM_H_ */ +diff --git a/libc/kernel/common/drm/mga_drm.h b/libc/kernel/common/drm/mga_drm.h +new file mode 100644 +index 0000000..ff812de +--- /dev/null ++++ b/libc/kernel/common/drm/mga_drm.h +@@ -0,0 +1,419 @@ ++/* mga_drm.h -- Public header for the Matrox g200/g400 driver -*- linux-c -*- ++ * Created: Tue Jan 25 01:50:01 1999 by jhartmann@precisioninsight.com ++ * ++ * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. ++ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. ++ * All rights reserved. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice (including the next ++ * paragraph) shall be included in all copies or substantial portions of the ++ * Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ * ++ * Authors: ++ * Jeff Hartmann <jhartmann@valinux.com> ++ * Keith Whitwell <keith@tungstengraphics.com> ++ * ++ * Rewritten by: ++ * Gareth Hughes <gareth@valinux.com> ++ */ ++ ++#ifndef __MGA_DRM_H__ ++#define __MGA_DRM_H__ ++ ++#include "drm.h" ++ ++/* WARNING: If you change any of these defines, make sure to change the ++ * defines in the Xserver file (mga_sarea.h) ++ */ ++ ++#ifndef __MGA_SAREA_DEFINES__ ++#define __MGA_SAREA_DEFINES__ ++ ++/* WARP pipe flags ++ */ ++#define MGA_F 0x1 /* fog */ ++#define MGA_A 0x2 /* alpha */ ++#define MGA_S 0x4 /* specular */ ++#define MGA_T2 0x8 /* multitexture */ ++ ++#define MGA_WARP_TGZ 0 ++#define MGA_WARP_TGZF (MGA_F) ++#define MGA_WARP_TGZA (MGA_A) ++#define MGA_WARP_TGZAF (MGA_F|MGA_A) ++#define MGA_WARP_TGZS (MGA_S) ++#define MGA_WARP_TGZSF (MGA_S|MGA_F) ++#define MGA_WARP_TGZSA (MGA_S|MGA_A) ++#define MGA_WARP_TGZSAF (MGA_S|MGA_F|MGA_A) ++#define MGA_WARP_T2GZ (MGA_T2) ++#define MGA_WARP_T2GZF (MGA_T2|MGA_F) ++#define MGA_WARP_T2GZA (MGA_T2|MGA_A) ++#define MGA_WARP_T2GZAF (MGA_T2|MGA_A|MGA_F) ++#define MGA_WARP_T2GZS (MGA_T2|MGA_S) ++#define MGA_WARP_T2GZSF (MGA_T2|MGA_S|MGA_F) ++#define MGA_WARP_T2GZSA (MGA_T2|MGA_S|MGA_A) ++#define MGA_WARP_T2GZSAF (MGA_T2|MGA_S|MGA_F|MGA_A) ++ ++#define MGA_MAX_G200_PIPES 8 /* no multitex */ ++#define MGA_MAX_G400_PIPES 16 ++#define MGA_MAX_WARP_PIPES MGA_MAX_G400_PIPES ++#define MGA_WARP_UCODE_SIZE 32768 /* in bytes */ ++ ++#define MGA_CARD_TYPE_G200 1 ++#define MGA_CARD_TYPE_G400 2 ++#define MGA_CARD_TYPE_G450 3 /* not currently used */ ++#define MGA_CARD_TYPE_G550 4 ++ ++#define MGA_FRONT 0x1 ++#define MGA_BACK 0x2 ++#define MGA_DEPTH 0x4 ++ ++/* What needs to be changed for the current vertex dma buffer? ++ */ ++#define MGA_UPLOAD_CONTEXT 0x1 ++#define MGA_UPLOAD_TEX0 0x2 ++#define MGA_UPLOAD_TEX1 0x4 ++#define MGA_UPLOAD_PIPE 0x8 ++#define MGA_UPLOAD_TEX0IMAGE 0x10 /* handled client-side */ ++#define MGA_UPLOAD_TEX1IMAGE 0x20 /* handled client-side */ ++#define MGA_UPLOAD_2D 0x40 ++#define MGA_WAIT_AGE 0x80 /* handled client-side */ ++#define MGA_UPLOAD_CLIPRECTS 0x100 /* handled client-side */ ++#if 0 ++#define MGA_DMA_FLUSH 0x200 /* set when someone gets the lock ++ quiescent */ ++#endif ++ ++/* 32 buffers of 64k each, total 2 meg. ++ */ ++#define MGA_BUFFER_SIZE (1 << 16) ++#define MGA_NUM_BUFFERS 128 ++ ++/* Keep these small for testing. ++ */ ++#define MGA_NR_SAREA_CLIPRECTS 8 ++ ++/* 2 heaps (1 for card, 1 for agp), each divided into up to 128 ++ * regions, subject to a minimum region size of (1<<16) == 64k. ++ * ++ * Clients may subdivide regions internally, but when sharing between ++ * clients, the region size is the minimum granularity. ++ */ ++ ++#define MGA_CARD_HEAP 0 ++#define MGA_AGP_HEAP 1 ++#define MGA_NR_TEX_HEAPS 2 ++#define MGA_NR_TEX_REGIONS 16 ++#define MGA_LOG_MIN_TEX_REGION_SIZE 16 ++ ++#define DRM_MGA_IDLE_RETRY 2048 ++ ++#endif /* __MGA_SAREA_DEFINES__ */ ++ ++/* Setup registers for 3D context ++ */ ++typedef struct { ++ unsigned int dstorg; ++ unsigned int maccess; ++ unsigned int plnwt; ++ unsigned int dwgctl; ++ unsigned int alphactrl; ++ unsigned int fogcolor; ++ unsigned int wflag; ++ unsigned int tdualstage0; ++ unsigned int tdualstage1; ++ unsigned int fcol; ++ unsigned int stencil; ++ unsigned int stencilctl; ++} drm_mga_context_regs_t; ++ ++/* Setup registers for 2D, X server ++ */ ++typedef struct { ++ unsigned int pitch; ++} drm_mga_server_regs_t; ++ ++/* Setup registers for each texture unit ++ */ ++typedef struct { ++ unsigned int texctl; ++ unsigned int texctl2; ++ unsigned int texfilter; ++ unsigned int texbordercol; ++ unsigned int texorg; ++ unsigned int texwidth; ++ unsigned int texheight; ++ unsigned int texorg1; ++ unsigned int texorg2; ++ unsigned int texorg3; ++ unsigned int texorg4; ++} drm_mga_texture_regs_t; ++ ++/* General aging mechanism ++ */ ++typedef struct { ++ unsigned int head; /* Position of head pointer */ ++ unsigned int wrap; /* Primary DMA wrap count */ ++} drm_mga_age_t; ++ ++typedef struct _drm_mga_sarea { ++ /* The channel for communication of state information to the kernel ++ * on firing a vertex dma buffer. ++ */ ++ drm_mga_context_regs_t context_state; ++ drm_mga_server_regs_t server_state; ++ drm_mga_texture_regs_t tex_state[2]; ++ unsigned int warp_pipe; ++ unsigned int dirty; ++ unsigned int vertsize; ++ ++ /* The current cliprects, or a subset thereof. ++ */ ++ struct drm_clip_rect boxes[MGA_NR_SAREA_CLIPRECTS]; ++ unsigned int nbox; ++ ++ /* Information about the most recently used 3d drawable. The ++ * client fills in the req_* fields, the server fills in the ++ * exported_ fields and puts the cliprects into boxes, above. ++ * ++ * The client clears the exported_drawable field before ++ * clobbering the boxes data. ++ */ ++ unsigned int req_drawable; /* the X drawable id */ ++ unsigned int req_draw_buffer; /* MGA_FRONT or MGA_BACK */ ++ ++ unsigned int exported_drawable; ++ unsigned int exported_index; ++ unsigned int exported_stamp; ++ unsigned int exported_buffers; ++ unsigned int exported_nfront; ++ unsigned int exported_nback; ++ int exported_back_x, exported_front_x, exported_w; ++ int exported_back_y, exported_front_y, exported_h; ++ struct drm_clip_rect exported_boxes[MGA_NR_SAREA_CLIPRECTS]; ++ ++ /* Counters for aging textures and for client-side throttling. ++ */ ++ unsigned int status[4]; ++ unsigned int last_wrap; ++ ++ drm_mga_age_t last_frame; ++ unsigned int last_enqueue; /* last time a buffer was enqueued */ ++ unsigned int last_dispatch; /* age of the most recently dispatched buffer */ ++ unsigned int last_quiescent; /* */ ++ ++ /* LRU lists for texture memory in agp space and on the card. ++ */ ++ struct drm_tex_region texList[MGA_NR_TEX_HEAPS][MGA_NR_TEX_REGIONS + 1]; ++ unsigned int texAge[MGA_NR_TEX_HEAPS]; ++ ++ /* Mechanism to validate card state. ++ */ ++ int ctxOwner; ++} drm_mga_sarea_t; ++ ++/* MGA specific ioctls ++ * The device specific ioctl range is 0x40 to 0x79. ++ */ ++#define DRM_MGA_INIT 0x00 ++#define DRM_MGA_FLUSH 0x01 ++#define DRM_MGA_RESET 0x02 ++#define DRM_MGA_SWAP 0x03 ++#define DRM_MGA_CLEAR 0x04 ++#define DRM_MGA_VERTEX 0x05 ++#define DRM_MGA_INDICES 0x06 ++#define DRM_MGA_ILOAD 0x07 ++#define DRM_MGA_BLIT 0x08 ++#define DRM_MGA_GETPARAM 0x09 ++ ++/* 3.2: ++ * ioctls for operating on fences. ++ */ ++#define DRM_MGA_SET_FENCE 0x0a ++#define DRM_MGA_WAIT_FENCE 0x0b ++#define DRM_MGA_DMA_BOOTSTRAP 0x0c ++ ++#define DRM_IOCTL_MGA_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INIT, drm_mga_init_t) ++#define DRM_IOCTL_MGA_FLUSH DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_FLUSH, struct drm_lock) ++#define DRM_IOCTL_MGA_RESET DRM_IO( DRM_COMMAND_BASE + DRM_MGA_RESET) ++#define DRM_IOCTL_MGA_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_MGA_SWAP) ++#define DRM_IOCTL_MGA_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_CLEAR, drm_mga_clear_t) ++#define DRM_IOCTL_MGA_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_VERTEX, drm_mga_vertex_t) ++#define DRM_IOCTL_MGA_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INDICES, drm_mga_indices_t) ++#define DRM_IOCTL_MGA_ILOAD DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_ILOAD, drm_mga_iload_t) ++#define DRM_IOCTL_MGA_BLIT DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_BLIT, drm_mga_blit_t) ++#define DRM_IOCTL_MGA_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_GETPARAM, drm_mga_getparam_t) ++#define DRM_IOCTL_MGA_SET_FENCE DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_SET_FENCE, __u32) ++#define DRM_IOCTL_MGA_WAIT_FENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_WAIT_FENCE, __u32) ++#define DRM_IOCTL_MGA_DMA_BOOTSTRAP DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_DMA_BOOTSTRAP, drm_mga_dma_bootstrap_t) ++ ++typedef struct _drm_mga_warp_index { ++ int installed; ++ unsigned long phys_addr; ++ int size; ++} drm_mga_warp_index_t; ++ ++typedef struct drm_mga_init { ++ enum { ++ MGA_INIT_DMA = 0x01, ++ MGA_CLEANUP_DMA = 0x02 ++ } func; ++ ++ unsigned long sarea_priv_offset; ++ ++ int chipset; ++ int sgram; ++ ++ unsigned int maccess; ++ ++ unsigned int fb_cpp; ++ unsigned int front_offset, front_pitch; ++ unsigned int back_offset, back_pitch; ++ ++ unsigned int depth_cpp; ++ unsigned int depth_offset, depth_pitch; ++ ++ unsigned int texture_offset[MGA_NR_TEX_HEAPS]; ++ unsigned int texture_size[MGA_NR_TEX_HEAPS]; ++ ++ unsigned long fb_offset; ++ unsigned long mmio_offset; ++ unsigned long status_offset; ++ unsigned long warp_offset; ++ unsigned long primary_offset; ++ unsigned long buffers_offset; ++} drm_mga_init_t; ++ ++typedef struct drm_mga_dma_bootstrap { ++ /** ++ * \name AGP texture region ++ * ++ * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, these fields will ++ * be filled in with the actual AGP texture settings. ++ * ++ * \warning ++ * If these fields are non-zero, but dma_mga_dma_bootstrap::agp_mode ++ * is zero, it means that PCI memory (most likely through the use of ++ * an IOMMU) is being used for "AGP" textures. ++ */ ++ /*@{ */ ++ unsigned long texture_handle; /**< Handle used to map AGP textures. */ ++ __u32 texture_size; /**< Size of the AGP texture region. */ ++ /*@} */ ++ ++ /** ++ * Requested size of the primary DMA region. ++ * ++ * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be ++ * filled in with the actual AGP mode. If AGP was not available ++ */ ++ __u32 primary_size; ++ ++ /** ++ * Requested number of secondary DMA buffers. ++ * ++ * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be ++ * filled in with the actual number of secondary DMA buffers ++ * allocated. Particularly when PCI DMA is used, this may be ++ * (subtantially) less than the number requested. ++ */ ++ __u32 secondary_bin_count; ++ ++ /** ++ * Requested size of each secondary DMA buffer. ++ * ++ * While the kernel \b is free to reduce ++ * dma_mga_dma_bootstrap::secondary_bin_count, it is \b not allowed ++ * to reduce dma_mga_dma_bootstrap::secondary_bin_size. ++ */ ++ __u32 secondary_bin_size; ++ ++ /** ++ * Bit-wise mask of AGPSTAT2_* values. Currently only \c AGPSTAT2_1X, ++ * \c AGPSTAT2_2X, and \c AGPSTAT2_4X are supported. If this value is ++ * zero, it means that PCI DMA should be used, even if AGP is ++ * possible. ++ * ++ * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be ++ * filled in with the actual AGP mode. If AGP was not available ++ * (i.e., PCI DMA was used), this value will be zero. ++ */ ++ __u32 agp_mode; ++ ++ /** ++ * Desired AGP GART size, measured in megabytes. ++ */ ++ __u8 agp_size; ++} drm_mga_dma_bootstrap_t; ++ ++typedef struct drm_mga_clear { ++ unsigned int flags; ++ unsigned int clear_color; ++ unsigned int clear_depth; ++ unsigned int color_mask; ++ unsigned int depth_mask; ++} drm_mga_clear_t; ++ ++typedef struct drm_mga_vertex { ++ int idx; /* buffer to queue */ ++ int used; /* bytes in use */ ++ int discard; /* client finished with buffer? */ ++} drm_mga_vertex_t; ++ ++typedef struct drm_mga_indices { ++ int idx; /* buffer to queue */ ++ unsigned int start; ++ unsigned int end; ++ int discard; /* client finished with buffer? */ ++} drm_mga_indices_t; ++ ++typedef struct drm_mga_iload { ++ int idx; ++ unsigned int dstorg; ++ unsigned int length; ++} drm_mga_iload_t; ++ ++typedef struct _drm_mga_blit { ++ unsigned int planemask; ++ unsigned int srcorg; ++ unsigned int dstorg; ++ int src_pitch, dst_pitch; ++ int delta_sx, delta_sy; ++ int delta_dx, delta_dy; ++ int height, ydir; /* flip image vertically */ ++ int source_pitch, dest_pitch; ++} drm_mga_blit_t; ++ ++/* 3.1: An ioctl to get parameters that aren't available to the 3d ++ * client any other way. ++ */ ++#define MGA_PARAM_IRQ_NR 1 ++ ++/* 3.2: Query the actual card type. The DDX only distinguishes between ++ * G200 chips and non-G200 chips, which it calls G400. It turns out that ++ * there are some very sublte differences between the G4x0 chips and the G550 ++ * chips. Using this parameter query, a client-side driver can detect the ++ * difference between a G4x0 and a G550. ++ */ ++#define MGA_PARAM_CARD_TYPE 2 ++ ++typedef struct drm_mga_getparam { ++ int param; ++ void *value; ++} drm_mga_getparam_t; ++ ++#endif +diff --git a/libc/kernel/common/drm/nouveau_drm.h b/libc/kernel/common/drm/nouveau_drm.h +new file mode 100644 +index 0000000..2a5769f +--- /dev/null ++++ b/libc/kernel/common/drm/nouveau_drm.h +@@ -0,0 +1,138 @@ ++/* ++ * Copyright 2005 Stephane Marchesin. ++ * All Rights Reserved. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice (including the next ++ * paragraph) shall be included in all copies or substantial portions of the ++ * Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++#ifndef __NOUVEAU_DRM_H__ ++#define __NOUVEAU_DRM_H__ ++ ++#define NOUVEAU_GEM_DOMAIN_CPU (1 << 0) ++#define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1) ++#define NOUVEAU_GEM_DOMAIN_GART (1 << 2) ++#define NOUVEAU_GEM_DOMAIN_MAPPABLE (1 << 3) ++ ++#define NOUVEAU_GEM_TILE_COMP 0x00030000 /* nv50-only */ ++#define NOUVEAU_GEM_TILE_LAYOUT_MASK 0x0000ff00 ++#define NOUVEAU_GEM_TILE_16BPP 0x00000001 ++#define NOUVEAU_GEM_TILE_32BPP 0x00000002 ++#define NOUVEAU_GEM_TILE_ZETA 0x00000004 ++#define NOUVEAU_GEM_TILE_NONCONTIG 0x00000008 ++ ++struct drm_nouveau_gem_info { ++ uint32_t handle; ++ uint32_t domain; ++ uint64_t size; ++ uint64_t offset; ++ uint64_t map_handle; ++ uint32_t tile_mode; ++ uint32_t tile_flags; ++}; ++ ++struct drm_nouveau_gem_new { ++ struct drm_nouveau_gem_info info; ++ uint32_t channel_hint; ++ uint32_t align; ++}; ++ ++#define NOUVEAU_GEM_MAX_BUFFERS 1024 ++struct drm_nouveau_gem_pushbuf_bo_presumed { ++ uint32_t valid; ++ uint32_t domain; ++ uint64_t offset; ++}; ++ ++struct drm_nouveau_gem_pushbuf_bo { ++ uint64_t user_priv; ++ uint32_t handle; ++ uint32_t read_domains; ++ uint32_t write_domains; ++ uint32_t valid_domains; ++ struct drm_nouveau_gem_pushbuf_bo_presumed presumed; ++}; ++ ++#define NOUVEAU_GEM_RELOC_LOW (1 << 0) ++#define NOUVEAU_GEM_RELOC_HIGH (1 << 1) ++#define NOUVEAU_GEM_RELOC_OR (1 << 2) ++#define NOUVEAU_GEM_MAX_RELOCS 1024 ++struct drm_nouveau_gem_pushbuf_reloc { ++ uint32_t reloc_bo_index; ++ uint32_t reloc_bo_offset; ++ uint32_t bo_index; ++ uint32_t flags; ++ uint32_t data; ++ uint32_t vor; ++ uint32_t tor; ++}; ++ ++#define NOUVEAU_GEM_MAX_PUSH 512 ++struct drm_nouveau_gem_pushbuf_push { ++ uint32_t bo_index; ++ uint32_t pad; ++ uint64_t offset; ++ uint64_t length; ++}; ++ ++struct drm_nouveau_gem_pushbuf { ++ uint32_t channel; ++ uint32_t nr_buffers; ++ uint64_t buffers; ++ uint32_t nr_relocs; ++ uint32_t nr_push; ++ uint64_t relocs; ++ uint64_t push; ++ uint32_t suffix0; ++ uint32_t suffix1; ++ uint64_t vram_available; ++ uint64_t gart_available; ++}; ++ ++#define NOUVEAU_GEM_CPU_PREP_NOWAIT 0x00000001 ++#define NOUVEAU_GEM_CPU_PREP_WRITE 0x00000004 ++struct drm_nouveau_gem_cpu_prep { ++ uint32_t handle; ++ uint32_t flags; ++}; ++ ++struct drm_nouveau_gem_cpu_fini { ++ uint32_t handle; ++}; ++ ++#define DRM_NOUVEAU_GETPARAM 0x00 /* deprecated */ ++#define DRM_NOUVEAU_SETPARAM 0x01 /* deprecated */ ++#define DRM_NOUVEAU_CHANNEL_ALLOC 0x02 /* deprecated */ ++#define DRM_NOUVEAU_CHANNEL_FREE 0x03 /* deprecated */ ++#define DRM_NOUVEAU_GROBJ_ALLOC 0x04 /* deprecated */ ++#define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x05 /* deprecated */ ++#define DRM_NOUVEAU_GPUOBJ_FREE 0x06 /* deprecated */ ++#define DRM_NOUVEAU_GEM_NEW 0x40 ++#define DRM_NOUVEAU_GEM_PUSHBUF 0x41 ++#define DRM_NOUVEAU_GEM_CPU_PREP 0x42 ++#define DRM_NOUVEAU_GEM_CPU_FINI 0x43 ++#define DRM_NOUVEAU_GEM_INFO 0x44 ++ ++#define DRM_IOCTL_NOUVEAU_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_NEW, struct drm_nouveau_gem_new) ++#define DRM_IOCTL_NOUVEAU_GEM_PUSHBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_PUSHBUF, struct drm_nouveau_gem_pushbuf) ++#define DRM_IOCTL_NOUVEAU_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_PREP, struct drm_nouveau_gem_cpu_prep) ++#define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, struct drm_nouveau_gem_cpu_fini) ++#define DRM_IOCTL_NOUVEAU_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_INFO, struct drm_nouveau_gem_info) ++ ++#endif /* __NOUVEAU_DRM_H__ */ +diff --git a/libc/kernel/common/drm/r128_drm.h b/libc/kernel/common/drm/r128_drm.h +new file mode 100644 +index 0000000..ede78ff +--- /dev/null ++++ b/libc/kernel/common/drm/r128_drm.h +@@ -0,0 +1,326 @@ ++/* r128_drm.h -- Public header for the r128 driver -*- linux-c -*- ++ * Created: Wed Apr 5 19:24:19 2000 by kevin@precisioninsight.com ++ */ ++/* ++ * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. ++ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. ++ * All rights reserved. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice (including the next ++ * paragraph) shall be included in all copies or substantial portions of the ++ * Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER ++ * DEALINGS IN THE SOFTWARE. ++ * ++ * Authors: ++ * Gareth Hughes <gareth@valinux.com> ++ * Kevin E. Martin <martin@valinux.com> ++ */ ++ ++#ifndef __R128_DRM_H__ ++#define __R128_DRM_H__ ++ ++/* WARNING: If you change any of these defines, make sure to change the ++ * defines in the X server file (r128_sarea.h) ++ */ ++#ifndef __R128_SAREA_DEFINES__ ++#define __R128_SAREA_DEFINES__ ++ ++/* What needs to be changed for the current vertex buffer? ++ */ ++#define R128_UPLOAD_CONTEXT 0x001 ++#define R128_UPLOAD_SETUP 0x002 ++#define R128_UPLOAD_TEX0 0x004 ++#define R128_UPLOAD_TEX1 0x008 ++#define R128_UPLOAD_TEX0IMAGES 0x010 ++#define R128_UPLOAD_TEX1IMAGES 0x020 ++#define R128_UPLOAD_CORE 0x040 ++#define R128_UPLOAD_MASKS 0x080 ++#define R128_UPLOAD_WINDOW 0x100 ++#define R128_UPLOAD_CLIPRECTS 0x200 /* handled client-side */ ++#define R128_REQUIRE_QUIESCENCE 0x400 ++#define R128_UPLOAD_ALL 0x7ff ++ ++#define R128_FRONT 0x1 ++#define R128_BACK 0x2 ++#define R128_DEPTH 0x4 ++ ++/* Primitive types ++ */ ++#define R128_POINTS 0x1 ++#define R128_LINES 0x2 ++#define R128_LINE_STRIP 0x3 ++#define R128_TRIANGLES 0x4 ++#define R128_TRIANGLE_FAN 0x5 ++#define R128_TRIANGLE_STRIP 0x6 ++ ++/* Vertex/indirect buffer size ++ */ ++#define R128_BUFFER_SIZE 16384 ++ ++/* Byte offsets for indirect buffer data ++ */ ++#define R128_INDEX_PRIM_OFFSET 20 ++#define R128_HOSTDATA_BLIT_OFFSET 32 ++ ++/* Keep these small for testing. ++ */ ++#define R128_NR_SAREA_CLIPRECTS 12 ++ ++/* There are 2 heaps (local/AGP). Each region within a heap is a ++ * minimum of 64k, and there are at most 64 of them per heap. ++ */ ++#define R128_LOCAL_TEX_HEAP 0 ++#define R128_AGP_TEX_HEAP 1 ++#define R128_NR_TEX_HEAPS 2 ++#define R128_NR_TEX_REGIONS 64 ++#define R128_LOG_TEX_GRANULARITY 16 ++ ++#define R128_NR_CONTEXT_REGS 12 ++ ++#define R128_MAX_TEXTURE_LEVELS 11 ++#define R128_MAX_TEXTURE_UNITS 2 ++ ++#endif /* __R128_SAREA_DEFINES__ */ ++ ++typedef struct { ++ /* Context state - can be written in one large chunk */ ++ unsigned int dst_pitch_offset_c; ++ unsigned int dp_gui_master_cntl_c; ++ unsigned int sc_top_left_c; ++ unsigned int sc_bottom_right_c; ++ unsigned int z_offset_c; ++ unsigned int z_pitch_c; ++ unsigned int z_sten_cntl_c; ++ unsigned int tex_cntl_c; ++ unsigned int misc_3d_state_cntl_reg; ++ unsigned int texture_clr_cmp_clr_c; ++ unsigned int texture_clr_cmp_msk_c; ++ unsigned int fog_color_c; ++ ++ /* Texture state */ ++ unsigned int tex_size_pitch_c; ++ unsigned int constant_color_c; ++ ++ /* Setup state */ ++ unsigned int pm4_vc_fpu_setup; ++ unsigned int setup_cntl; ++ ++ /* Mask state */ ++ unsigned int dp_write_mask; ++ unsigned int sten_ref_mask_c; ++ unsigned int plane_3d_mask_c; ++ ++ /* Window state */ ++ unsigned int window_xy_offset; ++ ++ /* Core state */ ++ unsigned int scale_3d_cntl; ++} drm_r128_context_regs_t; ++ ++/* Setup registers for each texture unit ++ */ ++typedef struct { ++ unsigned int tex_cntl; ++ unsigned int tex_combine_cntl; ++ unsigned int tex_size_pitch; ++ unsigned int tex_offset[R128_MAX_TEXTURE_LEVELS]; ++ unsigned int tex_border_color; ++} drm_r128_texture_regs_t; ++ ++typedef struct drm_r128_sarea { ++ /* The channel for communication of state information to the kernel ++ * on firing a vertex buffer. ++ */ ++ drm_r128_context_regs_t context_state; ++ drm_r128_texture_regs_t tex_state[R128_MAX_TEXTURE_UNITS]; ++ unsigned int dirty; ++ unsigned int vertsize; ++ unsigned int vc_format; ++ ++ /* The current cliprects, or a subset thereof. ++ */ ++ struct drm_clip_rect boxes[R128_NR_SAREA_CLIPRECTS]; ++ unsigned int nbox; ++ ++ /* Counters for client-side throttling of rendering clients. ++ */ ++ unsigned int last_frame; ++ unsigned int last_dispatch; ++ ++ struct drm_tex_region tex_list[R128_NR_TEX_HEAPS][R128_NR_TEX_REGIONS + 1]; ++ unsigned int tex_age[R128_NR_TEX_HEAPS]; ++ int ctx_owner; ++ int pfAllowPageFlip; /* number of 3d windows (0,1,2 or more) */ ++ int pfCurrentPage; /* which buffer is being displayed? */ ++} drm_r128_sarea_t; ++ ++/* WARNING: If you change any of these defines, make sure to change the ++ * defines in the Xserver file (xf86drmR128.h) ++ */ ++ ++/* Rage 128 specific ioctls ++ * The device specific ioctl range is 0x40 to 0x79. ++ */ ++#define DRM_R128_INIT 0x00 ++#define DRM_R128_CCE_START 0x01 ++#define DRM_R128_CCE_STOP 0x02 ++#define DRM_R128_CCE_RESET 0x03 ++#define DRM_R128_CCE_IDLE 0x04 ++/* 0x05 not used */ ++#define DRM_R128_RESET 0x06 ++#define DRM_R128_SWAP 0x07 ++#define DRM_R128_CLEAR 0x08 ++#define DRM_R128_VERTEX 0x09 ++#define DRM_R128_INDICES 0x0a ++#define DRM_R128_BLIT 0x0b ++#define DRM_R128_DEPTH 0x0c ++#define DRM_R128_STIPPLE 0x0d ++/* 0x0e not used */ ++#define DRM_R128_INDIRECT 0x0f ++#define DRM_R128_FULLSCREEN 0x10 ++#define DRM_R128_CLEAR2 0x11 ++#define DRM_R128_GETPARAM 0x12 ++#define DRM_R128_FLIP 0x13 ++ ++#define DRM_IOCTL_R128_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_R128_INIT, drm_r128_init_t) ++#define DRM_IOCTL_R128_CCE_START DRM_IO( DRM_COMMAND_BASE + DRM_R128_CCE_START) ++#define DRM_IOCTL_R128_CCE_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CCE_STOP, drm_r128_cce_stop_t) ++#define DRM_IOCTL_R128_CCE_RESET DRM_IO( DRM_COMMAND_BASE + DRM_R128_CCE_RESET) ++#define DRM_IOCTL_R128_CCE_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_R128_CCE_IDLE) ++/* 0x05 not used */ ++#define DRM_IOCTL_R128_RESET DRM_IO( DRM_COMMAND_BASE + DRM_R128_RESET) ++#define DRM_IOCTL_R128_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_R128_SWAP) ++#define DRM_IOCTL_R128_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CLEAR, drm_r128_clear_t) ++#define DRM_IOCTL_R128_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_R128_VERTEX, drm_r128_vertex_t) ++#define DRM_IOCTL_R128_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_R128_INDICES, drm_r128_indices_t) ++#define DRM_IOCTL_R128_BLIT DRM_IOW( DRM_COMMAND_BASE + DRM_R128_BLIT, drm_r128_blit_t) ++#define DRM_IOCTL_R128_DEPTH DRM_IOW( DRM_COMMAND_BASE + DRM_R128_DEPTH, drm_r128_depth_t) ++#define DRM_IOCTL_R128_STIPPLE DRM_IOW( DRM_COMMAND_BASE + DRM_R128_STIPPLE, drm_r128_stipple_t) ++/* 0x0e not used */ ++#define DRM_IOCTL_R128_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_R128_INDIRECT, drm_r128_indirect_t) ++#define DRM_IOCTL_R128_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_R128_FULLSCREEN, drm_r128_fullscreen_t) ++#define DRM_IOCTL_R128_CLEAR2 DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CLEAR2, drm_r128_clear2_t) ++#define DRM_IOCTL_R128_GETPARAM DRM_IOWR( DRM_COMMAND_BASE + DRM_R128_GETPARAM, drm_r128_getparam_t) ++#define DRM_IOCTL_R128_FLIP DRM_IO( DRM_COMMAND_BASE + DRM_R128_FLIP) ++ ++typedef struct drm_r128_init { ++ enum { ++ R128_INIT_CCE = 0x01, ++ R128_CLEANUP_CCE = 0x02 ++ } func; ++ unsigned long sarea_priv_offset; ++ int is_pci; ++ int cce_mode; ++ int cce_secure; ++ int ring_size; ++ int usec_timeout; ++ ++ unsigned int fb_bpp; ++ unsigned int front_offset, front_pitch; ++ unsigned int back_offset, back_pitch; ++ unsigned int depth_bpp; ++ unsigned int depth_offset, depth_pitch; ++ unsigned int span_offset; ++ ++ unsigned long fb_offset; ++ unsigned long mmio_offset; ++ unsigned long ring_offset; ++ unsigned long ring_rptr_offset; ++ unsigned long buffers_offset; ++ unsigned long agp_textures_offset; ++} drm_r128_init_t; ++ ++typedef struct drm_r128_cce_stop { ++ int flush; ++ int idle; ++} drm_r128_cce_stop_t; ++ ++typedef struct drm_r128_clear { ++ unsigned int flags; ++ unsigned int clear_color; ++ unsigned int clear_depth; ++ unsigned int color_mask; ++ unsigned int depth_mask; ++} drm_r128_clear_t; ++ ++typedef struct drm_r128_vertex { ++ int prim; ++ int idx; /* Index of vertex buffer */ ++ int count; /* Number of vertices in buffer */ ++ int discard; /* Client finished with buffer? */ ++} drm_r128_vertex_t; ++ ++typedef struct drm_r128_indices { ++ int prim; ++ int idx; ++ int start; ++ int end; ++ int discard; /* Client finished with buffer? */ ++} drm_r128_indices_t; ++ ++typedef struct drm_r128_blit { ++ int idx; ++ int pitch; ++ int offset; ++ int format; ++ unsigned short x, y; ++ unsigned short width, height; ++} drm_r128_blit_t; ++ ++typedef struct drm_r128_depth { ++ enum { ++ R128_WRITE_SPAN = 0x01, ++ R128_WRITE_PIXELS = 0x02, ++ R128_READ_SPAN = 0x03, ++ R128_READ_PIXELS = 0x04 ++ } func; ++ int n; ++ int *x; ++ int *y; ++ unsigned int *buffer; ++ unsigned char *mask; ++} drm_r128_depth_t; ++ ++typedef struct drm_r128_stipple { ++ unsigned int *mask; ++} drm_r128_stipple_t; ++ ++typedef struct drm_r128_indirect { ++ int idx; ++ int start; ++ int end; ++ int discard; ++} drm_r128_indirect_t; ++ ++typedef struct drm_r128_fullscreen { ++ enum { ++ R128_INIT_FULLSCREEN = 0x01, ++ R128_CLEANUP_FULLSCREEN = 0x02 ++ } func; ++} drm_r128_fullscreen_t; ++ ++/* 2.3: An ioctl to get parameters that aren't available to the 3d ++ * client any other way. ++ */ ++#define R128_PARAM_IRQ_NR 1 ++ ++typedef struct drm_r128_getparam { ++ int param; ++ void *value; ++} drm_r128_getparam_t; ++ ++#endif +diff --git a/libc/kernel/common/drm/radeon_drm.h b/libc/kernel/common/drm/radeon_drm.h +new file mode 100644 +index 0000000..7ae3f42 +--- /dev/null ++++ b/libc/kernel/common/drm/radeon_drm.h +@@ -0,0 +1,976 @@ ++/* radeon_drm.h -- Public header for the radeon driver -*- linux-c -*- ++ * ++ * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. ++ * Copyright 2000 VA Linux Systems, Inc., Fremont, California. ++ * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. ++ * All rights reserved. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice (including the next ++ * paragraph) shall be included in all copies or substantial portions of the ++ * Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER ++ * DEALINGS IN THE SOFTWARE. ++ * ++ * Authors: ++ * Kevin E. Martin <martin@valinux.com> ++ * Gareth Hughes <gareth@valinux.com> ++ * Keith Whitwell <keith@tungstengraphics.com> ++ */ ++ ++#ifndef __RADEON_DRM_H__ ++#define __RADEON_DRM_H__ ++ ++#include "drm.h" ++ ++/* WARNING: If you change any of these defines, make sure to change the ++ * defines in the X server file (radeon_sarea.h) ++ */ ++#ifndef __RADEON_SAREA_DEFINES__ ++#define __RADEON_SAREA_DEFINES__ ++ ++/* Old style state flags, required for sarea interface (1.1 and 1.2 ++ * clears) and 1.2 drm_vertex2 ioctl. ++ */ ++#define RADEON_UPLOAD_CONTEXT 0x00000001 ++#define RADEON_UPLOAD_VERTFMT 0x00000002 ++#define RADEON_UPLOAD_LINE 0x00000004 ++#define RADEON_UPLOAD_BUMPMAP 0x00000008 ++#define RADEON_UPLOAD_MASKS 0x00000010 ++#define RADEON_UPLOAD_VIEWPORT 0x00000020 ++#define RADEON_UPLOAD_SETUP 0x00000040 ++#define RADEON_UPLOAD_TCL 0x00000080 ++#define RADEON_UPLOAD_MISC 0x00000100 ++#define RADEON_UPLOAD_TEX0 0x00000200 ++#define RADEON_UPLOAD_TEX1 0x00000400 ++#define RADEON_UPLOAD_TEX2 0x00000800 ++#define RADEON_UPLOAD_TEX0IMAGES 0x00001000 ++#define RADEON_UPLOAD_TEX1IMAGES 0x00002000 ++#define RADEON_UPLOAD_TEX2IMAGES 0x00004000 ++#define RADEON_UPLOAD_CLIPRECTS 0x00008000 /* handled client-side */ ++#define RADEON_REQUIRE_QUIESCENCE 0x00010000 ++#define RADEON_UPLOAD_ZBIAS 0x00020000 /* version 1.2 and newer */ ++#define RADEON_UPLOAD_ALL 0x003effff ++#define RADEON_UPLOAD_CONTEXT_ALL 0x003e01ff ++ ++/* New style per-packet identifiers for use in cmd_buffer ioctl with ++ * the RADEON_EMIT_PACKET command. Comments relate new packets to old ++ * state bits and the packet size: ++ */ ++#define RADEON_EMIT_PP_MISC 0 /* context/7 */ ++#define RADEON_EMIT_PP_CNTL 1 /* context/3 */ ++#define RADEON_EMIT_RB3D_COLORPITCH 2 /* context/1 */ ++#define RADEON_EMIT_RE_LINE_PATTERN 3 /* line/2 */ ++#define RADEON_EMIT_SE_LINE_WIDTH 4 /* line/1 */ ++#define RADEON_EMIT_PP_LUM_MATRIX 5 /* bumpmap/1 */ ++#define RADEON_EMIT_PP_ROT_MATRIX_0 6 /* bumpmap/2 */ ++#define RADEON_EMIT_RB3D_STENCILREFMASK 7 /* masks/3 */ ++#define RADEON_EMIT_SE_VPORT_XSCALE 8 /* viewport/6 */ ++#define RADEON_EMIT_SE_CNTL 9 /* setup/2 */ ++#define RADEON_EMIT_SE_CNTL_STATUS 10 /* setup/1 */ ++#define RADEON_EMIT_RE_MISC 11 /* misc/1 */ ++#define RADEON_EMIT_PP_TXFILTER_0 12 /* tex0/6 */ ++#define RADEON_EMIT_PP_BORDER_COLOR_0 13 /* tex0/1 */ ++#define RADEON_EMIT_PP_TXFILTER_1 14 /* tex1/6 */ ++#define RADEON_EMIT_PP_BORDER_COLOR_1 15 /* tex1/1 */ ++#define RADEON_EMIT_PP_TXFILTER_2 16 /* tex2/6 */ ++#define RADEON_EMIT_PP_BORDER_COLOR_2 17 /* tex2/1 */ ++#define RADEON_EMIT_SE_ZBIAS_FACTOR 18 /* zbias/2 */ ++#define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT 19 /* tcl/11 */ ++#define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED 20 /* material/17 */ ++#define R200_EMIT_PP_TXCBLEND_0 21 /* tex0/4 */ ++#define R200_EMIT_PP_TXCBLEND_1 22 /* tex1/4 */ ++#define R200_EMIT_PP_TXCBLEND_2 23 /* tex2/4 */ ++#define R200_EMIT_PP_TXCBLEND_3 24 /* tex3/4 */ ++#define R200_EMIT_PP_TXCBLEND_4 25 /* tex4/4 */ ++#define R200_EMIT_PP_TXCBLEND_5 26 /* tex5/4 */ ++#define R200_EMIT_PP_TXCBLEND_6 27 /* /4 */ ++#define R200_EMIT_PP_TXCBLEND_7 28 /* /4 */ ++#define R200_EMIT_TCL_LIGHT_MODEL_CTL_0 29 /* tcl/7 */ ++#define R200_EMIT_TFACTOR_0 30 /* tf/7 */ ++#define R200_EMIT_VTX_FMT_0 31 /* vtx/5 */ ++#define R200_EMIT_VAP_CTL 32 /* vap/1 */ ++#define R200_EMIT_MATRIX_SELECT_0 33 /* msl/5 */ ++#define R200_EMIT_TEX_PROC_CTL_2 34 /* tcg/5 */ ++#define R200_EMIT_TCL_UCP_VERT_BLEND_CTL 35 /* tcl/1 */ ++#define R200_EMIT_PP_TXFILTER_0 36 /* tex0/6 */ ++#define R200_EMIT_PP_TXFILTER_1 37 /* tex1/6 */ ++#define R200_EMIT_PP_TXFILTER_2 38 /* tex2/6 */ ++#define R200_EMIT_PP_TXFILTER_3 39 /* tex3/6 */ ++#define R200_EMIT_PP_TXFILTER_4 40 /* tex4/6 */ ++#define R200_EMIT_PP_TXFILTER_5 41 /* tex5/6 */ ++#define R200_EMIT_PP_TXOFFSET_0 42 /* tex0/1 */ ++#define R200_EMIT_PP_TXOFFSET_1 43 /* tex1/1 */ ++#define R200_EMIT_PP_TXOFFSET_2 44 /* tex2/1 */ ++#define R200_EMIT_PP_TXOFFSET_3 45 /* tex3/1 */ ++#define R200_EMIT_PP_TXOFFSET_4 46 /* tex4/1 */ ++#define R200_EMIT_PP_TXOFFSET_5 47 /* tex5/1 */ ++#define R200_EMIT_VTE_CNTL 48 /* vte/1 */ ++#define R200_EMIT_OUTPUT_VTX_COMP_SEL 49 /* vtx/1 */ ++#define R200_EMIT_PP_TAM_DEBUG3 50 /* tam/1 */ ++#define R200_EMIT_PP_CNTL_X 51 /* cst/1 */ ++#define R200_EMIT_RB3D_DEPTHXY_OFFSET 52 /* cst/1 */ ++#define R200_EMIT_RE_AUX_SCISSOR_CNTL 53 /* cst/1 */ ++#define R200_EMIT_RE_SCISSOR_TL_0 54 /* cst/2 */ ++#define R200_EMIT_RE_SCISSOR_TL_1 55 /* cst/2 */ ++#define R200_EMIT_RE_SCISSOR_TL_2 56 /* cst/2 */ ++#define R200_EMIT_SE_VAP_CNTL_STATUS 57 /* cst/1 */ ++#define R200_EMIT_SE_VTX_STATE_CNTL 58 /* cst/1 */ ++#define R200_EMIT_RE_POINTSIZE 59 /* cst/1 */ ++#define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 60 /* cst/4 */ ++#define R200_EMIT_PP_CUBIC_FACES_0 61 ++#define R200_EMIT_PP_CUBIC_OFFSETS_0 62 ++#define R200_EMIT_PP_CUBIC_FACES_1 63 ++#define R200_EMIT_PP_CUBIC_OFFSETS_1 64 ++#define R200_EMIT_PP_CUBIC_FACES_2 65 ++#define R200_EMIT_PP_CUBIC_OFFSETS_2 66 ++#define R200_EMIT_PP_CUBIC_FACES_3 67 ++#define R200_EMIT_PP_CUBIC_OFFSETS_3 68 ++#define R200_EMIT_PP_CUBIC_FACES_4 69 ++#define R200_EMIT_PP_CUBIC_OFFSETS_4 70 ++#define R200_EMIT_PP_CUBIC_FACES_5 71 ++#define R200_EMIT_PP_CUBIC_OFFSETS_5 72 ++#define RADEON_EMIT_PP_TEX_SIZE_0 73 ++#define RADEON_EMIT_PP_TEX_SIZE_1 74 ++#define RADEON_EMIT_PP_TEX_SIZE_2 75 ++#define R200_EMIT_RB3D_BLENDCOLOR 76 ++#define R200_EMIT_TCL_POINT_SPRITE_CNTL 77 ++#define RADEON_EMIT_PP_CUBIC_FACES_0 78 ++#define RADEON_EMIT_PP_CUBIC_OFFSETS_T0 79 ++#define RADEON_EMIT_PP_CUBIC_FACES_1 80 ++#define RADEON_EMIT_PP_CUBIC_OFFSETS_T1 81 ++#define RADEON_EMIT_PP_CUBIC_FACES_2 82 ++#define RADEON_EMIT_PP_CUBIC_OFFSETS_T2 83 ++#define R200_EMIT_PP_TRI_PERF_CNTL 84 ++#define R200_EMIT_PP_AFS_0 85 ++#define R200_EMIT_PP_AFS_1 86 ++#define R200_EMIT_ATF_TFACTOR 87 ++#define R200_EMIT_PP_TXCTLALL_0 88 ++#define R200_EMIT_PP_TXCTLALL_1 89 ++#define R200_EMIT_PP_TXCTLALL_2 90 ++#define R200_EMIT_PP_TXCTLALL_3 91 ++#define R200_EMIT_PP_TXCTLALL_4 92 ++#define R200_EMIT_PP_TXCTLALL_5 93 ++#define R200_EMIT_VAP_PVS_CNTL 94 ++#define RADEON_MAX_STATE_PACKETS 95 ++ ++/* Commands understood by cmd_buffer ioctl. More can be added but ++ * obviously these can't be removed or changed: ++ */ ++#define RADEON_CMD_PACKET 1 /* emit one of the register packets above */ ++#define RADEON_CMD_SCALARS 2 /* emit scalar data */ ++#define RADEON_CMD_VECTORS 3 /* emit vector data */ ++#define RADEON_CMD_DMA_DISCARD 4 /* discard current dma buf */ ++#define RADEON_CMD_PACKET3 5 /* emit hw packet */ ++#define RADEON_CMD_PACKET3_CLIP 6 /* emit hw packet wrapped in cliprects */ ++#define RADEON_CMD_SCALARS2 7 /* r200 stopgap */ ++#define RADEON_CMD_WAIT 8 /* emit hw wait commands -- note: ++ * doesn't make the cpu wait, just ++ * the graphics hardware */ ++#define RADEON_CMD_VECLINEAR 9 /* another r200 stopgap */ ++ ++typedef union { ++ int i; ++ struct { ++ unsigned char cmd_type, pad0, pad1, pad2; ++ } header; ++ struct { ++ unsigned char cmd_type, packet_id, pad0, pad1; ++ } packet; ++ struct { ++ unsigned char cmd_type, offset, stride, count; ++ } scalars; ++ struct { ++ unsigned char cmd_type, offset, stride, count; ++ } vectors; ++ struct { ++ unsigned char cmd_type, addr_lo, addr_hi, count; ++ } veclinear; ++ struct { ++ unsigned char cmd_type, buf_idx, pad0, pad1; ++ } dma; ++ struct { ++ unsigned char cmd_type, flags, pad0, pad1; ++ } wait; ++} drm_radeon_cmd_header_t; ++ ++#define RADEON_WAIT_2D 0x1 ++#define RADEON_WAIT_3D 0x2 ++ ++/* Allowed parameters for R300_CMD_PACKET3 ++ */ ++#define R300_CMD_PACKET3_CLEAR 0 ++#define R300_CMD_PACKET3_RAW 1 ++ ++/* Commands understood by cmd_buffer ioctl for R300. ++ * The interface has not been stabilized, so some of these may be removed ++ * and eventually reordered before stabilization. ++ */ ++#define R300_CMD_PACKET0 1 ++#define R300_CMD_VPU 2 /* emit vertex program upload */ ++#define R300_CMD_PACKET3 3 /* emit a packet3 */ ++#define R300_CMD_END3D 4 /* emit sequence ending 3d rendering */ ++#define R300_CMD_CP_DELAY 5 ++#define R300_CMD_DMA_DISCARD 6 ++#define R300_CMD_WAIT 7 ++# define R300_WAIT_2D 0x1 ++# define R300_WAIT_3D 0x2 ++/* these two defines are DOING IT WRONG - however ++ * we have userspace which relies on using these. ++ * The wait interface is backwards compat new ++ * code should use the NEW_WAIT defines below ++ * THESE ARE NOT BIT FIELDS ++ */ ++# define R300_WAIT_2D_CLEAN 0x3 ++# define R300_WAIT_3D_CLEAN 0x4 ++ ++# define R300_NEW_WAIT_2D_3D 0x3 ++# define R300_NEW_WAIT_2D_2D_CLEAN 0x4 ++# define R300_NEW_WAIT_3D_3D_CLEAN 0x6 ++# define R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN 0x8 ++ ++#define R300_CMD_SCRATCH 8 ++#define R300_CMD_R500FP 9 ++ ++typedef union { ++ unsigned int u; ++ struct { ++ unsigned char cmd_type, pad0, pad1, pad2; ++ } header; ++ struct { ++ unsigned char cmd_type, count, reglo, reghi; ++ } packet0; ++ struct { ++ unsigned char cmd_type, count, adrlo, adrhi; ++ } vpu; ++ struct { ++ unsigned char cmd_type, packet, pad0, pad1; ++ } packet3; ++ struct { ++ unsigned char cmd_type, packet; ++ unsigned short count; /* amount of packet2 to emit */ ++ } delay; ++ struct { ++ unsigned char cmd_type, buf_idx, pad0, pad1; ++ } dma; ++ struct { ++ unsigned char cmd_type, flags, pad0, pad1; ++ } wait; ++ struct { ++ unsigned char cmd_type, reg, n_bufs, flags; ++ } scratch; ++ struct { ++ unsigned char cmd_type, count, adrlo, adrhi_flags; ++ } r500fp; ++} drm_r300_cmd_header_t; ++ ++#define RADEON_FRONT 0x1 ++#define RADEON_BACK 0x2 ++#define RADEON_DEPTH 0x4 ++#define RADEON_STENCIL 0x8 ++#define RADEON_CLEAR_FASTZ 0x80000000 ++#define RADEON_USE_HIERZ 0x40000000 ++#define RADEON_USE_COMP_ZBUF 0x20000000 ++ ++#define R500FP_CONSTANT_TYPE (1 << 1) ++#define R500FP_CONSTANT_CLAMP (1 << 2) ++ ++/* Primitive types ++ */ ++#define RADEON_POINTS 0x1 ++#define RADEON_LINES 0x2 ++#define RADEON_LINE_STRIP 0x3 ++#define RADEON_TRIANGLES 0x4 ++#define RADEON_TRIANGLE_FAN 0x5 ++#define RADEON_TRIANGLE_STRIP 0x6 ++ ++/* Vertex/indirect buffer size ++ */ ++#define RADEON_BUFFER_SIZE 65536 ++ ++/* Byte offsets for indirect buffer data ++ */ ++#define RADEON_INDEX_PRIM_OFFSET 20 ++ ++#define RADEON_SCRATCH_REG_OFFSET 32 ++ ++#define R600_SCRATCH_REG_OFFSET 256 ++ ++#define RADEON_NR_SAREA_CLIPRECTS 12 ++ ++/* There are 2 heaps (local/GART). Each region within a heap is a ++ * minimum of 64k, and there are at most 64 of them per heap. ++ */ ++#define RADEON_LOCAL_TEX_HEAP 0 ++#define RADEON_GART_TEX_HEAP 1 ++#define RADEON_NR_TEX_HEAPS 2 ++#define RADEON_NR_TEX_REGIONS 64 ++#define RADEON_LOG_TEX_GRANULARITY 16 ++ ++#define RADEON_MAX_TEXTURE_LEVELS 12 ++#define RADEON_MAX_TEXTURE_UNITS 3 ++ ++#define RADEON_MAX_SURFACES 8 ++ ++/* Blits have strict offset rules. All blit offset must be aligned on ++ * a 1K-byte boundary. ++ */ ++#define RADEON_OFFSET_SHIFT 10 ++#define RADEON_OFFSET_ALIGN (1 << RADEON_OFFSET_SHIFT) ++#define RADEON_OFFSET_MASK (RADEON_OFFSET_ALIGN - 1) ++ ++#endif /* __RADEON_SAREA_DEFINES__ */ ++ ++typedef struct { ++ unsigned int red; ++ unsigned int green; ++ unsigned int blue; ++ unsigned int alpha; ++} radeon_color_regs_t; ++ ++typedef struct { ++ /* Context state */ ++ unsigned int pp_misc; /* 0x1c14 */ ++ unsigned int pp_fog_color; ++ unsigned int re_solid_color; ++ unsigned int rb3d_blendcntl; ++ unsigned int rb3d_depthoffset; ++ unsigned int rb3d_depthpitch; ++ unsigned int rb3d_zstencilcntl; ++ ++ unsigned int pp_cntl; /* 0x1c38 */ ++ unsigned int rb3d_cntl; ++ unsigned int rb3d_coloroffset; ++ unsigned int re_width_height; ++ unsigned int rb3d_colorpitch; ++ unsigned int se_cntl; ++ ++ /* Vertex format state */ ++ unsigned int se_coord_fmt; /* 0x1c50 */ ++ ++ /* Line state */ ++ unsigned int re_line_pattern; /* 0x1cd0 */ ++ unsigned int re_line_state; ++ ++ unsigned int se_line_width; /* 0x1db8 */ ++ ++ /* Bumpmap state */ ++ unsigned int pp_lum_matrix; /* 0x1d00 */ ++ ++ unsigned int pp_rot_matrix_0; /* 0x1d58 */ ++ unsigned int pp_rot_matrix_1; ++ ++ /* Mask state */ ++ unsigned int rb3d_stencilrefmask; /* 0x1d7c */ ++ unsigned int rb3d_ropcntl; ++ unsigned int rb3d_planemask; ++ ++ /* Viewport state */ ++ unsigned int se_vport_xscale; /* 0x1d98 */ ++ unsigned int se_vport_xoffset; ++ unsigned int se_vport_yscale; ++ unsigned int se_vport_yoffset; ++ unsigned int se_vport_zscale; ++ unsigned int se_vport_zoffset; ++ ++ /* Setup state */ ++ unsigned int se_cntl_status; /* 0x2140 */ ++ ++ /* Misc state */ ++ unsigned int re_top_left; /* 0x26c0 */ ++ unsigned int re_misc; ++} drm_radeon_context_regs_t; ++ ++typedef struct { ++ /* Zbias state */ ++ unsigned int se_zbias_factor; /* 0x1dac */ ++ unsigned int se_zbias_constant; ++} drm_radeon_context2_regs_t; ++ ++/* Setup registers for each texture unit ++ */ ++typedef struct { ++ unsigned int pp_txfilter; ++ unsigned int pp_txformat; ++ unsigned int pp_txoffset; ++ unsigned int pp_txcblend; ++ unsigned int pp_txablend; ++ unsigned int pp_tfactor; ++ unsigned int pp_border_color; ++} drm_radeon_texture_regs_t; ++ ++typedef struct { ++ unsigned int start; ++ unsigned int finish; ++ unsigned int prim:8; ++ unsigned int stateidx:8; ++ unsigned int numverts:16; /* overloaded as offset/64 for elt prims */ ++ unsigned int vc_format; /* vertex format */ ++} drm_radeon_prim_t; ++ ++typedef struct { ++ drm_radeon_context_regs_t context; ++ drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS]; ++ drm_radeon_context2_regs_t context2; ++ unsigned int dirty; ++} drm_radeon_state_t; ++ ++typedef struct { ++ /* The channel for communication of state information to the ++ * kernel on firing a vertex buffer with either of the ++ * obsoleted vertex/index ioctls. ++ */ ++ drm_radeon_context_regs_t context_state; ++ drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS]; ++ unsigned int dirty; ++ unsigned int vertsize; ++ unsigned int vc_format; ++ ++ /* The current cliprects, or a subset thereof. ++ */ ++ struct drm_clip_rect boxes[RADEON_NR_SAREA_CLIPRECTS]; ++ unsigned int nbox; ++ ++ /* Counters for client-side throttling of rendering clients. ++ */ ++ unsigned int last_frame; ++ unsigned int last_dispatch; ++ unsigned int last_clear; ++ ++ struct drm_tex_region tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS + ++ 1]; ++ unsigned int tex_age[RADEON_NR_TEX_HEAPS]; ++ int ctx_owner; ++ int pfState; /* number of 3d windows (0,1,2ormore) */ ++ int pfCurrentPage; /* which buffer is being displayed? */ ++ int crtc2_base; /* CRTC2 frame offset */ ++ int tiling_enabled; /* set by drm, read by 2d + 3d clients */ ++} drm_radeon_sarea_t; ++ ++/* WARNING: If you change any of these defines, make sure to change the ++ * defines in the Xserver file (xf86drmRadeon.h) ++ * ++ * KW: actually it's illegal to change any of this (backwards compatibility). ++ */ ++ ++/* Radeon specific ioctls ++ * The device specific ioctl range is 0x40 to 0x79. ++ */ ++#define DRM_RADEON_CP_INIT 0x00 ++#define DRM_RADEON_CP_START 0x01 ++#define DRM_RADEON_CP_STOP 0x02 ++#define DRM_RADEON_CP_RESET 0x03 ++#define DRM_RADEON_CP_IDLE 0x04 ++#define DRM_RADEON_RESET 0x05 ++#define DRM_RADEON_FULLSCREEN 0x06 ++#define DRM_RADEON_SWAP 0x07 ++#define DRM_RADEON_CLEAR 0x08 ++#define DRM_RADEON_VERTEX 0x09 ++#define DRM_RADEON_INDICES 0x0A ++#define DRM_RADEON_NOT_USED ++#define DRM_RADEON_STIPPLE 0x0C ++#define DRM_RADEON_INDIRECT 0x0D ++#define DRM_RADEON_TEXTURE 0x0E ++#define DRM_RADEON_VERTEX2 0x0F ++#define DRM_RADEON_CMDBUF 0x10 ++#define DRM_RADEON_GETPARAM 0x11 ++#define DRM_RADEON_FLIP 0x12 ++#define DRM_RADEON_ALLOC 0x13 ++#define DRM_RADEON_FREE 0x14 ++#define DRM_RADEON_INIT_HEAP 0x15 ++#define DRM_RADEON_IRQ_EMIT 0x16 ++#define DRM_RADEON_IRQ_WAIT 0x17 ++#define DRM_RADEON_CP_RESUME 0x18 ++#define DRM_RADEON_SETPARAM 0x19 ++#define DRM_RADEON_SURF_ALLOC 0x1a ++#define DRM_RADEON_SURF_FREE 0x1b ++/* KMS ioctl */ ++#define DRM_RADEON_GEM_INFO 0x1c ++#define DRM_RADEON_GEM_CREATE 0x1d ++#define DRM_RADEON_GEM_MMAP 0x1e ++#define DRM_RADEON_GEM_PREAD 0x21 ++#define DRM_RADEON_GEM_PWRITE 0x22 ++#define DRM_RADEON_GEM_SET_DOMAIN 0x23 ++#define DRM_RADEON_GEM_WAIT_IDLE 0x24 ++#define DRM_RADEON_CS 0x26 ++#define DRM_RADEON_INFO 0x27 ++#define DRM_RADEON_GEM_SET_TILING 0x28 ++#define DRM_RADEON_GEM_GET_TILING 0x29 ++#define DRM_RADEON_GEM_BUSY 0x2a ++#define DRM_RADEON_GEM_VA 0x2b ++ ++#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t) ++#define DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START) ++#define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t) ++#define DRM_IOCTL_RADEON_CP_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESET) ++#define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_IDLE) ++#define DRM_IOCTL_RADEON_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_RESET) ++#define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FULLSCREEN, drm_radeon_fullscreen_t) ++#define DRM_IOCTL_RADEON_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_SWAP) ++#define DRM_IOCTL_RADEON_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CLEAR, drm_radeon_clear_t) ++#define DRM_IOCTL_RADEON_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX, drm_radeon_vertex_t) ++#define DRM_IOCTL_RADEON_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INDICES, drm_radeon_indices_t) ++#define DRM_IOCTL_RADEON_STIPPLE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_STIPPLE, drm_radeon_stipple_t) ++#define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INDIRECT, drm_radeon_indirect_t) ++#define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_TEXTURE, drm_radeon_texture_t) ++#define DRM_IOCTL_RADEON_VERTEX2 DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX2, drm_radeon_vertex2_t) ++#define DRM_IOCTL_RADEON_CMDBUF DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CMDBUF, drm_radeon_cmd_buffer_t) ++#define DRM_IOCTL_RADEON_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GETPARAM, drm_radeon_getparam_t) ++#define DRM_IOCTL_RADEON_FLIP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_FLIP) ++#define DRM_IOCTL_RADEON_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_ALLOC, drm_radeon_mem_alloc_t) ++#define DRM_IOCTL_RADEON_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FREE, drm_radeon_mem_free_t) ++#define DRM_IOCTL_RADEON_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INIT_HEAP, drm_radeon_mem_init_heap_t) ++#define DRM_IOCTL_RADEON_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_IRQ_EMIT, drm_radeon_irq_emit_t) ++#define DRM_IOCTL_RADEON_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t) ++#define DRM_IOCTL_RADEON_CP_RESUME DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME) ++#define DRM_IOCTL_RADEON_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t) ++#define DRM_IOCTL_RADEON_SURF_ALLOC DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t) ++#define DRM_IOCTL_RADEON_SURF_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t) ++/* KMS */ ++#define DRM_IOCTL_RADEON_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_INFO, struct drm_radeon_gem_info) ++#define DRM_IOCTL_RADEON_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_CREATE, struct drm_radeon_gem_create) ++#define DRM_IOCTL_RADEON_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_MMAP, struct drm_radeon_gem_mmap) ++#define DRM_IOCTL_RADEON_GEM_PREAD DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PREAD, struct drm_radeon_gem_pread) ++#define DRM_IOCTL_RADEON_GEM_PWRITE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PWRITE, struct drm_radeon_gem_pwrite) ++#define DRM_IOCTL_RADEON_GEM_SET_DOMAIN DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_DOMAIN, struct drm_radeon_gem_set_domain) ++#define DRM_IOCTL_RADEON_GEM_WAIT_IDLE DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_GEM_WAIT_IDLE, struct drm_radeon_gem_wait_idle) ++#define DRM_IOCTL_RADEON_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS, struct drm_radeon_cs) ++#define DRM_IOCTL_RADEON_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INFO, struct drm_radeon_info) ++#define DRM_IOCTL_RADEON_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_TILING, struct drm_radeon_gem_set_tiling) ++#define DRM_IOCTL_RADEON_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_GET_TILING, struct drm_radeon_gem_get_tiling) ++#define DRM_IOCTL_RADEON_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_BUSY, struct drm_radeon_gem_busy) ++#define DRM_IOCTL_RADEON_GEM_VA DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_VA, struct drm_radeon_gem_va) ++ ++typedef struct drm_radeon_init { ++ enum { ++ RADEON_INIT_CP = 0x01, ++ RADEON_CLEANUP_CP = 0x02, ++ RADEON_INIT_R200_CP = 0x03, ++ RADEON_INIT_R300_CP = 0x04, ++ RADEON_INIT_R600_CP = 0x05 ++ } func; ++ unsigned long sarea_priv_offset; ++ int is_pci; ++ int cp_mode; ++ int gart_size; ++ int ring_size; ++ int usec_timeout; ++ ++ unsigned int fb_bpp; ++ unsigned int front_offset, front_pitch; ++ unsigned int back_offset, back_pitch; ++ unsigned int depth_bpp; ++ unsigned int depth_offset, depth_pitch; ++ ++ unsigned long fb_offset; ++ unsigned long mmio_offset; ++ unsigned long ring_offset; ++ unsigned long ring_rptr_offset; ++ unsigned long buffers_offset; ++ unsigned long gart_textures_offset; ++} drm_radeon_init_t; ++ ++typedef struct drm_radeon_cp_stop { ++ int flush; ++ int idle; ++} drm_radeon_cp_stop_t; ++ ++typedef struct drm_radeon_fullscreen { ++ enum { ++ RADEON_INIT_FULLSCREEN = 0x01, ++ RADEON_CLEANUP_FULLSCREEN = 0x02 ++ } func; ++} drm_radeon_fullscreen_t; ++ ++#define CLEAR_X1 0 ++#define CLEAR_Y1 1 ++#define CLEAR_X2 2 ++#define CLEAR_Y2 3 ++#define CLEAR_DEPTH 4 ++ ++typedef union drm_radeon_clear_rect { ++ float f[5]; ++ unsigned int ui[5]; ++} drm_radeon_clear_rect_t; ++ ++typedef struct drm_radeon_clear { ++ unsigned int flags; ++ unsigned int clear_color; ++ unsigned int clear_depth; ++ unsigned int color_mask; ++ unsigned int depth_mask; /* misnamed field: should be stencil */ ++ drm_radeon_clear_rect_t *depth_boxes; ++} drm_radeon_clear_t; ++ ++typedef struct drm_radeon_vertex { ++ int prim; ++ int idx; /* Index of vertex buffer */ ++ int count; /* Number of vertices in buffer */ ++ int discard; /* Client finished with buffer? */ ++} drm_radeon_vertex_t; ++ ++typedef struct drm_radeon_indices { ++ int prim; ++ int idx; ++ int start; ++ int end; ++ int discard; /* Client finished with buffer? */ ++} drm_radeon_indices_t; ++ ++/* v1.2 - obsoletes drm_radeon_vertex and drm_radeon_indices ++ * - allows multiple primitives and state changes in a single ioctl ++ * - supports driver change to emit native primitives ++ */ ++typedef struct drm_radeon_vertex2 { ++ int idx; /* Index of vertex buffer */ ++ int discard; /* Client finished with buffer? */ ++ int nr_states; ++ drm_radeon_state_t *state; ++ int nr_prims; ++ drm_radeon_prim_t *prim; ++} drm_radeon_vertex2_t; ++ ++/* v1.3 - obsoletes drm_radeon_vertex2 ++ * - allows arbitrarily large cliprect list ++ * - allows updating of tcl packet, vector and scalar state ++ * - allows memory-efficient description of state updates ++ * - allows state to be emitted without a primitive ++ * (for clears, ctx switches) ++ * - allows more than one dma buffer to be referenced per ioctl ++ * - supports tcl driver ++ * - may be extended in future versions with new cmd types, packets ++ */ ++typedef struct drm_radeon_cmd_buffer { ++ int bufsz; ++ char *buf; ++ int nbox; ++ struct drm_clip_rect *boxes; ++} drm_radeon_cmd_buffer_t; ++ ++typedef struct drm_radeon_tex_image { ++ unsigned int x, y; /* Blit coordinates */ ++ unsigned int width, height; ++ const void *data; ++} drm_radeon_tex_image_t; ++ ++typedef struct drm_radeon_texture { ++ unsigned int offset; ++ int pitch; ++ int format; ++ int width; /* Texture image coordinates */ ++ int height; ++ drm_radeon_tex_image_t *image; ++} drm_radeon_texture_t; ++ ++typedef struct drm_radeon_stipple { ++ unsigned int *mask; ++} drm_radeon_stipple_t; ++ ++typedef struct drm_radeon_indirect { ++ int idx; ++ int start; ++ int end; ++ int discard; ++} drm_radeon_indirect_t; ++ ++/* enum for card type parameters */ ++#define RADEON_CARD_PCI 0 ++#define RADEON_CARD_AGP 1 ++#define RADEON_CARD_PCIE 2 ++ ++/* 1.3: An ioctl to get parameters that aren't available to the 3d ++ * client any other way. ++ */ ++#define RADEON_PARAM_GART_BUFFER_OFFSET 1 /* card offset of 1st GART buffer */ ++#define RADEON_PARAM_LAST_FRAME 2 ++#define RADEON_PARAM_LAST_DISPATCH 3 ++#define RADEON_PARAM_LAST_CLEAR 4 ++/* Added with DRM version 1.6. */ ++#define RADEON_PARAM_IRQ_NR 5 ++#define RADEON_PARAM_GART_BASE 6 /* card offset of GART base */ ++/* Added with DRM version 1.8. */ ++#define RADEON_PARAM_REGISTER_HANDLE 7 /* for drmMap() */ ++#define RADEON_PARAM_STATUS_HANDLE 8 ++#define RADEON_PARAM_SAREA_HANDLE 9 ++#define RADEON_PARAM_GART_TEX_HANDLE 10 ++#define RADEON_PARAM_SCRATCH_OFFSET 11 ++#define RADEON_PARAM_CARD_TYPE 12 ++#define RADEON_PARAM_VBLANK_CRTC 13 /* VBLANK CRTC */ ++#define RADEON_PARAM_FB_LOCATION 14 /* FB location */ ++#define RADEON_PARAM_NUM_GB_PIPES 15 /* num GB pipes */ ++#define RADEON_PARAM_DEVICE_ID 16 ++#define RADEON_PARAM_NUM_Z_PIPES 17 /* num Z pipes */ ++ ++typedef struct drm_radeon_getparam { ++ int param; ++ void *value; ++} drm_radeon_getparam_t; ++ ++/* 1.6: Set up a memory manager for regions of shared memory: ++ */ ++#define RADEON_MEM_REGION_GART 1 ++#define RADEON_MEM_REGION_FB 2 ++ ++typedef struct drm_radeon_mem_alloc { ++ int region; ++ int alignment; ++ int size; ++ int *region_offset; /* offset from start of fb or GART */ ++} drm_radeon_mem_alloc_t; ++ ++typedef struct drm_radeon_mem_free { ++ int region; ++ int region_offset; ++} drm_radeon_mem_free_t; ++ ++typedef struct drm_radeon_mem_init_heap { ++ int region; ++ int size; ++ int start; ++} drm_radeon_mem_init_heap_t; ++ ++/* 1.6: Userspace can request & wait on irq's: ++ */ ++typedef struct drm_radeon_irq_emit { ++ int *irq_seq; ++} drm_radeon_irq_emit_t; ++ ++typedef struct drm_radeon_irq_wait { ++ int irq_seq; ++} drm_radeon_irq_wait_t; ++ ++/* 1.10: Clients tell the DRM where they think the framebuffer is located in ++ * the card's address space, via a new generic ioctl to set parameters ++ */ ++ ++typedef struct drm_radeon_setparam { ++ unsigned int param; ++ __s64 value; ++} drm_radeon_setparam_t; ++ ++#define RADEON_SETPARAM_FB_LOCATION 1 /* determined framebuffer location */ ++#define RADEON_SETPARAM_SWITCH_TILING 2 /* enable/disable color tiling */ ++#define RADEON_SETPARAM_PCIGART_LOCATION 3 /* PCI Gart Location */ ++#define RADEON_SETPARAM_NEW_MEMMAP 4 /* Use new memory map */ ++#define RADEON_SETPARAM_PCIGART_TABLE_SIZE 5 /* PCI GART Table Size */ ++#define RADEON_SETPARAM_VBLANK_CRTC 6 /* VBLANK CRTC */ ++/* 1.14: Clients can allocate/free a surface ++ */ ++typedef struct drm_radeon_surface_alloc { ++ unsigned int address; ++ unsigned int size; ++ unsigned int flags; ++} drm_radeon_surface_alloc_t; ++ ++typedef struct drm_radeon_surface_free { ++ unsigned int address; ++} drm_radeon_surface_free_t; ++ ++#define DRM_RADEON_VBLANK_CRTC1 1 ++#define DRM_RADEON_VBLANK_CRTC2 2 ++ ++/* ++ * Kernel modesetting world below. ++ */ ++#define RADEON_GEM_DOMAIN_CPU 0x1 ++#define RADEON_GEM_DOMAIN_GTT 0x2 ++#define RADEON_GEM_DOMAIN_VRAM 0x4 ++ ++struct drm_radeon_gem_info { ++ uint64_t gart_size; ++ uint64_t vram_size; ++ uint64_t vram_visible; ++}; ++ ++#define RADEON_GEM_NO_BACKING_STORE 1 ++ ++struct drm_radeon_gem_create { ++ uint64_t size; ++ uint64_t alignment; ++ uint32_t handle; ++ uint32_t initial_domain; ++ uint32_t flags; ++}; ++ ++#define RADEON_TILING_MACRO 0x1 ++#define RADEON_TILING_MICRO 0x2 ++#define RADEON_TILING_SWAP_16BIT 0x4 ++#define RADEON_TILING_SWAP_32BIT 0x8 ++/* this object requires a surface when mapped - i.e. front buffer */ ++#define RADEON_TILING_SURFACE 0x10 ++#define RADEON_TILING_MICRO_SQUARE 0x20 ++#define RADEON_TILING_EG_BANKW_SHIFT 8 ++#define RADEON_TILING_EG_BANKW_MASK 0xf ++#define RADEON_TILING_EG_BANKH_SHIFT 12 ++#define RADEON_TILING_EG_BANKH_MASK 0xf ++#define RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT 16 ++#define RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK 0xf ++#define RADEON_TILING_EG_TILE_SPLIT_SHIFT 24 ++#define RADEON_TILING_EG_TILE_SPLIT_MASK 0xf ++#define RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT 28 ++#define RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK 0xf ++ ++struct drm_radeon_gem_set_tiling { ++ uint32_t handle; ++ uint32_t tiling_flags; ++ uint32_t pitch; ++}; ++ ++struct drm_radeon_gem_get_tiling { ++ uint32_t handle; ++ uint32_t tiling_flags; ++ uint32_t pitch; ++}; ++ ++struct drm_radeon_gem_mmap { ++ uint32_t handle; ++ uint32_t pad; ++ uint64_t offset; ++ uint64_t size; ++ uint64_t addr_ptr; ++}; ++ ++struct drm_radeon_gem_set_domain { ++ uint32_t handle; ++ uint32_t read_domains; ++ uint32_t write_domain; ++}; ++ ++struct drm_radeon_gem_wait_idle { ++ uint32_t handle; ++ uint32_t pad; ++}; ++ ++struct drm_radeon_gem_busy { ++ uint32_t handle; ++ uint32_t domain; ++}; ++ ++struct drm_radeon_gem_pread { ++ /** Handle for the object being read. */ ++ uint32_t handle; ++ uint32_t pad; ++ /** Offset into the object to read from */ ++ uint64_t offset; ++ /** Length of data to read */ ++ uint64_t size; ++ /** Pointer to write the data into. */ ++ /* void *, but pointers are not 32/64 compatible */ ++ uint64_t data_ptr; ++}; ++ ++struct drm_radeon_gem_pwrite { ++ /** Handle for the object being written to. */ ++ uint32_t handle; ++ uint32_t pad; ++ /** Offset into the object to write to */ ++ uint64_t offset; ++ /** Length of data to write */ ++ uint64_t size; ++ /** Pointer to read the data from. */ ++ /* void *, but pointers are not 32/64 compatible */ ++ uint64_t data_ptr; ++}; ++ ++#define RADEON_VA_MAP 1 ++#define RADEON_VA_UNMAP 2 ++ ++#define RADEON_VA_RESULT_OK 0 ++#define RADEON_VA_RESULT_ERROR 1 ++#define RADEON_VA_RESULT_VA_EXIST 2 ++ ++#define RADEON_VM_PAGE_VALID (1 << 0) ++#define RADEON_VM_PAGE_READABLE (1 << 1) ++#define RADEON_VM_PAGE_WRITEABLE (1 << 2) ++#define RADEON_VM_PAGE_SYSTEM (1 << 3) ++#define RADEON_VM_PAGE_SNOOPED (1 << 4) ++ ++struct drm_radeon_gem_va { ++ uint32_t handle; ++ uint32_t operation; ++ uint32_t vm_id; ++ uint32_t flags; ++ uint64_t offset; ++}; ++ ++#define RADEON_CHUNK_ID_RELOCS 0x01 ++#define RADEON_CHUNK_ID_IB 0x02 ++#define RADEON_CHUNK_ID_FLAGS 0x03 ++#define RADEON_CHUNK_ID_CONST_IB 0x04 ++ ++/* The first dword of RADEON_CHUNK_ID_FLAGS is a uint32 of these flags: */ ++#define RADEON_CS_KEEP_TILING_FLAGS 0x01 ++#define RADEON_CS_USE_VM 0x02 ++/* The second dword of RADEON_CHUNK_ID_FLAGS is a uint32 that sets the ring type */ ++#define RADEON_CS_RING_GFX 0 ++#define RADEON_CS_RING_COMPUTE 1 ++/* The third dword of RADEON_CHUNK_ID_FLAGS is a sint32 that sets the priority */ ++/* 0 = normal, + = higher priority, - = lower priority */ ++ ++struct drm_radeon_cs_chunk { ++ uint32_t chunk_id; ++ uint32_t length_dw; ++ uint64_t chunk_data; ++}; ++ ++/* drm_radeon_cs_reloc.flags */ ++ ++struct drm_radeon_cs_reloc { ++ uint32_t handle; ++ uint32_t read_domains; ++ uint32_t write_domain; ++ uint32_t flags; ++}; ++ ++struct drm_radeon_cs { ++ uint32_t num_chunks; ++ uint32_t cs_id; ++ /* this points to uint64_t * which point to cs chunks */ ++ uint64_t chunks; ++ /* updates to the limits after this CS ioctl */ ++ uint64_t gart_limit; ++ uint64_t vram_limit; ++}; ++ ++#define RADEON_INFO_DEVICE_ID 0x00 ++#define RADEON_INFO_NUM_GB_PIPES 0x01 ++#define RADEON_INFO_NUM_Z_PIPES 0x02 ++#define RADEON_INFO_ACCEL_WORKING 0x03 ++#define RADEON_INFO_CRTC_FROM_ID 0x04 ++#define RADEON_INFO_ACCEL_WORKING2 0x05 ++#define RADEON_INFO_TILING_CONFIG 0x06 ++#define RADEON_INFO_WANT_HYPERZ 0x07 ++#define RADEON_INFO_WANT_CMASK 0x08 /* get access to CMASK on r300 */ ++#define RADEON_INFO_CLOCK_CRYSTAL_FREQ 0x09 /* clock crystal frequency */ ++#define RADEON_INFO_NUM_BACKENDS 0x0a /* DB/backends for r600+ - need for OQ */ ++#define RADEON_INFO_NUM_TILE_PIPES 0x0b /* tile pipes for r600+ */ ++#define RADEON_INFO_FUSION_GART_WORKING 0x0c /* fusion writes to GTT were broken before this */ ++#define RADEON_INFO_BACKEND_MAP 0x0d /* pipe to backend map, needed by mesa */ ++/* virtual address start, va < start are reserved by the kernel */ ++#define RADEON_INFO_VA_START 0x0e ++/* maximum size of ib using the virtual memory cs */ ++#define RADEON_INFO_IB_VM_MAX_SIZE 0x0f ++/* max pipes - needed for compute shaders */ ++#define RADEON_INFO_MAX_PIPES 0x10 ++/* timestamp for GL_ARB_timer_query (OpenGL), returns the current GPU clock */ ++#define RADEON_INFO_TIMESTAMP 0x11 ++ ++struct drm_radeon_info { ++ uint32_t request; ++ uint32_t pad; ++ uint64_t value; ++}; ++ ++#endif +diff --git a/libc/kernel/common/drm/savage_drm.h b/libc/kernel/common/drm/savage_drm.h +new file mode 100644 +index 0000000..a1df939 +--- /dev/null ++++ b/libc/kernel/common/drm/savage_drm.h +@@ -0,0 +1,210 @@ ++/* savage_drm.h -- Public header for the savage driver ++ * ++ * Copyright 2004 Felix Kuehling ++ * All Rights Reserved. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sub license, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice (including the ++ * next paragraph) shall be included in all copies or substantial portions ++ * of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF ++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NON-INFRINGEMENT. IN NO EVENT SHALL FELIX KUEHLING BE LIABLE FOR ++ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF ++ * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION ++ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++#ifndef __SAVAGE_DRM_H__ ++#define __SAVAGE_DRM_H__ ++ ++#ifndef __SAVAGE_SAREA_DEFINES__ ++#define __SAVAGE_SAREA_DEFINES__ ++ ++/* 2 heaps (1 for card, 1 for agp), each divided into up to 128 ++ * regions, subject to a minimum region size of (1<<16) == 64k. ++ * ++ * Clients may subdivide regions internally, but when sharing between ++ * clients, the region size is the minimum granularity. ++ */ ++ ++#define SAVAGE_CARD_HEAP 0 ++#define SAVAGE_AGP_HEAP 1 ++#define SAVAGE_NR_TEX_HEAPS 2 ++#define SAVAGE_NR_TEX_REGIONS 16 ++#define SAVAGE_LOG_MIN_TEX_REGION_SIZE 16 ++ ++#endif /* __SAVAGE_SAREA_DEFINES__ */ ++ ++typedef struct _drm_savage_sarea { ++ /* LRU lists for texture memory in agp space and on the card. ++ */ ++ struct drm_tex_region texList[SAVAGE_NR_TEX_HEAPS][SAVAGE_NR_TEX_REGIONS + ++ 1]; ++ unsigned int texAge[SAVAGE_NR_TEX_HEAPS]; ++ ++ /* Mechanism to validate card state. ++ */ ++ int ctxOwner; ++} drm_savage_sarea_t, *drm_savage_sarea_ptr; ++ ++/* Savage-specific ioctls ++ */ ++#define DRM_SAVAGE_BCI_INIT 0x00 ++#define DRM_SAVAGE_BCI_CMDBUF 0x01 ++#define DRM_SAVAGE_BCI_EVENT_EMIT 0x02 ++#define DRM_SAVAGE_BCI_EVENT_WAIT 0x03 ++ ++#define DRM_IOCTL_SAVAGE_BCI_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_SAVAGE_BCI_INIT, drm_savage_init_t) ++#define DRM_IOCTL_SAVAGE_BCI_CMDBUF DRM_IOW( DRM_COMMAND_BASE + DRM_SAVAGE_BCI_CMDBUF, drm_savage_cmdbuf_t) ++#define DRM_IOCTL_SAVAGE_BCI_EVENT_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_SAVAGE_BCI_EVENT_EMIT, drm_savage_event_emit_t) ++#define DRM_IOCTL_SAVAGE_BCI_EVENT_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_SAVAGE_BCI_EVENT_WAIT, drm_savage_event_wait_t) ++ ++#define SAVAGE_DMA_PCI 1 ++#define SAVAGE_DMA_AGP 3 ++typedef struct drm_savage_init { ++ enum { ++ SAVAGE_INIT_BCI = 1, ++ SAVAGE_CLEANUP_BCI = 2 ++ } func; ++ unsigned int sarea_priv_offset; ++ ++ /* some parameters */ ++ unsigned int cob_size; ++ unsigned int bci_threshold_lo, bci_threshold_hi; ++ unsigned int dma_type; ++ ++ /* frame buffer layout */ ++ unsigned int fb_bpp; ++ unsigned int front_offset, front_pitch; ++ unsigned int back_offset, back_pitch; ++ unsigned int depth_bpp; ++ unsigned int depth_offset, depth_pitch; ++ ++ /* local textures */ ++ unsigned int texture_offset; ++ unsigned int texture_size; ++ ++ /* physical locations of non-permanent maps */ ++ unsigned long status_offset; ++ unsigned long buffers_offset; ++ unsigned long agp_textures_offset; ++ unsigned long cmd_dma_offset; ++} drm_savage_init_t; ++ ++typedef union drm_savage_cmd_header drm_savage_cmd_header_t; ++typedef struct drm_savage_cmdbuf { ++ /* command buffer in client's address space */ ++ drm_savage_cmd_header_t *cmd_addr; ++ unsigned int size; /* size of the command buffer in 64bit units */ ++ ++ unsigned int dma_idx; /* DMA buffer index to use */ ++ int discard; /* discard DMA buffer when done */ ++ /* vertex buffer in client's address space */ ++ unsigned int *vb_addr; ++ unsigned int vb_size; /* size of client vertex buffer in bytes */ ++ unsigned int vb_stride; /* stride of vertices in 32bit words */ ++ /* boxes in client's address space */ ++ struct drm_clip_rect *box_addr; ++ unsigned int nbox; /* number of clipping boxes */ ++} drm_savage_cmdbuf_t; ++ ++#define SAVAGE_WAIT_2D 0x1 /* wait for 2D idle before updating event tag */ ++#define SAVAGE_WAIT_3D 0x2 /* wait for 3D idle before updating event tag */ ++#define SAVAGE_WAIT_IRQ 0x4 /* emit or wait for IRQ, not implemented yet */ ++typedef struct drm_savage_event { ++ unsigned int count; ++ unsigned int flags; ++} drm_savage_event_emit_t, drm_savage_event_wait_t; ++ ++/* Commands for the cmdbuf ioctl ++ */ ++#define SAVAGE_CMD_STATE 0 /* a range of state registers */ ++#define SAVAGE_CMD_DMA_PRIM 1 /* vertices from DMA buffer */ ++#define SAVAGE_CMD_VB_PRIM 2 /* vertices from client vertex buffer */ ++#define SAVAGE_CMD_DMA_IDX 3 /* indexed vertices from DMA buffer */ ++#define SAVAGE_CMD_VB_IDX 4 /* indexed vertices client vertex buffer */ ++#define SAVAGE_CMD_CLEAR 5 /* clear buffers */ ++#define SAVAGE_CMD_SWAP 6 /* swap buffers */ ++ ++/* Primitive types ++*/ ++#define SAVAGE_PRIM_TRILIST 0 /* triangle list */ ++#define SAVAGE_PRIM_TRISTRIP 1 /* triangle strip */ ++#define SAVAGE_PRIM_TRIFAN 2 /* triangle fan */ ++#define SAVAGE_PRIM_TRILIST_201 3 /* reorder verts for correct flat ++ * shading on s3d */ ++ ++/* Skip flags (vertex format) ++ */ ++#define SAVAGE_SKIP_Z 0x01 ++#define SAVAGE_SKIP_W 0x02 ++#define SAVAGE_SKIP_C0 0x04 ++#define SAVAGE_SKIP_C1 0x08 ++#define SAVAGE_SKIP_S0 0x10 ++#define SAVAGE_SKIP_T0 0x20 ++#define SAVAGE_SKIP_ST0 0x30 ++#define SAVAGE_SKIP_S1 0x40 ++#define SAVAGE_SKIP_T1 0x80 ++#define SAVAGE_SKIP_ST1 0xc0 ++#define SAVAGE_SKIP_ALL_S3D 0x3f ++#define SAVAGE_SKIP_ALL_S4 0xff ++ ++/* Buffer names for clear command ++ */ ++#define SAVAGE_FRONT 0x1 ++#define SAVAGE_BACK 0x2 ++#define SAVAGE_DEPTH 0x4 ++ ++/* 64-bit command header ++ */ ++union drm_savage_cmd_header { ++ struct { ++ unsigned char cmd; /* command */ ++ unsigned char pad0; ++ unsigned short pad1; ++ unsigned short pad2; ++ unsigned short pad3; ++ } cmd; /* generic */ ++ struct { ++ unsigned char cmd; ++ unsigned char global; /* need idle engine? */ ++ unsigned short count; /* number of consecutive registers */ ++ unsigned short start; /* first register */ ++ unsigned short pad3; ++ } state; /* SAVAGE_CMD_STATE */ ++ struct { ++ unsigned char cmd; ++ unsigned char prim; /* primitive type */ ++ unsigned short skip; /* vertex format (skip flags) */ ++ unsigned short count; /* number of vertices */ ++ unsigned short start; /* first vertex in DMA/vertex buffer */ ++ } prim; /* SAVAGE_CMD_DMA_PRIM, SAVAGE_CMD_VB_PRIM */ ++ struct { ++ unsigned char cmd; ++ unsigned char prim; ++ unsigned short skip; ++ unsigned short count; /* number of indices that follow */ ++ unsigned short pad3; ++ } idx; /* SAVAGE_CMD_DMA_IDX, SAVAGE_CMD_VB_IDX */ ++ struct { ++ unsigned char cmd; ++ unsigned char pad0; ++ unsigned short pad1; ++ unsigned int flags; ++ } clear0; /* SAVAGE_CMD_CLEAR */ ++ struct { ++ unsigned int mask; ++ unsigned int value; ++ } clear1; /* SAVAGE_CMD_CLEAR data */ ++}; ++ ++#endif +diff --git a/libc/kernel/common/drm/sis_drm.h b/libc/kernel/common/drm/sis_drm.h +new file mode 100644 +index 0000000..df37632 +--- /dev/null ++++ b/libc/kernel/common/drm/sis_drm.h +@@ -0,0 +1,71 @@ ++/* sis_drv.h -- Private header for sis driver -*- linux-c -*- */ ++/* ++ * Copyright 2005 Eric Anholt ++ * All Rights Reserved. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice (including the next ++ * paragraph) shall be included in all copies or substantial portions of the ++ * Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER ++ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, ++ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE ++ * SOFTWARE. ++ * ++ */ ++ ++#ifndef __SIS_DRM_H__ ++#define __SIS_DRM_H__ ++ ++/* SiS specific ioctls */ ++#define NOT_USED_0_3 ++#define DRM_SIS_FB_ALLOC 0x04 ++#define DRM_SIS_FB_FREE 0x05 ++#define NOT_USED_6_12 ++#define DRM_SIS_AGP_INIT 0x13 ++#define DRM_SIS_AGP_ALLOC 0x14 ++#define DRM_SIS_AGP_FREE 0x15 ++#define DRM_SIS_FB_INIT 0x16 ++ ++#define DRM_IOCTL_SIS_FB_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_SIS_FB_ALLOC, drm_sis_mem_t) ++#define DRM_IOCTL_SIS_FB_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_SIS_FB_FREE, drm_sis_mem_t) ++#define DRM_IOCTL_SIS_AGP_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_SIS_AGP_INIT, drm_sis_agp_t) ++#define DRM_IOCTL_SIS_AGP_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_SIS_AGP_ALLOC, drm_sis_mem_t) ++#define DRM_IOCTL_SIS_AGP_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_SIS_AGP_FREE, drm_sis_mem_t) ++#define DRM_IOCTL_SIS_FB_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_SIS_FB_INIT, drm_sis_fb_t) ++/* ++#define DRM_IOCTL_SIS_FLIP DRM_IOW( 0x48, drm_sis_flip_t) ++#define DRM_IOCTL_SIS_FLIP_INIT DRM_IO( 0x49) ++#define DRM_IOCTL_SIS_FLIP_FINAL DRM_IO( 0x50) ++*/ ++ ++typedef struct { ++ int context; ++ unsigned long offset; ++ unsigned long size; ++ unsigned long free; ++} drm_sis_mem_t; ++ ++typedef struct { ++ unsigned long offset, size; ++} drm_sis_agp_t; ++ ++typedef struct { ++ unsigned long offset, size; ++} drm_sis_fb_t; ++ ++struct sis_file_private { ++ struct list_head obj_list; ++}; ++ ++#endif /* __SIS_DRM_H__ */ +diff --git a/libc/kernel/common/drm/via_drm.h b/libc/kernel/common/drm/via_drm.h +new file mode 100644 +index 0000000..44eafda +--- /dev/null ++++ b/libc/kernel/common/drm/via_drm.h +@@ -0,0 +1,279 @@ ++/* ++ * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved. ++ * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sub license, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice (including the ++ * next paragraph) shall be included in all copies or substantial portions ++ * of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL ++ * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER ++ * DEALINGS IN THE SOFTWARE. ++ */ ++#ifndef _VIA_DRM_H_ ++#define _VIA_DRM_H_ ++ ++#include "drm.h" ++ ++/* WARNING: These defines must be the same as what the Xserver uses. ++ * if you change them, you must change the defines in the Xserver. ++ */ ++ ++#ifndef _VIA_DEFINES_ ++#define _VIA_DEFINES_ ++ ++#include "via_drmclient.h" ++ ++#define VIA_NR_SAREA_CLIPRECTS 8 ++#define VIA_NR_XVMC_PORTS 10 ++#define VIA_NR_XVMC_LOCKS 5 ++#define VIA_MAX_CACHELINE_SIZE 64 ++#define XVMCLOCKPTR(saPriv,lockNo) \ ++ ((__volatile__ struct drm_hw_lock *)(((((unsigned long) (saPriv)->XvMCLockArea) + \ ++ (VIA_MAX_CACHELINE_SIZE - 1)) & \ ++ ~(VIA_MAX_CACHELINE_SIZE - 1)) + \ ++ VIA_MAX_CACHELINE_SIZE*(lockNo))) ++ ++/* Each region is a minimum of 64k, and there are at most 64 of them. ++ */ ++#define VIA_NR_TEX_REGIONS 64 ++#define VIA_LOG_MIN_TEX_REGION_SIZE 16 ++#endif ++ ++#define VIA_UPLOAD_TEX0IMAGE 0x1 /* handled clientside */ ++#define VIA_UPLOAD_TEX1IMAGE 0x2 /* handled clientside */ ++#define VIA_UPLOAD_CTX 0x4 ++#define VIA_UPLOAD_BUFFERS 0x8 ++#define VIA_UPLOAD_TEX0 0x10 ++#define VIA_UPLOAD_TEX1 0x20 ++#define VIA_UPLOAD_CLIPRECTS 0x40 ++#define VIA_UPLOAD_ALL 0xff ++ ++/* VIA specific ioctls */ ++#define DRM_VIA_ALLOCMEM 0x00 ++#define DRM_VIA_FREEMEM 0x01 ++#define DRM_VIA_AGP_INIT 0x02 ++#define DRM_VIA_FB_INIT 0x03 ++#define DRM_VIA_MAP_INIT 0x04 ++#define DRM_VIA_DEC_FUTEX 0x05 ++#define NOT_USED ++#define DRM_VIA_DMA_INIT 0x07 ++#define DRM_VIA_CMDBUFFER 0x08 ++#define DRM_VIA_FLUSH 0x09 ++#define DRM_VIA_PCICMD 0x0a ++#define DRM_VIA_CMDBUF_SIZE 0x0b ++#define NOT_USED ++#define DRM_VIA_WAIT_IRQ 0x0d ++#define DRM_VIA_DMA_BLIT 0x0e ++#define DRM_VIA_BLIT_SYNC 0x0f ++ ++#define DRM_IOCTL_VIA_ALLOCMEM DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_ALLOCMEM, drm_via_mem_t) ++#define DRM_IOCTL_VIA_FREEMEM DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_FREEMEM, drm_via_mem_t) ++#define DRM_IOCTL_VIA_AGP_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_AGP_INIT, drm_via_agp_t) ++#define DRM_IOCTL_VIA_FB_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_FB_INIT, drm_via_fb_t) ++#define DRM_IOCTL_VIA_MAP_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_MAP_INIT, drm_via_init_t) ++#define DRM_IOCTL_VIA_DEC_FUTEX DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_DEC_FUTEX, drm_via_futex_t) ++#define DRM_IOCTL_VIA_DMA_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_DMA_INIT, drm_via_dma_init_t) ++#define DRM_IOCTL_VIA_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_CMDBUFFER, drm_via_cmdbuffer_t) ++#define DRM_IOCTL_VIA_FLUSH DRM_IO( DRM_COMMAND_BASE + DRM_VIA_FLUSH) ++#define DRM_IOCTL_VIA_PCICMD DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_PCICMD, drm_via_cmdbuffer_t) ++#define DRM_IOCTL_VIA_CMDBUF_SIZE DRM_IOWR( DRM_COMMAND_BASE + DRM_VIA_CMDBUF_SIZE, \ ++ drm_via_cmdbuf_size_t) ++#define DRM_IOCTL_VIA_WAIT_IRQ DRM_IOWR( DRM_COMMAND_BASE + DRM_VIA_WAIT_IRQ, drm_via_irqwait_t) ++#define DRM_IOCTL_VIA_DMA_BLIT DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_DMA_BLIT, drm_via_dmablit_t) ++#define DRM_IOCTL_VIA_BLIT_SYNC DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_BLIT_SYNC, drm_via_blitsync_t) ++ ++/* Indices into buf.Setup where various bits of state are mirrored per ++ * context and per buffer. These can be fired at the card as a unit, ++ * or in a piecewise fashion as required. ++ */ ++ ++#define VIA_TEX_SETUP_SIZE 8 ++ ++/* Flags for clear ioctl ++ */ ++#define VIA_FRONT 0x1 ++#define VIA_BACK 0x2 ++#define VIA_DEPTH 0x4 ++#define VIA_STENCIL 0x8 ++#define VIA_MEM_VIDEO 0 /* matches drm constant */ ++#define VIA_MEM_AGP 1 /* matches drm constant */ ++#define VIA_MEM_SYSTEM 2 ++#define VIA_MEM_MIXED 3 ++#define VIA_MEM_UNKNOWN 4 ++ ++typedef struct { ++ __u32 offset; ++ __u32 size; ++} drm_via_agp_t; ++ ++typedef struct { ++ __u32 offset; ++ __u32 size; ++} drm_via_fb_t; ++ ++typedef struct { ++ __u32 context; ++ __u32 type; ++ __u32 size; ++ unsigned long index; ++ unsigned long offset; ++} drm_via_mem_t; ++ ++typedef struct _drm_via_init { ++ enum { ++ VIA_INIT_MAP = 0x01, ++ VIA_CLEANUP_MAP = 0x02 ++ } func; ++ ++ unsigned long sarea_priv_offset; ++ unsigned long fb_offset; ++ unsigned long mmio_offset; ++ unsigned long agpAddr; ++} drm_via_init_t; ++ ++typedef struct _drm_via_futex { ++ enum { ++ VIA_FUTEX_WAIT = 0x00, ++ VIA_FUTEX_WAKE = 0X01 ++ } func; ++ __u32 ms; ++ __u32 lock; ++ __u32 val; ++} drm_via_futex_t; ++ ++typedef struct _drm_via_dma_init { ++ enum { ++ VIA_INIT_DMA = 0x01, ++ VIA_CLEANUP_DMA = 0x02, ++ VIA_DMA_INITIALIZED = 0x03 ++ } func; ++ ++ unsigned long offset; ++ unsigned long size; ++ unsigned long reg_pause_addr; ++} drm_via_dma_init_t; ++ ++typedef struct _drm_via_cmdbuffer { ++ char *buf; ++ unsigned long size; ++} drm_via_cmdbuffer_t; ++ ++/* Warning: If you change the SAREA structure you must change the Xserver ++ * structure as well */ ++ ++typedef struct _drm_via_tex_region { ++ unsigned char next, prev; /* indices to form a circular LRU */ ++ unsigned char inUse; /* owned by a client, or free? */ ++ int age; /* tracked by clients to update local LRU's */ ++} drm_via_tex_region_t; ++ ++typedef struct _drm_via_sarea { ++ unsigned int dirty; ++ unsigned int nbox; ++ struct drm_clip_rect boxes[VIA_NR_SAREA_CLIPRECTS]; ++ drm_via_tex_region_t texList[VIA_NR_TEX_REGIONS + 1]; ++ int texAge; /* last time texture was uploaded */ ++ int ctxOwner; /* last context to upload state */ ++ int vertexPrim; ++ ++ /* ++ * Below is for XvMC. ++ * We want the lock integers alone on, and aligned to, a cache line. ++ * Therefore this somewhat strange construct. ++ */ ++ ++ char XvMCLockArea[VIA_MAX_CACHELINE_SIZE * (VIA_NR_XVMC_LOCKS + 1)]; ++ ++ unsigned int XvMCDisplaying[VIA_NR_XVMC_PORTS]; ++ unsigned int XvMCSubPicOn[VIA_NR_XVMC_PORTS]; ++ unsigned int XvMCCtxNoGrabbed; /* Last context to hold decoder */ ++ ++ /* Used by the 3d driver only at this point, for pageflipping: ++ */ ++ unsigned int pfCurrentOffset; ++} drm_via_sarea_t; ++ ++typedef struct _drm_via_cmdbuf_size { ++ enum { ++ VIA_CMDBUF_SPACE = 0x01, ++ VIA_CMDBUF_LAG = 0x02 ++ } func; ++ int wait; ++ __u32 size; ++} drm_via_cmdbuf_size_t; ++ ++typedef enum { ++ VIA_IRQ_ABSOLUTE = 0x0, ++ VIA_IRQ_RELATIVE = 0x1, ++ VIA_IRQ_SIGNAL = 0x10000000, ++ VIA_IRQ_FORCE_SEQUENCE = 0x20000000 ++} via_irq_seq_type_t; ++ ++#define VIA_IRQ_FLAGS_MASK 0xF0000000 ++ ++enum drm_via_irqs { ++ drm_via_irq_hqv0 = 0, ++ drm_via_irq_hqv1, ++ drm_via_irq_dma0_dd, ++ drm_via_irq_dma0_td, ++ drm_via_irq_dma1_dd, ++ drm_via_irq_dma1_td, ++ drm_via_irq_num ++}; ++ ++struct drm_via_wait_irq_request { ++ unsigned irq; ++ via_irq_seq_type_t type; ++ __u32 sequence; ++ __u32 signal; ++}; ++ ++typedef union drm_via_irqwait { ++ struct drm_via_wait_irq_request request; ++ struct drm_wait_vblank_reply reply; ++} drm_via_irqwait_t; ++ ++typedef struct drm_via_blitsync { ++ __u32 sync_handle; ++ unsigned engine; ++} drm_via_blitsync_t; ++ ++/* - * Below,"flags" is currently unused but will be used for possible future ++ * extensions like kernel space bounce buffers for bad alignments and ++ * blit engine busy-wait polling for better latency in the absence of ++ * interrupts. ++ */ ++ ++typedef struct drm_via_dmablit { ++ __u32 num_lines; ++ __u32 line_length; ++ ++ __u32 fb_addr; ++ __u32 fb_stride; ++ ++ unsigned char *mem_addr; ++ __u32 mem_stride; ++ ++ __u32 flags; ++ int to_fb; ++ ++ drm_via_blitsync_t sync; ++} drm_via_dmablit_t; ++ ++struct via_file_private { ++ struct list_head obj_list; ++}; ++ ++#endif /* _VIA_DRM_H_ */ +diff --git a/libc/kernel/common/drm/vmwgfx_drm.h b/libc/kernel/common/drm/vmwgfx_drm.h +new file mode 100644 +index 0000000..bcb0912 +--- /dev/null ++++ b/libc/kernel/common/drm/vmwgfx_drm.h +@@ -0,0 +1,790 @@ ++/************************************************************************** ++ * ++ * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA ++ * All Rights Reserved. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the ++ * "Software"), to deal in the Software without restriction, including ++ * without limitation the rights to use, copy, modify, merge, publish, ++ * distribute, sub license, and/or sell copies of the Software, and to ++ * permit persons to whom the Software is furnished to do so, subject to ++ * the following conditions: ++ * ++ * The above copyright notice and this permission notice (including the ++ * next paragraph) shall be included in all copies or substantial portions ++ * of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, ++ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR ++ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE ++ * USE OR OTHER DEALINGS IN THE SOFTWARE. ++ * ++ **************************************************************************/ ++ ++#ifndef __VMWGFX_DRM_H__ ++#define __VMWGFX_DRM_H__ ++ ++#define DRM_VMW_MAX_SURFACE_FACES 6 ++#define DRM_VMW_MAX_MIP_LEVELS 24 ++ ++ ++#define DRM_VMW_GET_PARAM 0 ++#define DRM_VMW_ALLOC_DMABUF 1 ++#define DRM_VMW_UNREF_DMABUF 2 ++#define DRM_VMW_CURSOR_BYPASS 3 ++/* guarded by DRM_VMW_PARAM_NUM_STREAMS != 0*/ ++#define DRM_VMW_CONTROL_STREAM 4 ++#define DRM_VMW_CLAIM_STREAM 5 ++#define DRM_VMW_UNREF_STREAM 6 ++/* guarded by DRM_VMW_PARAM_3D == 1 */ ++#define DRM_VMW_CREATE_CONTEXT 7 ++#define DRM_VMW_UNREF_CONTEXT 8 ++#define DRM_VMW_CREATE_SURFACE 9 ++#define DRM_VMW_UNREF_SURFACE 10 ++#define DRM_VMW_REF_SURFACE 11 ++#define DRM_VMW_EXECBUF 12 ++#define DRM_VMW_GET_3D_CAP 13 ++#define DRM_VMW_FENCE_WAIT 14 ++#define DRM_VMW_FENCE_SIGNALED 15 ++#define DRM_VMW_FENCE_UNREF 16 ++#define DRM_VMW_FENCE_EVENT 17 ++#define DRM_VMW_PRESENT 18 ++#define DRM_VMW_PRESENT_READBACK 19 ++#define DRM_VMW_UPDATE_LAYOUT 20 ++ ++/*************************************************************************/ ++/** ++ * DRM_VMW_GET_PARAM - get device information. ++ * ++ * DRM_VMW_PARAM_FIFO_OFFSET: ++ * Offset to use to map the first page of the FIFO read-only. ++ * The fifo is mapped using the mmap() system call on the drm device. ++ * ++ * DRM_VMW_PARAM_OVERLAY_IOCTL: ++ * Does the driver support the overlay ioctl. ++ */ ++ ++#define DRM_VMW_PARAM_NUM_STREAMS 0 ++#define DRM_VMW_PARAM_NUM_FREE_STREAMS 1 ++#define DRM_VMW_PARAM_3D 2 ++#define DRM_VMW_PARAM_HW_CAPS 3 ++#define DRM_VMW_PARAM_FIFO_CAPS 4 ++#define DRM_VMW_PARAM_MAX_FB_SIZE 5 ++#define DRM_VMW_PARAM_FIFO_HW_VERSION 6 ++ ++/** ++ * struct drm_vmw_getparam_arg ++ * ++ * @value: Returned value. //Out ++ * @param: Parameter to query. //In. ++ * ++ * Argument to the DRM_VMW_GET_PARAM Ioctl. ++ */ ++ ++struct drm_vmw_getparam_arg { ++ uint64_t value; ++ uint32_t param; ++ uint32_t pad64; ++}; ++ ++/*************************************************************************/ ++/** ++ * DRM_VMW_CREATE_CONTEXT - Create a host context. ++ * ++ * Allocates a device unique context id, and queues a create context command ++ * for the host. Does not wait for host completion. ++ */ ++ ++/** ++ * struct drm_vmw_context_arg ++ * ++ * @cid: Device unique context ID. ++ * ++ * Output argument to the DRM_VMW_CREATE_CONTEXT Ioctl. ++ * Input argument to the DRM_VMW_UNREF_CONTEXT Ioctl. ++ */ ++ ++struct drm_vmw_context_arg { ++ int32_t cid; ++ uint32_t pad64; ++}; ++ ++/*************************************************************************/ ++/** ++ * DRM_VMW_UNREF_CONTEXT - Create a host context. ++ * ++ * Frees a global context id, and queues a destroy host command for the host. ++ * Does not wait for host completion. The context ID can be used directly ++ * in the command stream and shows up as the same context ID on the host. ++ */ ++ ++/*************************************************************************/ ++/** ++ * DRM_VMW_CREATE_SURFACE - Create a host suface. ++ * ++ * Allocates a device unique surface id, and queues a create surface command ++ * for the host. Does not wait for host completion. The surface ID can be ++ * used directly in the command stream and shows up as the same surface ++ * ID on the host. ++ */ ++ ++/** ++ * struct drm_wmv_surface_create_req ++ * ++ * @flags: Surface flags as understood by the host. ++ * @format: Surface format as understood by the host. ++ * @mip_levels: Number of mip levels for each face. ++ * An unused face should have 0 encoded. ++ * @size_addr: Address of a user-space array of sruct drm_vmw_size ++ * cast to an uint64_t for 32-64 bit compatibility. ++ * The size of the array should equal the total number of mipmap levels. ++ * @shareable: Boolean whether other clients (as identified by file descriptors) ++ * may reference this surface. ++ * @scanout: Boolean whether the surface is intended to be used as a ++ * scanout. ++ * ++ * Input data to the DRM_VMW_CREATE_SURFACE Ioctl. ++ * Output data from the DRM_VMW_REF_SURFACE Ioctl. ++ */ ++ ++struct drm_vmw_surface_create_req { ++ uint32_t flags; ++ uint32_t format; ++ uint32_t mip_levels[DRM_VMW_MAX_SURFACE_FACES]; ++ uint64_t size_addr; ++ int32_t shareable; ++ int32_t scanout; ++}; ++ ++/** ++ * struct drm_wmv_surface_arg ++ * ++ * @sid: Surface id of created surface or surface to destroy or reference. ++ * ++ * Output data from the DRM_VMW_CREATE_SURFACE Ioctl. ++ * Input argument to the DRM_VMW_UNREF_SURFACE Ioctl. ++ * Input argument to the DRM_VMW_REF_SURFACE Ioctl. ++ */ ++ ++struct drm_vmw_surface_arg { ++ int32_t sid; ++ uint32_t pad64; ++}; ++ ++/** ++ * struct drm_vmw_size ioctl. ++ * ++ * @width - mip level width ++ * @height - mip level height ++ * @depth - mip level depth ++ * ++ * Description of a mip level. ++ * Input data to the DRM_WMW_CREATE_SURFACE Ioctl. ++ */ ++ ++struct drm_vmw_size { ++ uint32_t width; ++ uint32_t height; ++ uint32_t depth; ++ uint32_t pad64; ++}; ++ ++/** ++ * union drm_vmw_surface_create_arg ++ * ++ * @rep: Output data as described above. ++ * @req: Input data as described above. ++ * ++ * Argument to the DRM_VMW_CREATE_SURFACE Ioctl. ++ */ ++ ++union drm_vmw_surface_create_arg { ++ struct drm_vmw_surface_arg rep; ++ struct drm_vmw_surface_create_req req; ++}; ++ ++/*************************************************************************/ ++/** ++ * DRM_VMW_REF_SURFACE - Reference a host surface. ++ * ++ * Puts a reference on a host surface with a give sid, as previously ++ * returned by the DRM_VMW_CREATE_SURFACE ioctl. ++ * A reference will make sure the surface isn't destroyed while we hold ++ * it and will allow the calling client to use the surface ID in the command ++ * stream. ++ * ++ * On successful return, the Ioctl returns the surface information given ++ * in the DRM_VMW_CREATE_SURFACE ioctl. ++ */ ++ ++/** ++ * union drm_vmw_surface_reference_arg ++ * ++ * @rep: Output data as described above. ++ * @req: Input data as described above. ++ * ++ * Argument to the DRM_VMW_REF_SURFACE Ioctl. ++ */ ++ ++union drm_vmw_surface_reference_arg { ++ struct drm_vmw_surface_create_req rep; ++ struct drm_vmw_surface_arg req; ++}; ++ ++/*************************************************************************/ ++/** ++ * DRM_VMW_UNREF_SURFACE - Unreference a host surface. ++ * ++ * Clear a reference previously put on a host surface. ++ * When all references are gone, including the one implicitly placed ++ * on creation, ++ * a destroy surface command will be queued for the host. ++ * Does not wait for completion. ++ */ ++ ++/*************************************************************************/ ++/** ++ * DRM_VMW_EXECBUF ++ * ++ * Submit a command buffer for execution on the host, and return a ++ * fence seqno that when signaled, indicates that the command buffer has ++ * executed. ++ */ ++ ++/** ++ * struct drm_vmw_execbuf_arg ++ * ++ * @commands: User-space address of a command buffer cast to an uint64_t. ++ * @command-size: Size in bytes of the command buffer. ++ * @throttle-us: Sleep until software is less than @throttle_us ++ * microseconds ahead of hardware. The driver may round this value ++ * to the nearest kernel tick. ++ * @fence_rep: User-space address of a struct drm_vmw_fence_rep cast to an ++ * uint64_t. ++ * @version: Allows expanding the execbuf ioctl parameters without breaking ++ * backwards compatibility, since user-space will always tell the kernel ++ * which version it uses. ++ * @flags: Execbuf flags. None currently. ++ * ++ * Argument to the DRM_VMW_EXECBUF Ioctl. ++ */ ++ ++#define DRM_VMW_EXECBUF_VERSION 1 ++ ++struct drm_vmw_execbuf_arg { ++ uint64_t commands; ++ uint32_t command_size; ++ uint32_t throttle_us; ++ uint64_t fence_rep; ++ uint32_t version; ++ uint32_t flags; ++}; ++ ++/** ++ * struct drm_vmw_fence_rep ++ * ++ * @handle: Fence object handle for fence associated with a command submission. ++ * @mask: Fence flags relevant for this fence object. ++ * @seqno: Fence sequence number in fifo. A fence object with a lower ++ * seqno will signal the EXEC flag before a fence object with a higher ++ * seqno. This can be used by user-space to avoid kernel calls to determine ++ * whether a fence has signaled the EXEC flag. Note that @seqno will ++ * wrap at 32-bit. ++ * @passed_seqno: The highest seqno number processed by the hardware ++ * so far. This can be used to mark user-space fence objects as signaled, and ++ * to determine whether a fence seqno might be stale. ++ * @error: This member should've been set to -EFAULT on submission. ++ * The following actions should be take on completion: ++ * error == -EFAULT: Fence communication failed. The host is synchronized. ++ * Use the last fence id read from the FIFO fence register. ++ * error != 0 && error != -EFAULT: ++ * Fence submission failed. The host is synchronized. Use the fence_seq member. ++ * error == 0: All is OK, The host may not be synchronized. ++ * Use the fence_seq member. ++ * ++ * Input / Output data to the DRM_VMW_EXECBUF Ioctl. ++ */ ++ ++struct drm_vmw_fence_rep { ++ uint32_t handle; ++ uint32_t mask; ++ uint32_t seqno; ++ uint32_t passed_seqno; ++ uint32_t pad64; ++ int32_t error; ++}; ++ ++/*************************************************************************/ ++/** ++ * DRM_VMW_ALLOC_DMABUF ++ * ++ * Allocate a DMA buffer that is visible also to the host. ++ * NOTE: The buffer is ++ * identified by a handle and an offset, which are private to the guest, but ++ * useable in the command stream. The guest kernel may translate these ++ * and patch up the command stream accordingly. In the future, the offset may ++ * be zero at all times, or it may disappear from the interface before it is ++ * fixed. ++ * ++ * The DMA buffer may stay user-space mapped in the guest at all times, ++ * and is thus suitable for sub-allocation. ++ * ++ * DMA buffers are mapped using the mmap() syscall on the drm device. ++ */ ++ ++/** ++ * struct drm_vmw_alloc_dmabuf_req ++ * ++ * @size: Required minimum size of the buffer. ++ * ++ * Input data to the DRM_VMW_ALLOC_DMABUF Ioctl. ++ */ ++ ++struct drm_vmw_alloc_dmabuf_req { ++ uint32_t size; ++ uint32_t pad64; ++}; ++ ++/** ++ * struct drm_vmw_dmabuf_rep ++ * ++ * @map_handle: Offset to use in the mmap() call used to map the buffer. ++ * @handle: Handle unique to this buffer. Used for unreferencing. ++ * @cur_gmr_id: GMR id to use in the command stream when this buffer is ++ * referenced. See not above. ++ * @cur_gmr_offset: Offset to use in the command stream when this buffer is ++ * referenced. See note above. ++ * ++ * Output data from the DRM_VMW_ALLOC_DMABUF Ioctl. ++ */ ++ ++struct drm_vmw_dmabuf_rep { ++ uint64_t map_handle; ++ uint32_t handle; ++ uint32_t cur_gmr_id; ++ uint32_t cur_gmr_offset; ++ uint32_t pad64; ++}; ++ ++/** ++ * union drm_vmw_dmabuf_arg ++ * ++ * @req: Input data as described above. ++ * @rep: Output data as described above. ++ * ++ * Argument to the DRM_VMW_ALLOC_DMABUF Ioctl. ++ */ ++ ++union drm_vmw_alloc_dmabuf_arg { ++ struct drm_vmw_alloc_dmabuf_req req; ++ struct drm_vmw_dmabuf_rep rep; ++}; ++ ++/*************************************************************************/ ++/** ++ * DRM_VMW_UNREF_DMABUF - Free a DMA buffer. ++ * ++ */ ++ ++/** ++ * struct drm_vmw_unref_dmabuf_arg ++ * ++ * @handle: Handle indicating what buffer to free. Obtained from the ++ * DRM_VMW_ALLOC_DMABUF Ioctl. ++ * ++ * Argument to the DRM_VMW_UNREF_DMABUF Ioctl. ++ */ ++ ++struct drm_vmw_unref_dmabuf_arg { ++ uint32_t handle; ++ uint32_t pad64; ++}; ++ ++/*************************************************************************/ ++/** ++ * DRM_VMW_CONTROL_STREAM - Control overlays, aka streams. ++ * ++ * This IOCTL controls the overlay units of the svga device. ++ * The SVGA overlay units does not work like regular hardware units in ++ * that they do not automaticaly read back the contents of the given dma ++ * buffer. But instead only read back for each call to this ioctl, and ++ * at any point between this call being made and a following call that ++ * either changes the buffer or disables the stream. ++ */ ++ ++/** ++ * struct drm_vmw_rect ++ * ++ * Defines a rectangle. Used in the overlay ioctl to define ++ * source and destination rectangle. ++ */ ++ ++struct drm_vmw_rect { ++ int32_t x; ++ int32_t y; ++ uint32_t w; ++ uint32_t h; ++}; ++ ++/** ++ * struct drm_vmw_control_stream_arg ++ * ++ * @stream_id: Stearm to control ++ * @enabled: If false all following arguments are ignored. ++ * @handle: Handle to buffer for getting data from. ++ * @format: Format of the overlay as understood by the host. ++ * @width: Width of the overlay. ++ * @height: Height of the overlay. ++ * @size: Size of the overlay in bytes. ++ * @pitch: Array of pitches, the two last are only used for YUV12 formats. ++ * @offset: Offset from start of dma buffer to overlay. ++ * @src: Source rect, must be within the defined area above. ++ * @dst: Destination rect, x and y may be negative. ++ * ++ * Argument to the DRM_VMW_CONTROL_STREAM Ioctl. ++ */ ++ ++struct drm_vmw_control_stream_arg { ++ uint32_t stream_id; ++ uint32_t enabled; ++ ++ uint32_t flags; ++ uint32_t color_key; ++ ++ uint32_t handle; ++ uint32_t offset; ++ int32_t format; ++ uint32_t size; ++ uint32_t width; ++ uint32_t height; ++ uint32_t pitch[3]; ++ ++ uint32_t pad64; ++ struct drm_vmw_rect src; ++ struct drm_vmw_rect dst; ++}; ++ ++/*************************************************************************/ ++/** ++ * DRM_VMW_CURSOR_BYPASS - Give extra information about cursor bypass. ++ * ++ */ ++ ++#define DRM_VMW_CURSOR_BYPASS_ALL (1 << 0) ++#define DRM_VMW_CURSOR_BYPASS_FLAGS (1) ++ ++/** ++ * struct drm_vmw_cursor_bypass_arg ++ * ++ * @flags: Flags. ++ * @crtc_id: Crtc id, only used if DMR_CURSOR_BYPASS_ALL isn't passed. ++ * @xpos: X position of cursor. ++ * @ypos: Y position of cursor. ++ * @xhot: X hotspot. ++ * @yhot: Y hotspot. ++ * ++ * Argument to the DRM_VMW_CURSOR_BYPASS Ioctl. ++ */ ++ ++struct drm_vmw_cursor_bypass_arg { ++ uint32_t flags; ++ uint32_t crtc_id; ++ int32_t xpos; ++ int32_t ypos; ++ int32_t xhot; ++ int32_t yhot; ++}; ++ ++/*************************************************************************/ ++/** ++ * DRM_VMW_CLAIM_STREAM - Claim a single stream. ++ */ ++ ++/** ++ * struct drm_vmw_context_arg ++ * ++ * @stream_id: Device unique context ID. ++ * ++ * Output argument to the DRM_VMW_CREATE_CONTEXT Ioctl. ++ * Input argument to the DRM_VMW_UNREF_CONTEXT Ioctl. ++ */ ++ ++struct drm_vmw_stream_arg { ++ uint32_t stream_id; ++ uint32_t pad64; ++}; ++ ++/*************************************************************************/ ++/** ++ * DRM_VMW_UNREF_STREAM - Unclaim a stream. ++ * ++ * Return a single stream that was claimed by this process. Also makes ++ * sure that the stream has been stopped. ++ */ ++ ++/*************************************************************************/ ++/** ++ * DRM_VMW_GET_3D_CAP ++ * ++ * Read 3D capabilities from the FIFO ++ * ++ */ ++ ++/** ++ * struct drm_vmw_get_3d_cap_arg ++ * ++ * @buffer: Pointer to a buffer for capability data, cast to an uint64_t ++ * @size: Max size to copy ++ * ++ * Input argument to the DRM_VMW_GET_3D_CAP_IOCTL ++ * ioctls. ++ */ ++ ++struct drm_vmw_get_3d_cap_arg { ++ uint64_t buffer; ++ uint32_t max_size; ++ uint32_t pad64; ++}; ++ ++/*************************************************************************/ ++/** ++ * DRM_VMW_FENCE_WAIT ++ * ++ * Waits for a fence object to signal. The wait is interruptible, so that ++ * signals may be delivered during the interrupt. The wait may timeout, ++ * in which case the calls returns -EBUSY. If the wait is restarted, ++ * that is restarting without resetting @cookie_valid to zero, ++ * the timeout is computed from the first call. ++ * ++ * The flags argument to the DRM_VMW_FENCE_WAIT ioctl indicates what to wait ++ * on: ++ * DRM_VMW_FENCE_FLAG_EXEC: All commands ahead of the fence in the command ++ * stream ++ * have executed. ++ * DRM_VMW_FENCE_FLAG_QUERY: All query results resulting from query finish ++ * commands ++ * in the buffer given to the EXECBUF ioctl returning the fence object handle ++ * are available to user-space. ++ * ++ * DRM_VMW_WAIT_OPTION_UNREF: If this wait option is given, and the ++ * fenc wait ioctl returns 0, the fence object has been unreferenced after ++ * the wait. ++ */ ++ ++#define DRM_VMW_FENCE_FLAG_EXEC (1 << 0) ++#define DRM_VMW_FENCE_FLAG_QUERY (1 << 1) ++ ++#define DRM_VMW_WAIT_OPTION_UNREF (1 << 0) ++ ++/** ++ * struct drm_vmw_fence_wait_arg ++ * ++ * @handle: Fence object handle as returned by the DRM_VMW_EXECBUF ioctl. ++ * @cookie_valid: Must be reset to 0 on first call. Left alone on restart. ++ * @kernel_cookie: Set to 0 on first call. Left alone on restart. ++ * @timeout_us: Wait timeout in microseconds. 0 for indefinite timeout. ++ * @lazy: Set to 1 if timing is not critical. Allow more than a kernel tick ++ * before returning. ++ * @flags: Fence flags to wait on. ++ * @wait_options: Options that control the behaviour of the wait ioctl. ++ * ++ * Input argument to the DRM_VMW_FENCE_WAIT ioctl. ++ */ ++ ++struct drm_vmw_fence_wait_arg { ++ uint32_t handle; ++ int32_t cookie_valid; ++ uint64_t kernel_cookie; ++ uint64_t timeout_us; ++ int32_t lazy; ++ int32_t flags; ++ int32_t wait_options; ++ int32_t pad64; ++}; ++ ++/*************************************************************************/ ++/** ++ * DRM_VMW_FENCE_SIGNALED ++ * ++ * Checks if a fence object is signaled.. ++ */ ++ ++/** ++ * struct drm_vmw_fence_signaled_arg ++ * ++ * @handle: Fence object handle as returned by the DRM_VMW_EXECBUF ioctl. ++ * @flags: Fence object flags input to DRM_VMW_FENCE_SIGNALED ioctl ++ * @signaled: Out: Flags signaled. ++ * @sequence: Out: Highest sequence passed so far. Can be used to signal the ++ * EXEC flag of user-space fence objects. ++ * ++ * Input/Output argument to the DRM_VMW_FENCE_SIGNALED and DRM_VMW_FENCE_UNREF ++ * ioctls. ++ */ ++ ++struct drm_vmw_fence_signaled_arg { ++ uint32_t handle; ++ uint32_t flags; ++ int32_t signaled; ++ uint32_t passed_seqno; ++ uint32_t signaled_flags; ++ uint32_t pad64; ++}; ++ ++/*************************************************************************/ ++/** ++ * DRM_VMW_FENCE_UNREF ++ * ++ * Unreferences a fence object, and causes it to be destroyed if there are no ++ * other references to it. ++ * ++ */ ++ ++/** ++ * struct drm_vmw_fence_arg ++ * ++ * @handle: Fence object handle as returned by the DRM_VMW_EXECBUF ioctl. ++ * ++ * Input/Output argument to the DRM_VMW_FENCE_UNREF ioctl.. ++ */ ++ ++struct drm_vmw_fence_arg { ++ uint32_t handle; ++ uint32_t pad64; ++}; ++ ++ ++/*************************************************************************/ ++/** ++ * DRM_VMW_FENCE_EVENT ++ * ++ * Queues an event on a fence to be delivered on the drm character device ++ * when the fence has signaled the DRM_VMW_FENCE_FLAG_EXEC flag. ++ * Optionally the approximate time when the fence signaled is ++ * given by the event. ++ */ ++ ++/* ++ * The event type ++ */ ++#define DRM_VMW_EVENT_FENCE_SIGNALED 0x80000000 ++ ++struct drm_vmw_event_fence { ++ struct drm_event base; ++ uint64_t user_data; ++ uint32_t tv_sec; ++ uint32_t tv_usec; ++}; ++ ++/* ++ * Flags that may be given to the command. ++ */ ++/* Request fence signaled time on the event. */ ++#define DRM_VMW_FE_FLAG_REQ_TIME (1 << 0) ++ ++/** ++ * struct drm_vmw_fence_event_arg ++ * ++ * @fence_rep: Pointer to fence_rep structure cast to uint64_t or 0 if ++ * the fence is not supposed to be referenced by user-space. ++ * @user_info: Info to be delivered with the event. ++ * @handle: Attach the event to this fence only. ++ * @flags: A set of flags as defined above. ++ */ ++struct drm_vmw_fence_event_arg { ++ uint64_t fence_rep; ++ uint64_t user_data; ++ uint32_t handle; ++ uint32_t flags; ++}; ++ ++ ++/*************************************************************************/ ++/** ++ * DRM_VMW_PRESENT ++ * ++ * Executes an SVGA present on a given fb for a given surface. The surface ++ * is placed on the framebuffer. Cliprects are given relative to the given ++ * point (the point disignated by dest_{x|y}). ++ * ++ */ ++ ++/** ++ * struct drm_vmw_present_arg ++ * @fb_id: framebuffer id to present / read back from. ++ * @sid: Surface id to present from. ++ * @dest_x: X placement coordinate for surface. ++ * @dest_y: Y placement coordinate for surface. ++ * @clips_ptr: Pointer to an array of clip rects cast to an uint64_t. ++ * @num_clips: Number of cliprects given relative to the framebuffer origin, ++ * in the same coordinate space as the frame buffer. ++ * @pad64: Unused 64-bit padding. ++ * ++ * Input argument to the DRM_VMW_PRESENT ioctl. ++ */ ++ ++struct drm_vmw_present_arg { ++ uint32_t fb_id; ++ uint32_t sid; ++ int32_t dest_x; ++ int32_t dest_y; ++ uint64_t clips_ptr; ++ uint32_t num_clips; ++ uint32_t pad64; ++}; ++ ++ ++/*************************************************************************/ ++/** ++ * DRM_VMW_PRESENT_READBACK ++ * ++ * Executes an SVGA present readback from a given fb to the dma buffer ++ * currently bound as the fb. If there is no dma buffer bound to the fb, ++ * an error will be returned. ++ * ++ */ ++ ++/** ++ * struct drm_vmw_present_arg ++ * @fb_id: fb_id to present / read back from. ++ * @num_clips: Number of cliprects. ++ * @clips_ptr: Pointer to an array of clip rects cast to an uint64_t. ++ * @fence_rep: Pointer to a struct drm_vmw_fence_rep, cast to an uint64_t. ++ * If this member is NULL, then the ioctl should not return a fence. ++ */ ++ ++struct drm_vmw_present_readback_arg { ++ uint32_t fb_id; ++ uint32_t num_clips; ++ uint64_t clips_ptr; ++ uint64_t fence_rep; ++}; ++ ++/*************************************************************************/ ++/** ++ * DRM_VMW_UPDATE_LAYOUT - Update layout ++ * ++ * Updates the preferred modes and connection status for connectors. The ++ * command consists of one drm_vmw_update_layout_arg pointing to an array ++ * of num_outputs drm_vmw_rect's. ++ */ ++ ++/** ++ * struct drm_vmw_update_layout_arg ++ * ++ * @num_outputs: number of active connectors ++ * @rects: pointer to array of drm_vmw_rect cast to an uint64_t ++ * ++ * Input argument to the DRM_VMW_UPDATE_LAYOUT Ioctl. ++ */ ++struct drm_vmw_update_layout_arg { ++ uint32_t num_outputs; ++ uint32_t pad64; ++ uint64_t rects; ++}; ++ ++#endif +-- +1.7.8.6 + |