summaryrefslogtreecommitdiff
path: root/shared-core/nouveau_irq.c
blob: 08bd1da02f2d929ff7e5463fd8f6efd30e78d636 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
/*
 * Copyright (C) 2006 Ben Skeggs.
 *
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining
 * a copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sublicense, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial
 * portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 */

/*
 * Authors:
 *   Ben Skeggs <darktama@iinet.net.au>
 */

#include "drmP.h"
#include "drm.h"
#include "nouveau_drm.h"
#include "nouveau_drv.h"
#include "nouveau_reg.h"
#include "nouveau_swmthd.h"

void
nouveau_irq_preinstall(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;

	/* Master disable */
	NV_WRITE(NV03_PMC_INTR_EN_0, 0);
}

void
nouveau_irq_postinstall(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;

	/* Master enable */
	NV_WRITE(NV03_PMC_INTR_EN_0, NV_PMC_INTR_EN_0_MASTER_ENABLE);
}

void
nouveau_irq_uninstall(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;

	/* Master disable */
	NV_WRITE(NV03_PMC_INTR_EN_0, 0);
}

static void
nouveau_fifo_irq_handler(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	uint32_t status;

	while ((status = NV_READ(NV03_PFIFO_INTR_0))) {
		uint32_t chid, get;

		NV_WRITE(NV03_PFIFO_CACHES, 0);

		chid = NV_READ(NV03_PFIFO_CACHE1_PUSH1) &
				(nouveau_fifo_number(dev) - 1);
		get  = NV_READ(NV03_PFIFO_CACHE1_GET);

		if (status & NV_PFIFO_INTR_CACHE_ERROR) {
			uint32_t mthd, data;
			int ptr;
			
			ptr = get >> 2;
			if (dev_priv->card_type < NV_40) {
				mthd = NV_READ(NV04_PFIFO_CACHE1_METHOD(ptr));
				data = NV_READ(NV04_PFIFO_CACHE1_DATA(ptr));
			} else {
				mthd = NV_READ(NV40_PFIFO_CACHE1_METHOD(ptr));
				data = NV_READ(NV40_PFIFO_CACHE1_DATA(ptr));
			}

			DRM_INFO("PFIFO_CACHE_ERROR - "
				 "Ch %d/%d Mthd 0x%04x Data 0x%08x\n",
				 chid, (mthd >> 13) & 7, mthd & 0x1ffc, data);

			NV_WRITE(NV03_PFIFO_CACHE1_GET, get + 4);
			NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 1);

			status &= ~NV_PFIFO_INTR_CACHE_ERROR;
			NV_WRITE(NV03_PFIFO_INTR_0, NV_PFIFO_INTR_CACHE_ERROR);
		}

		if (status & NV_PFIFO_INTR_DMA_PUSHER) {
			DRM_INFO("PFIFO_DMA_PUSHER - Ch %d\n", chid);

			status &= ~NV_PFIFO_INTR_DMA_PUSHER;
			NV_WRITE(NV03_PFIFO_INTR_0, NV_PFIFO_INTR_DMA_PUSHER);

			NV_WRITE(NV04_PFIFO_CACHE1_DMA_STATE, 0x00000000);
			if (NV_READ(NV04_PFIFO_CACHE1_DMA_PUT) != get)
				NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET, get + 4);
		}

		if (status) {
			DRM_INFO("Unhandled PFIFO_INTR - 0x%08x\n", status);
			NV_WRITE(NV03_PFIFO_INTR_0, status);
		}

		NV_WRITE(NV03_PFIFO_CACHES, 1);
	}

	NV_WRITE(NV03_PMC_INTR_0, NV_PMC_INTR_0_PFIFO_PENDING);
}

struct nouveau_bitfield_names {
	uint32_t mask;
	const char * name;
};

static struct nouveau_bitfield_names nouveau_nstatus_names[] =
{
	{ NV04_PGRAPH_NSTATUS_STATE_IN_USE,       "STATE_IN_USE" },
	{ NV04_PGRAPH_NSTATUS_INVALID_STATE,      "INVALID_STATE" },
	{ NV04_PGRAPH_NSTATUS_BAD_ARGUMENT,       "BAD_ARGUMENT" },
	{ NV04_PGRAPH_NSTATUS_PROTECTION_FAULT,   "PROTECTION_FAULT" }
};

static struct nouveau_bitfield_names nouveau_nstatus_names_nv10[] =
{
	{ NV10_PGRAPH_NSTATUS_STATE_IN_USE,       "STATE_IN_USE" },
	{ NV10_PGRAPH_NSTATUS_INVALID_STATE,      "INVALID_STATE" },
	{ NV10_PGRAPH_NSTATUS_BAD_ARGUMENT,       "BAD_ARGUMENT" },
	{ NV10_PGRAPH_NSTATUS_PROTECTION_FAULT,   "PROTECTION_FAULT" }
};

static struct nouveau_bitfield_names nouveau_nsource_names[] =
{
	{ NV03_PGRAPH_NSOURCE_NOTIFICATION,       "NOTIFICATION" },
	{ NV03_PGRAPH_NSOURCE_DATA_ERROR,         "DATA_ERROR" },
	{ NV03_PGRAPH_NSOURCE_PROTECTION_ERROR,   "PROTECTION_ERROR" },
	{ NV03_PGRAPH_NSOURCE_RANGE_EXCEPTION,    "RANGE_EXCEPTION" },
	{ NV03_PGRAPH_NSOURCE_LIMIT_COLOR,        "LIMIT_COLOR" },
	{ NV03_PGRAPH_NSOURCE_LIMIT_ZETA,         "LIMIT_ZETA" },
	{ NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD,       "ILLEGAL_MTHD" },
	{ NV03_PGRAPH_NSOURCE_DMA_R_PROTECTION,   "DMA_R_PROTECTION" },
	{ NV03_PGRAPH_NSOURCE_DMA_W_PROTECTION,   "DMA_W_PROTECTION" },
	{ NV03_PGRAPH_NSOURCE_FORMAT_EXCEPTION,   "FORMAT_EXCEPTION" },
	{ NV03_PGRAPH_NSOURCE_PATCH_EXCEPTION,    "PATCH_EXCEPTION" },
	{ NV03_PGRAPH_NSOURCE_STATE_INVALID,      "STATE_INVALID" },
	{ NV03_PGRAPH_NSOURCE_DOUBLE_NOTIFY,      "DOUBLE_NOTIFY" },
	{ NV03_PGRAPH_NSOURCE_NOTIFY_IN_USE,      "NOTIFY_IN_USE" },
	{ NV03_PGRAPH_NSOURCE_METHOD_CNT,         "METHOD_CNT" },
	{ NV03_PGRAPH_NSOURCE_BFR_NOTIFICATION,   "BFR_NOTIFICATION" },
	{ NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION, "DMA_VTX_PROTECTION" },
	{ NV03_PGRAPH_NSOURCE_DMA_WIDTH_A,        "DMA_WIDTH_A" },
	{ NV03_PGRAPH_NSOURCE_DMA_WIDTH_B,        "DMA_WIDTH_B" },
};

static void
nouveau_print_bitfield_names(uint32_t value,
                             const struct nouveau_bitfield_names *namelist,
                             const int namelist_len)
{
	int i;
	for(i=0; i<namelist_len; ++i) {
		uint32_t mask = namelist[i].mask;
		if(value & mask) {
			printk(" %s", namelist[i].name);
			value &= ~mask;
		}
	}
	if(value)
		printk(" (unknown bits 0x%08x)", value);
}

static int
nouveau_graph_trapped_channel(struct drm_device *dev, int *channel_ret)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	int channel;

	if (dev_priv->card_type < NV_10) {
		channel = (NV_READ(NV04_PGRAPH_TRAPPED_ADDR) >> 24) & 0xf;
	} else if (dev_priv->card_type < NV_40) {
		channel = (NV_READ(NV04_PGRAPH_TRAPPED_ADDR) >> 20) & 0x1f;
	} else
	if (dev_priv->card_type < NV_50) {
		uint32_t cur_grctx = (NV_READ(0x40032C) & 0xfffff) << 4;

		/* 0x400704 *sometimes* contains a sensible channel ID, but
		 * mostly not.. for now lookup which channel owns the active
		 * PGRAPH context.  Probably a better way, but this'll do
		 * for now.
		 */
		for (channel = 0; channel < 32; channel++) {
			if (dev_priv->fifos[channel] == NULL)
				continue;
			if (cur_grctx ==
			    dev_priv->fifos[channel]->ramin_grctx->instance)
				break;
		}
		if (channel == 32) {
			DRM_ERROR("AIII, unable to determine active channel "
				  "from PGRAPH context 0x%08x\n", cur_grctx);
			return -EINVAL;
		}
	} else {
		uint32_t cur_grctx = (NV_READ(0x40032C) & 0xfffff) << 12;

		for (channel = 0; channel < 128; channel++) {
			if (dev_priv->fifos[channel] == NULL)
				continue;
			if (cur_grctx ==
			    dev_priv->fifos[channel]->ramin_grctx->instance)
				break;
		}
		if (channel == 128) {
			DRM_ERROR("AIII, unable to determine active channel "
				  "from PGRAPH context 0x%08x\n", cur_grctx);
			return -EINVAL;
		}
	}

	if (channel > nouveau_fifo_number(dev) ||
	    dev_priv->fifos[channel] == NULL) {
		DRM_ERROR("AIII, invalid/inactive channel id %d\n", channel);
		return -EINVAL;
	}

	*channel_ret = channel;
	return 0;
}

struct nouveau_pgraph_trap {
	int channel;
	int class;
	int subc, mthd, size;
	uint32_t data, data2;
};

static void
nouveau_graph_trap_info(struct drm_device *dev,
			struct nouveau_pgraph_trap *trap)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	uint32_t address;

	if (nouveau_graph_trapped_channel(dev, &trap->channel))
		trap->channel = -1;
	address = NV_READ(NV04_PGRAPH_TRAPPED_ADDR);

	trap->mthd = address & 0x1FFC;
	trap->data = NV_READ(NV04_PGRAPH_TRAPPED_DATA);
	if (dev_priv->card_type < NV_10) {
		trap->subc  = (address >> 13) & 0x7;
	} else {
		trap->subc  = (address >> 16) & 0x7;
		trap->data2 = NV_READ(NV10_PGRAPH_TRAPPED_DATA_HIGH);
	}

	if (dev_priv->card_type < NV_10) {
		trap->class = NV_READ(0x400180 + trap->subc*4) & 0xFF;
	} else if (dev_priv->card_type < NV_40) {
		trap->class = NV_READ(0x400160 + trap->subc*4) & 0xFFF;
	} else if (dev_priv->card_type < NV_50) {
		trap->class = NV_READ(0x400160 + trap->subc*4) & 0xFFFF;
	} else {
		trap->class = NV_READ(0x400814);
	}
}

static void
nouveau_graph_dump_trap_info(struct drm_device *dev, const char *id,
			     struct nouveau_pgraph_trap *trap)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	uint32_t nsource, nstatus;

	nsource = NV_READ(NV03_PGRAPH_NSOURCE);
	nstatus = NV_READ(NV03_PGRAPH_NSTATUS);

	DRM_INFO("%s - nSource:", id);
	nouveau_print_bitfield_names(nsource, nouveau_nsource_names,
	                             ARRAY_SIZE(nouveau_nsource_names));
	printk(", nStatus:");
	if (dev_priv->card_type < NV_10)
		nouveau_print_bitfield_names(nstatus, nouveau_nstatus_names,
	                             ARRAY_SIZE(nouveau_nstatus_names));
	else
		nouveau_print_bitfield_names(nstatus, nouveau_nstatus_names_nv10,
	                             ARRAY_SIZE(nouveau_nstatus_names_nv10));
	printk("\n");

	DRM_INFO("%s - Ch %d/%d Class 0x%04x Mthd 0x%04x Data 0x%08x:0x%08x\n",
		 id, trap->channel, trap->subc, trap->class, trap->mthd,
		 trap->data2, trap->data);
}

static inline void
nouveau_pgraph_intr_notify(struct drm_device *dev, uint32_t nsource)
{
	struct nouveau_pgraph_trap trap;
	int unhandled = 0;

	nouveau_graph_trap_info(dev, &trap);

	if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
		/* NV4 (nvidia TNT 1) reports software methods with
		 * PGRAPH NOTIFY ILLEGAL_MTHD
		 */
		DRM_DEBUG("Got NV04 software method method %x for class %#x\n",
			  trap.mthd, trap.class);

		if (nouveau_sw_method_execute(dev, trap.class, trap.mthd)) {
			DRM_ERROR("Unable to execute NV04 software method %x "
				  "for object class %x. Please report.\n",
				  trap.mthd, trap.class);
			unhandled = 1;
		}
	} else {
		unhandled = 1;
	}

	if (unhandled)
		nouveau_graph_dump_trap_info(dev, "PGRAPH_NOTIFY", &trap);
}

static inline void
nouveau_pgraph_intr_error(struct drm_device *dev, uint32_t nsource)
{
	struct nouveau_pgraph_trap trap;
	int unhandled = 0;

	nouveau_graph_trap_info(dev, &trap);

	if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
		if (trap.channel >= 0 && trap.mthd == 0x0150) {
			nouveau_fence_handler(dev, trap.channel);
		} else
		if (nouveau_sw_method_execute(dev, trap.class, trap.mthd)) {
			unhandled = 1;
		}
	} else {
		unhandled = 1;
	}

	if (unhandled)
		nouveau_graph_dump_trap_info(dev, "PGRAPH_ERROR", &trap);
}

static inline void
nouveau_pgraph_intr_context_switch(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	uint32_t chid;
	
	chid = NV_READ(NV03_PFIFO_CACHE1_PUSH1) & (nouveau_fifo_number(dev)-1);
	DRM_DEBUG("PGRAPH context switch interrupt channel %x\n", chid);

	switch(dev_priv->card_type) {
	case NV_04:
	case NV_05:
		nouveau_nv04_context_switch(dev);
		break;
	case NV_10:
	case NV_11:
	case NV_17:
		nouveau_nv10_context_switch(dev);
		break;
	default:
		DRM_ERROR("Context switch not implemented\n");
		break;
	}
}

static void
nouveau_pgraph_irq_handler(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	uint32_t status;

	while ((status = NV_READ(NV03_PGRAPH_INTR))) {
		uint32_t nsource = NV_READ(NV03_PGRAPH_NSOURCE);

		if (status & NV_PGRAPH_INTR_NOTIFY) {
			nouveau_pgraph_intr_notify(dev, nsource);

			status &= ~NV_PGRAPH_INTR_NOTIFY;
			NV_WRITE(NV03_PGRAPH_INTR, NV_PGRAPH_INTR_NOTIFY);
		}

		if (status & NV_PGRAPH_INTR_ERROR) {
			nouveau_pgraph_intr_error(dev, nsource);

			status &= ~NV_PGRAPH_INTR_ERROR;
			NV_WRITE(NV03_PGRAPH_INTR, NV_PGRAPH_INTR_ERROR);
		}

		if (status & NV_PGRAPH_INTR_CONTEXT_SWITCH) {
			nouveau_pgraph_intr_context_switch(dev);

			status &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
			NV_WRITE(NV03_PGRAPH_INTR,
				 NV_PGRAPH_INTR_CONTEXT_SWITCH);
		}

		if (status) {
			DRM_INFO("Unhandled PGRAPH_INTR - 0x%08x\n", status);
			NV_WRITE(NV03_PGRAPH_INTR, status);
		}

		if ((NV_READ(NV04_PGRAPH_FIFO) & (1 << 0)) == 0)
			NV_WRITE(NV04_PGRAPH_FIFO, 1);
	}

	NV_WRITE(NV03_PMC_INTR_0, NV_PMC_INTR_0_PGRAPH_PENDING);
}

static void
nouveau_crtc_irq_handler(struct drm_device *dev, int crtc)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;

	if (crtc&1) {
		NV_WRITE(NV_CRTC0_INTSTAT, NV_CRTC_INTR_VBLANK);
	}

	if (crtc&2) {
		NV_WRITE(NV_CRTC1_INTSTAT, NV_CRTC_INTR_VBLANK);
	}
}

irqreturn_t
nouveau_irq_handler(DRM_IRQ_ARGS)
{
	struct drm_device *dev = (struct drm_device*)arg;
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	uint32_t status;

	status = NV_READ(NV03_PMC_INTR_0);
	if (!status)
		return IRQ_NONE;

	if (status & NV_PMC_INTR_0_PFIFO_PENDING) {
		nouveau_fifo_irq_handler(dev);
		status &= ~NV_PMC_INTR_0_PFIFO_PENDING;
	}

	if (status & NV_PMC_INTR_0_PGRAPH_PENDING) {
		nouveau_pgraph_irq_handler(dev);
		status &= ~NV_PMC_INTR_0_PGRAPH_PENDING;
	}

	if (status & NV_PMC_INTR_0_CRTCn_PENDING) {
		nouveau_crtc_irq_handler(dev, (status>>24)&3);
		status &= ~NV_PMC_INTR_0_CRTCn_PENDING;
	}

	if (status)
		DRM_ERROR("Unhandled PMC INTR status bits 0x%08x\n", status);

	return IRQ_HANDLED;
}