/*
* Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved.
* Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sub license,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
* VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef VIA_3D_REG_H
#define VIA_3D_REG_H
#define HC_REG_BASE 0x0400
#define HC_REG_TRANS_SPACE 0x0040
#define HC_ParaN_MASK 0xffffffff
#define HC_Para_MASK 0x00ffffff
#define HC_SubA_MASK 0xff000000
#define HC_SubA_SHIFT 24
/* Transmission Setting
*/
#define HC_REG_TRANS_SET 0x003c
#define HC_ParaSubType_MASK 0xff000000
#define HC_ParaType_MASK 0x00ff0000
#define HC_ParaOS_MASK 0x0000ff00
#define HC_ParaAdr_MASK 0x000000ff
#define HC_ParaSubType_SHIFT 24
#define HC_ParaType_SHIFT 16
#define HC_ParaOS_SHIFT 8
#define HC_ParaAdr_SHIFT 0
#define HC_ParaType_CmdVdata 0x0000
#define HC_ParaType_NotTex 0x0001
#define HC_ParaType_Tex 0x0002
#define HC_ParaType_Palette 0x0003
#define HC_ParaType_PreCR 0x0010
#define HC_ParaType_Auto 0x00fe
/* Transmission Space
*/
#define HC_REG_Hpara0 0x0040
#define HC_REG_HpataAF 0x02fc
/* Read
*/
#define HC_REG_HREngSt 0x0000
#define HC_REG_HRFIFOempty 0x0004
#define HC_REG_HRFIFOfull 0x0008
#define HC_REG_HRErr 0x000c
#define HC_REG_FIFOstatus 0x0010
/* HC_REG_HREngSt 0x0000
*/
#define HC_HDASZC_MASK 0x00010000
#define HC_HSGEMI_MASK 0x0000f000
#define HC_HLGEMISt_MASK 0x00000f00
#define HC_HCRSt_MASK 0x00000080
#define HC_HSE0St_MASK 0x00000040
#define HC_HSE1St_MASK 0x00000020
#define HC_HPESt_MASK 0x00000010
#define HC_HXESt_MASK 0x00000008
#define HC_HBESt_MASK 0x00000004
#define HC_HE2St_MASK 0x00000002
#define HC_HE3St_MASK 0x00000001
/* HC_REG_HRFIFOempty 0x0004
*/
#define HC_HRZDempty_MASK 0x00000010
#define HC_HRTXAempty_MASK 0x00000008
#define HC_HRTXDempty_MASK 0x00000004
#define HC_HWZDempty_MASK 0x00000002
#define HC_HWCDempty_MASK 0x00000001
/* HC_REG_HRFIFOfull 0x0008
*/
#define HC_HRZDfull_MASK 0x00000010
#define HC_HRTXAfull_MASK 0x00000008
#define HC_HRTXDfull_MASK 0x00000004
#define HC_HWZDfull_MASK 0x00000002
#define HC_HWCDfull_MASK 0x00000001
/* HC_REG_HRErr 0x000c
*/
#define HC_HAGPCMErr_MASK 0x80000000
#define HC_HAGPCMErrC_MASK 0x70000000
/* HC_REG_FIFOstatus 0x0010
*/
#define HC_HRFIFOATall_MASK 0x80000000
#define HC_HRFIFOATbusy_MASK 0x40000000
#define HC_HRATFGMDo_MASK 0x00000100
#define HC_HRATFGMDi_MASK 0x00000080
#define HC_HRATFRZD_MASK 0x00000040
#define HC_HRATFRTXA_MASK 0x00000020
#define HC_HRATFRTXD_MASK 0x00000010
#define HC_HRATFWZD_MASK 0x00000008
#define HC_HRATFWCD_MASK 0x00000004
#define HC_HRATTXTAG_MASK 0x00000002
#define HC_HRATTXCH_MASK 0x00000001
/* AGP Command Setting
*/
#define HC_SubA_HAGPBstL 0x0060
#define HC_SubA_HAGPBendL 0x0061
#define HC_SubA_HAGPCMNT 0x0062
#define HC_SubA_HAGPBpL 0x0063
#define HC_SubA_HAGPBpH 0x0064
/* HC_SubA_HAGPCMNT 0x0062
*/
#define HC_HAGPCMNT_MASK 0x00800000
#define HC_HCmdErrClr_MASK 0x00400000
#define HC_HAGPBendH_MASK 0x0000ff00
#define HC_HAGPBstH_MASK 0x000000ff
#define HC_HAGPBendH_SHIFT 8
#define HC_HAGPBstH_SHIFT 0
/* HC_SubA_HAGPBpL 0x0063
*/
#define HC_HAGPBpL_MASK 0x00fffffc
#define HC_HAGPBpID_MASK 0x00000003
#define HC_HAGPBpID_PAUSE 0x00000000
#define HC_HAGPBpID_JUMP 0x00000001
#define HC_HAGPBpID_STOP 0x00000002
/* HC_SubA_HAGPBpH 0x0064
*/
#define HC_HAGPBpH_MASK 0x00ffffff
/* Miscellaneous Settings
*/
#define HC_SubA_HClipTB 0x0070
#define HC_SubA_HClipLR 0x0071
#define HC_SubA_HFPClipTL 0x0072
#define HC_SubA_HFPClipBL 0x0073
#define HC_SubA_HFPClipLL 0x0074
#define HC_SubA_HFPClipRL 0x0075
#define HC_SubA_HFPClipTBH 0x0076
#define HC_SubA_HFPClipLRH 0x0077
#define HC_SubA_HLP 0x0078
#define HC_SubA_HLPRF 0x0079
#define HC_SubA_HSolidCL 0x007a
#define HC_SubA_HPixGC 0x007b
#define HC_SubA_HSPXYOS 0x007c
#define HC_SubA_HVertexCNT 0x007d
#define HC_HClipT_MASK 0x00fff000
#define HC_HClipT_SHIFT 12
#define HC_HClipB_MASK 0x00000fff
#define HC_HClipB_SHIFT 0
#define HC_HClipL_MASK 0x00fff000
#define HC_HClipL_SHIFT 12
#define HC_HClipR_MASK 0x00000fff
#define HC_HClipR_SHIFT 0
#define HC_HFPClipBH_MASK 0x0000ff00
#define HC_HFPClipBH_SHIFT 8
#define HC_HFPClipTH_MASK 0x000000ff
#define HC_HFPClipTH_SHIFT 0
#define HC_HFPClipRH_MASK 0x0000ff00
#define HC_HFPClipRH_SHIFT 8
#define HC_HFPClipLH_MASK 0x000000ff
#define HC_HFPClipLH_SHIFT 0
#define HC_HSolidCH_MASK 0x000000ff
#define HC_HPixGC_MASK 0x00800000
#define HC_HSPXOS_MASK 0x00fff000
#define HC_HSPXOS_SHIFT 12
#define HC_HSPYOS_MASK 0x00000fff
/* Command
* Command A
*/
#define HC_HCmdHeader_MASK 0xfe000000 /*0xffe00000 */
#define HC_HE3Fire_MASK 0x00100000
#define HC_HPMType_MASK 0x000f0000
#define HC_HEFlag_MASK 0x0000e000
#define HC_HShading_MASK 0x00001c00
#define HC_HPMValidN_MASK 0x00000200
#define HC_HPLEND_MASK 0x00000100
#define HC_HVCycle_MASK 0x000000ff
#define HC_HVCycle_Style_MASK 0x000000c0
#define HC_HVCycle_ChgA_MASK 0x00000030
#define HC_HVCycle_ChgB_MASK 0x0000000c
#define HC_HVCycle_ChgC_MASK 0x00000003
#define HC_HPMType_Point 0x00000000
#define HC_HPMType_Line 0x00010000
#define HC_HPMType_Tri 0x00020000
#define HC_HPMType_TriWF 0x00040000
#define HC_HEFlag_NoAA 0x00000000
#define HC_HEFlag_ab 0x00008000
#define HC_HEFlag_bc 0x00004000
#define HC_HEFlag_ca 0x00002000
#define HC_HShading_Solid 0x00000000
#define HC_HShading_FlatA 0x00000400
#define HC_HShading_FlatB 0x00000800
#define HC_HShading_FlatC 0x00000c00
#define HC_HShading_Gouraud 0x00001000
#define HC_HVCycle_Full 0x00000000
#define HC_HVCycle_AFP 0x00000040
#define HC_HVCycle_One 0x000000c0
#define HC_HVCycle_NewA 0x00000000
#define HC_HVCycle_AA 0x00000010
#define HC_HVCycle_AB 0x00000020
#define HC_HVCycle_AC 0x00000030
#define HC_HVCycle_NewB 0x00000000
#define HC_HVCycle_BA 0x00000004
#define HC_HVCycle_BB 0x00000008
#define HC_HVCycle_BC 0x0000000c
#define HC_HVCycle_NewC 0x00000000
#define HC_HVCycle_CA 0x00000001
#define HC_HVCycle_CB 0x00000002
#define HC_HVCycle_CC 0x00000003
/* Command B
*/
#define HC_HLPrst_MASK 0x00010000
#define HC_HLLastP_MASK 0x00008000
#define HC_HVPMSK_MASK 0x00007f80
#define HC_HBFace_MASK 0x00000040
#define HC_H2nd1VT_MASK 0x0000003f
#define HC_HVPMSK_X 0x00004000
#define HC_HVPMSK_Y 0x00002000
#define HC_HVPMSK_Z 0x00001000
#define HC_HVPMSK_W 0x00000800
#define HC_HVPMSK_Cd 0x00000400
#define HC_HVPMSK_Cs 0x00000200
#define HC_HVPMSK_S 0x00000100
#define HC_HVPMSK_T 0x00000080
/* Enable Setting
*/
#define HC_SubA_HEnable 0x0000
#define HC_HenTXEnvMap_MASK 0x00200000
#define HC_HenVertexCNT_MASK 0x00100000
#define HC_HenCPUDAZ_MASK 0x00080000
#define HC_HenDASZWC_MASK 0x00040000
#define HC_HenFBCull_MASK 0x00020000
#define HC_HenCW_MASK 0x00010000
#define HC_HenAA_MASK 0x00008000
#define HC_HenST_MASK 0x00004000
#define HC_HenZT_MASK 0x00002000
#define HC_HenZW_MASK 0x00001000
#define HC_HenAT_MASK 0x00000800
#define HC_HenAW_MASK 0x00000400
#define HC_HenSP_MASK 0x00000200
#define HC_HenLP_MASK 0x00000100
#define HC_HenTXCH_MASK 0x00000080
#define HC_HenTXMP_MASK 0x00000040
#define HC_HenTXPP_MASK 0x00000020
#define HC_HenTXTR_MASK 0x00000010
#define HC_HenCS_MASK 0x00000008
#define HC_HenFOG_MASK 0x00000004
#define HC_HenABL_MASK 0x00000002
#define HC_HenDT_MASK 0x00000001
/* Z Setting
*/
#define HC_SubA_HZWBBasL 0x0010
#define HC_SubA_HZWBBasH 0x0011
#define HC_SubA_HZWBType 0x0012
#define HC_SubA_HZBiasL 0x0013
#define HC_SubA_HZWBend 0x0014
#define HC_SubA_HZWTMD 0x0015
#define HC_SubA_HZWCDL 0x0016
#define HC_SubA_HZWCTAGnum 0x0017
#define HC_SubA_HZCYNum 0x0018
#define HC_SubA_HZWCFire 0x0019
/* HC_SubA_HZWBType
*/
#define HC_HZWBType_MASK 0x00800000
#define HC_HZBiasedWB_MASK 0x00400000
#define HC_HZONEasFF_MASK 0x00200000
#define HC_HZOONEasFF_MASK 0x00100000
#define HC_HZWBFM_MASK 0x00030000
#define HC_HZWBLoc_MASK 0x0000c000
#define HC_HZWBPit_MASK 0x00003fff
#define HC_HZWBFM_16 0x00000000
#define HC_HZWBFM_32 0x00020000
#define HC_HZWBFM_24 0x00030000
#define HC_HZWBLoc_Local 0x00000000
#define HC_HZWBLoc_SyS 0x00004000
/* HC_SubA_HZWBend
*/
#define HC_HZWBend_MASK 0x00ffe000
#define HC_HZBiasH_MASK 0x000000ff
#define HC_HZWBend_SHIFT 10
/* HC_SubA_HZWTMD
*/
#define HC_HZWTMD_MASK 0x00070000
#define HC_HEBEBias_MASK 0x00007f00
#define HC_HZNF_MASK 0x000000ff
#define HC_HZWTMD_NeverPass 0x00000000
#define HC_HZWTMD_LT 0x00010000
#define HC_HZWTMD_EQ 0x00020000
#define HC_HZWTMD_LE 0x00030000
#define HC_HZWTMD_GT 0x00040000
#define HC_HZWTMD_NE 0x00050000
#define HC_HZWTMD_GE 0x00060000
#define HC_HZWTMD_AllPass 0x00070000
#define HC_HEBEBias_SHIFT 8
/* HC_SubA_HZWCDL 0x0016
*/
#define HC_HZWCDL_MASK 0x00ffffff
/* HC_SubA_HZWCTAGnum 0x0017
*/
#define HC_HZWCTAGnum_MASK 0x00ff0000
#define HC_HZWCTAGnum_SHIFT 16
#define HC_HZWCDH_MASK 0x000000ff
#define HC_HZWCDH_SHIFT 0
/* HC_SubA_HZCYNum 0x0018
*/
#define HC_HZCYNum_MASK 0x00030000
#define HC_HZCYNum_SHIFT 16
#define HC_HZWCQWnum_MASK 0x00003fff
#define HC_HZWCQWnum_SHIFT 0
/* HC_SubA_HZWCFire 0x0019
*/
#define HC_ZWCFire_MASK 0x00010000
#define HC_HZWCQWnumLast_MASK 0x00003fff
#define HC_HZWCQWnumLast_SHIFT 0
/* Stencil Setting
*/
#define HC_SubA_HSTREF 0x0023
#define HC_SubA_HSTMD 0x0024
/* HC_SubA_HSBFM
*/
#define HC_HSBFM_MASK 0x00030000
#define HC_HSBLoc_MASK 0x0000c000
#define HC_HSBPit_MASK 0x00003fff
/* HC_SubA_HSTREF
*/
#define HC_HSTREF_MASK 0x00ff0000
#define HC_HSTOPMSK_MASK 0x0000ff00
#define HC_HSTBMSK_MASK 0x000000ff
#define HC_HSTREF_SHIFT 16
#define HC_HSTOPMSK_SHIFT 8
/* HC_SubA_HSTMD
*/
#define HC_HSTMD_MASK 0x00070000
#define HC_HSTOPSF_MASK 0x000001c0
#define HC_HSTOPSPZF_MASK 0x00000038
#define HC_HSTOPSPZP_MASK 0x00000007
#define HC_HSTMD_NeverPass 0x00000000
#define HC_HSTMD_LT 0x00010000
#define HC_HSTMD_EQ 0x00020000
#define HC_HSTMD_LE 0x00030000
#define HC_HSTMD_GT 0x00040000
#define HC_HSTMD_NE 0x00050000
#define HC_HSTMD_GE 0x00060000
#define HC_HSTMD_AllPass 0x00070000
#define HC_HSTOPSF_KEEP 0x00000000
#define HC_HSTOPSF_ZERO 0x00000040
#define HC_HSTOPSF_REPLACE 0x00000080
#define HC_HSTOPSF_INCRSAT 0x000000c0
#define HC_HSTOPSF_DECRSAT 0x00000100
#define HC_HSTOPSF_INVERT 0x00000140
#define HC_HSTOPSF_INCR 0x00000180
#define HC_HSTOPSF_DECR 0x000001c0
#define HC_HSTOPSPZF_KEEP 0x00000000
#define HC_HSTOPSPZF_ZERO 0x00000008
#define HC_HSTOPSPZF_REPLACE 0x00000010
#define HC_HSTOPSPZF_INCRSAT 0x00000018
#define HC_HSTOPSPZF_DECRSAT 0x00000020
#define HC_HSTOPSPZF_INVERT 0x00000028
#define HC_HSTOPSPZF_INCR 0x00000030
#define HC_HSTOPSPZF_DECR 0x00000038
#define HC_HSTOPSPZP_KEEP 0x00000000
#define HC_HSTOPSPZP_ZERO 0x00000001
#define HC_HSTOPSPZP_REPLACE 0x00000002
#define HC_HSTOPSPZP_INCRSAT 0x00000003
#define HC_HSTOPSPZP_DECRSAT 0x00000004
#define HC_HSTOPSPZP_INVERT 0x00000005
#define HC_HSTOPSPZP_INCR 0x00000006
#define HC_HSTOPSPZP_DECR 0x00000007
/* Alpha Setting
*/
#define HC_SubA_HABBasL 0x0030
#define HC_SubA_HABBasH 0x0031
#define HC_SubA_HABFM 0x0032
#define HC_SubA_HATMD 0x0033
#define HC_SubA_HABLCsat 0x0034
#define HC_SubA_HABLCop 0x0035
#define HC_SubA_HABLAsat 0x0036
#define HC_SubA_HABLAop 0x0037
#define HC_SubA_HABLRCa 0x0038
#define HC_SubA_HABLRFCa 0x0039
#define HC_SubA_HABLRCbias 0x003a
#define HC_SubA_HABLRCb 0x003b
#define HC_SubA_HABLRFCb 0x003c
#define HC_SubA_HABLRAa 0x003d
#define HC_SubA_HABLRAb 0x003e
/* HC_SubA_HABFM
*/
#define HC_HABFM_MASK 0x00030000
#define HC_HABLoc_MASK 0x0000c000
#define HC_HABPit_MASK 0x000007ff
/* HC_SubA_HATMD
*/
#define HC_HATMD_MASK 0x00000700
#define HC_HATREF_MASK 0x000000ff
#define HC_HATMD_NeverPass 0x00000000
#define HC_HATMD_LT 0x00000100
#define HC_HATMD_EQ 0x00000200
#define HC_HATMD_LE 0x00000300
#define HC_HATMD_GT 0x00000400
#define HC_HATMD_NE 0x00000500
#define HC_HATMD_GE 0x00000600
#define HC_HATMD_AllPass 0x00000700
/* HC_SubA_HABLCsat
*/
#define HC_HABLCsat_MASK 0x00010000
#define HC_HABLCa_MASK 0x0000fc00
#define HC_HABLCa_C_MASK 0x0000c000
#define HC_HABLCa_OPC_MASK 0x00003c00
#define HC_HABLFCa_MASK 0x000003f0
#define HC_HABLFCa_C_MASK 0x00000300
#define HC_HABLFCa_OPC_MASK 0x000000f0
#define HC_HABLCbias_MASK 0x0000000f
#define HC_HABLCbias_C_MASK 0x00000008
#define HC_HABLCbias_OPC_MASK 0x00000007
/*-- Define the input color.
*/
#define HC_XC_Csrc 0x00000000
#define HC_XC_Cdst 0x00000001
#define HC_XC_Asrc 0x00000002
#define HC_XC_Adst 0x00000003
#define HC_XC_Fog 0x00000004
#define HC_XC_HABLRC 0x00000005
#define HC_XC_minSrcDst 0x00000006
#define HC_XC_maxSrcDst 0x00000007
#define HC_XC_mimAsrcInvAdst 0x00000008
#define HC_XC_OPC 0x00000000
#define HC_XC_InvOPC 0x00000010
#define HC_XC_OPCp5 0x00000020
/*-- Define the input Alpha
*/
#define HC_XA_OPA 0x00000000
#define HC_XA_InvOPA 0x00000010
#define HC_XA_OPAp5 0x00000020
#define HC_XA_0 0x00000000
#define HC_XA_Asrc 0x00000001
#define HC_XA_Adst 0x00000002
#define HC_XA_Fog 0x00000003
#define HC_XA_minAsrcFog 0x00000004
#define HC_XA_minAsrcAdst 0x00000005
#define HC_XA_maxAsrcFog 0x00000006
#define HC_XA_maxAsrcAdst 0x00000007
#define HC_XA_HABLRA 0x00000008
#define HC_XA_minAsrcInvAdst 0x00000008
#define HC_XA_HABLFRA 0x00000009
/*--
*/
#define HC_HABLCa_OPC (HC_XC_OPC << 10)
#define HC_HABLCa_InvOPC (HC_XC_InvOPC << 10)
#define HC_HABLCa_OPCp5 (HC_XC_OPCp5 << 10)
#define HC_HABLCa_Csrc (HC_XC_Csrc << 10)
#define HC_HABLCa_Cdst (HC_XC_Cdst << 10)
#define HC_HABLCa_Asrc (HC_XC_Asrc << 10)
#define HC_HABLCa_Adst (HC_XC_Adst << 10)
#define HC_HABLCa_Fog (HC_XC_Fog << 10)
#define HC_HABLCa_HABLRCa (HC_XC_HABLRC << 10)
#define HC_HABLCa_minSrcDst (HC_XC_minSrcDst << 10)
#define HC_HABLCa_maxSrcDst (HC_XC_maxSrcDst << 10)
#define HC_HABLFCa_OPC (HC_XC_OPC << 4)
#define HC_HABLFCa_InvOPC (HC_XC_InvOPC << 4)
#define HC_HABLFCa_OPCp5 (HC_XC_OPCp5 << 4)
#define HC_HABLFCa_Csrc (HC_XC_Csrc << 4)
#define HC_HABLFCa_Cdst (HC_XC_Cdst << 4)
#define HC_HABLFCa_Asrc (HC_XC_Asrc << 4)
#define HC_HABLFCa_Adst (HC_XC_Adst << 4)
#define HC_HABLFCa_Fog (HC_XC_Fog << 4)
#define HC_HABLFCa_HABLRCa (HC_XC_HABLRC << 4)
#define HC_HABLFCa_minSrcDst (HC_XC_minSrcDst << 4)
#define HC_HABLFCa_maxSrcDst (HC_XC_maxSrcDst << 4)
#define HC_HABLFCa_mimAsrcInvAdst (HC_XC_mimAsrcInvAdst << 4)
#define HC_HABLCbias_HABLRCbias 0x00000000
#define HC_HABLCbias_Asrc 0x00000001
#define HC_HABLCbias_Adst 0x00000002
#define HC_HABLCbias_Fog 0x00000003
#define HC_HABLCbias_Cin 0x00000004
/* HC_SubA_HABLCop 0x0035
*/
#define HC_HABLdot_MASK 0x00010000
#define HC_HABLCop_MASK 0x00004000
#define HC_HABLCb_MASK 0x00003f00
#define HC_HABLCb_C_MASK 0x00003000
#define HC_HABLCb_OPC_MASK 0x00000f00
#define HC_HABLFCb_MASK 0x000000fc
#define HC_HABLFCb_C_MASK 0x000000c0
#define HC_HABLFCb_OPC_MASK 0x0000003c
#define HC_HABLCshift_MASK 0x00000003
#define HC_HABLCb_OPC (HC_XC_OPC << 8)
#define HC_HABLCb_InvOPC (HC_XC_InvOPC << 8)
#define HC_HABLCb_OPCp5 (HC_XC_OPCp5 << 8)
#define HC_HABLCb_Csrc (HC_XC_Csrc << 8)
#define HC_HABLCb_Cdst (HC_XC_Cdst << 8)
#define HC_HABLCb_Asrc (HC_XC_Asrc << 8)
#define HC_HABLCb_Adst (HC_XC_Adst << 8)
#define HC_HABLCb_Fog (HC_XC_Fog << 8)
#define HC_HABLCb_HABLRCa (HC_XC_HABLRC << 8)
#define HC_HABLCb_minSrcDst (HC_XC_minSrcDst << 8)
#define HC_HABLCb_maxSrcDst (HC_XC_maxSrcDst << 8)
#define HC_HABLFCb_OPC (HC_XC_OPC << 2)
#define HC_HABLFCb_InvOPC (HC_XC_InvOPC << 2)
#define HC_HABLFCb_OPCp5 (HC_XC_OPCp5 << 2)
#define HC_HABLFCb_Csrc (HC_XC_Csrc << 2)
#define HC_HABLFCb_Cdst (HC_XC_Cdst << 2)
#define HC_HABLFCb_Asrc (HC_XC_Asrc << 2)
#define HC_HABLFCb_Adst (HC_XC_Adst << 2)
#define HC_HABLFCb_Fog (HC_XC_Fog << 2)
#define HC_HABLFCb_HABLRCb (HC_XC_HABLRC << 2)
#define HC_HABLFCb_minSrcDst (HC_XC_minSrcDst << 2)
#define HC_HABLFCb_maxSrcDst (HC_XC_maxSrcDst << 2)
#define HC_HABLFCb_mimAsrcInvAdst (HC_XC_mimAsrcInvAdst << 2)
/* HC_SubA_HABLAsat 0x0036
*/
#define HC_HABLAsat_MASK 0x00010000
#define HC_HABLAa_MASK 0x0000fc00
#define HC_HABLAa_A_MASK 0x0000c000
#define HC_HABLAa_OPA_MASK 0x00003c00
#define HC_HABLFAa_MASK 0x000003f0
#define HC_HABLFAa_A_MASK 0x00000300
#define HC_HABLFAa_OPA_MASK 0x000000f0
#define HC_HABLAbias_MASK 0x0000000f
#define HC_HABLAbias_A_MASK 0x00000008
#define HC_HABLAbias_OPA_MASK 0x00000007
#define HC_HABLAa_OPA (HC_XA_OPA << 10)
#define HC_HABLAa_InvOPA (HC_XA_InvOPA << 10)
#define HC_HABLAa_OPAp5 (HC_XA_OPAp5 << 10)
#define HC_HABLAa_0 (HC_XA_0 << 10)
#define HC_HABLAa_Asrc (HC_XA_Asrc << 10)
#define HC_HABLAa_Adst (HC_XA_Adst << 10)
#define HC_HABLAa_Fog (HC_XA_Fog << 10)
#define HC_HABLAa_minAsrcFog (HC_XA_minAsrcFog << 10)
#define HC_HABLAa_minAsrcAdst (HC_XA_minAsrcAdst << 10)
#define HC_HABLAa_maxAsrcFog (HC_XA_maxAsrcFog << 10)
#define HC_HABLAa_maxAsrcAdst (HC_XA_maxAsrcAdst << 10)
#define HC_HABLAa_HABLRA (HC_XA_HABLRA << 10)
#define HC_HABLFAa_OPA (HC_XA_OPA << 4)
#define HC_HABLFAa_InvOPA (HC_XA_InvOPA << 4)
#define HC_HABLFAa_OPAp5 (HC_XA_OPAp5 << 4)
#define HC_HABLFAa_0 (HC_XA_0 << 4)
#define HC_HABLFAa_Asrc (HC_XA_Asrc << 4)
#define HC_HABLFAa_Adst (HC_XA_Adst << 4)
#define HC_HABLFAa_Fog (HC_XA_Fog << 4)
#define HC_HABLFAa_minAsrcFog (HC_XA_minAsrcFog << 4)
#define HC_HABLFAa_minAsrcAdst (HC_XA_minAsrcAdst << 4)
#define HC_HABLFAa_maxAsrcFog (HC_XA_maxAsrcFog << 4)
#define HC_HABLFAa_maxAsrcAdst (HC_XA_maxAsrcAdst << 4)
#define HC_HABLFAa_minAsrcInvAdst (HC_XA_minAsrcInvAdst << 4)
#define HC_HABLFAa_HABLFRA (HC_XA_HABLFRA << 4)
#define HC_HABLAbias_HABLRAbias 0x00000000
#define HC_HABLAbias_Asrc 0x00000001
#define HC_HABLAbias_Adst 0x00000002
#define HC_HABLAbias_Fog 0x00000003
#define HC_HABLAbias_Aaa 0x00000004
/* HC_SubA_HABLA/*
* Copyright 2005-2006 Stephane Marchesin
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include "drmP.h"
#include "drm.h"
#include "nouveau_drv.h"
#include "nouveau_drm.h"
/* returns the number of hw fifos */
int nouveau_fifo_number(struct drm_device *dev)
{
struct drm_nouveau_private *dev_priv=dev->dev_private;
switch(dev_priv->card_type)
{
case NV_04:
case NV_05:
return 16;
case NV_50:
return 128;
default:
return 32;
}
}
/* returns the size of fifo context */
int nouveau_fifo_ctx_size(struct drm_device *dev)
{
struct drm_nouveau_private *dev_priv=dev->dev_private;
if (dev_priv->card_type >= NV_40)
return 128;
else if (dev_priv->card_type >= NV_17)
return 64;
else
return 32;
}
/***********************************
* functions doing the actual work
***********************************/
/* voir nv_xaa.c : NVResetGraphics
* mémoire mappée par nv_driver.c : NVMapMem
* voir nv_driver.c : NVPreInit
*/
static int nouveau_fifo_instmem_configure(struct drm_device *dev)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
NV_WRITE(NV03_PFIFO_RAMHT,
(0x03 << 24) /* search 128 */ |
((dev_priv->ramht_bits - 9) << 16) |
(dev_priv->ramht_offset >> 8)
);
NV_WRITE(NV03_PFIFO_RAMRO, dev_priv->ramro_offset>>8);
switch(dev_priv->card_type)
{
case NV_50:
case NV_40:
switch (dev_priv->chipset) {
case 0x47:
case 0x49:
case 0x4b:
NV_WRITE(0x2230, 1);
break;
default:
break;
}
NV_WRITE(NV40_PFIFO_RAMFC, 0x30002);
break;
case NV_44:
NV_WRITE(NV40_PFIFO_RAMFC, ((nouveau_mem_fb_amount(dev)-512*1024+dev_priv->ramfc_offset)>>16) |
(2 << 16));
break;
case NV_30:
case NV_20:
case NV_17:
NV_WRITE(NV03_PFIFO_RAMFC, (dev_priv->ramfc_offset>>8) |
(1 << 16) /* 64 Bytes entry*/);
/* XXX nvidia blob set bit 18, 21,23 for nv20 & nv30 */
break;
case NV_11:
case NV_10:
case NV_04:
NV_WRITE(NV03_PFIFO_RAMFC, dev_priv->ramfc_offset>>8);
break;
}
return 0;
}
int nouveau_fifo_init(struct drm_device *dev)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
int ret;
NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) &
~NV_PMC_ENABLE_PFIFO);
NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) |
NV_PMC_ENABLE_PFIFO);
/* Enable PFIFO error reporting */
NV_WRITE(NV03_PFIFO_INTR_0, 0xFFFFFFFF);
NV_WRITE(NV03_PFIFO_INTR_EN_0, 0xFFFFFFFF);
NV_WRITE(NV03_PFIFO_CACHES, 0x00000000);
ret = nouveau_fifo_instmem_configure(dev);
if (ret) {
DRM_ERROR("Failed to configure instance memory\n");
return ret;
}
/* FIXME remove all the stuff that's done in nouveau_fifo_alloc */
DRM_DEBUG("Setting defaults for remaining PFIFO regs\n");
/* All channels into PIO mode */
NV_WRITE(NV04_PFIFO_MODE, 0x00000000);
NV_WRITE(NV03_PFIFO_CACHE1_PUSH0, 0x00000000);
NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000000);
/* Channel 0 active, PIO mode */
NV_WRITE(NV03_PFIFO_CACHE1_PUSH1, 0x00000000);
/* PUT and GET to 0 */
NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUT, 0x00000000);
NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET, 0x00000000);
/* No cmdbuf object */
NV_WRITE(NV04_PFIFO_CACHE1_DMA_INSTANCE, 0x00000000);
NV_WRITE(NV03_PFIFO_CACHE0_PUSH0, 0x00000000);
NV_WRITE(NV03_PFIFO_CACHE0_PULL0, 0x00000000);
NV_WRITE(NV04_PFIFO_SIZE, 0x0000FFFF);
NV_WRITE(NV04_PFIFO_CACHE1_HASH, 0x0000FFFF);
NV_WRITE(NV04_PFIFO_CACHE0_PULL1, 0x00000001);
NV_WRITE(NV04_PFIFO_CACHE1_DMA_CTL, 0x00000000);
NV_WRITE(NV04_PFIFO_CACHE1_DMA_STATE, 0x00000000);
NV_WRITE(NV04_PFIFO_CACHE1_ENGINE, 0x00000000);
NV_WRITE(NV04_PFIFO_CACHE1_DMA_FETCH, NV_PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES |
NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4 |
#ifdef __BIG_ENDIAN
NV_PFIFO_CACHE1_BIG_ENDIAN |
#endif
0x00000000);
NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUSH, 0x00000001);
NV_WRITE(NV03_PFIFO_CACHE1_PUSH0, 0x00000001);
NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000001);
NV_WRITE(NV04_PFIFO_CACHE1_PULL1, 0x00000001);
/* FIXME on NV04 */
if (dev_priv->card_type >= NV_10) {
NV_WRITE(NV10_PGRAPH_CTX_USER, 0x0);
NV_WRITE(NV04_PFIFO_DELAY_0, 0xff /* retrycount*/ );
if (dev_priv->card_type >= NV_40)
NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x00002001);
else
NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10110000);
} else {
NV_WRITE(NV04_PGRAPH_CTX_USER, 0x0);
NV_WRITE(NV04_PFIFO_DELAY_0, 0xff /* retrycount*/ );
NV_WRITE(NV04_PGRAPH_CTX_CONTROL, 0x10110000);
}
NV_WRITE(NV04_PFIFO_DMA_TIMESLICE, 0x001fffff);
NV_WRITE(NV03_PFIFO_CACHES, 0x00000001);
return 0;
}
static int
nouveau_fifo_pushbuf_ctxdma_init(struct nouveau_channel *chan)
{
struct drm_device *dev = chan->dev;
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct mem_block *pb = chan->pushbuf_mem;
struct nouveau_gpuobj *pushbuf = NULL;
int ret;
if (pb->flags & NOUVEAU_MEM_AGP) {
ret = nouveau_gpuobj_gart_dma_new(chan, pb->start, pb->size,
NV_DMA_ACCESS_RO,
&pushbuf,
&chan->pushbuf_base);
} else
if (pb->flags & NOUVEAU_MEM_PCI) {
ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
pb->start, pb->size,
NV_DMA_ACCESS_RO,
NV_DMA_TARGET_PCI_NONLINEAR,
&pushbuf);
chan->pushbuf_base = 0;
} else if (dev_priv->card_type != NV_04) {
ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
pb->start, pb->size,
NV_DMA_ACCESS_RO,
NV_DMA_TARGET_VIDMEM, &pushbuf);
chan->pushbuf_base = 0;
} else {
/* NV04 cmdbuf hack, from original ddx.. not sure of it's
* exact reason for existing :) PCI access to cmdbuf in
* VRAM.
*/
ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
pb->start +
drm_get_resource_start(dev, 1),
pb->size, NV_DMA_ACCESS_RO,
NV_DMA_TARGET_PCI, &pushbuf);
chan->pushbuf_base = 0;
}
if ((ret = nouveau_gpuobj_ref_add(dev, chan, 0, pushbuf,
&chan->pushbuf))) {
DRM_ERROR("Error referencing push buffer ctxdma: %d\n", ret);
if (pushbuf != dev_priv->gart_info.sg_ctxdma)
nouveau_gpuobj_del(dev, &pushbuf);
return ret;
}
return 0;
}
static struct mem_block *
nouveau_fifo_user_pushbuf_alloc(struct drm_device *dev)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nouveau_config *config = &dev_priv->config;
struct mem_block *pb;
int pb_min_size = max(NV03_FIFO_SIZE,PAGE_SIZE);
/* Defaults for unconfigured values */
if (!config->cmdbuf.location)
config->cmdbuf.location = NOUVEAU_MEM_FB;
if (!config->cmdbuf.size || config->cmdbuf.size < pb_min_size)
config->cmdbuf.size = pb_min_size;
pb = nouveau_mem_alloc(dev, 0, config->cmdbuf.size,
config->cmdbuf.location | NOUVEAU_MEM_MAPPED,
(struct drm_file *)-2);
if (!pb)
DRM_ERROR("Couldn't allocate DMA push buffer.\n");
return pb;
}
/* allocates and initializes a fifo for user space consumption */
int
nouveau_fifo_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret,
struct drm_file *file_priv, struct mem_block *pushbuf,
uint32_t vram_handle, uint32_t tt_handle)
{
int ret;
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nouveau_engine *engine = &dev_priv->Engine;
struct nouveau_channel *chan;
int channel;
/*
* Alright, here is the full story
* Nvidia cards have multiple hw fifo contexts (praise them for that,
* no complicated crash-prone context switches)
* We allocate a new context for each app and let it write to it directly
* (woo, full userspace command submission !)
* When there are no more contexts, you lost
*/
for(channel=0; channel<nouveau_fifo_number(dev); channel++) {
if (dev_priv->fifos[channel] == NULL)
break;
}
/* no more fifos. you lost. */
if (channel==nouveau_fifo_number(dev))
return -EINVAL;
dev_priv->fifos[channel] = drm_calloc(1, sizeof(struct nouveau_channel),
DRM_MEM_DRIVER);
if (!dev_priv->fifos[channel])
return -ENOMEM;
dev_priv->fifo_alloc_count++;
chan = dev_priv->fifos[channel];
chan->dev = dev;
chan->id = channel;
chan->file_priv = file_priv;
chan->pushbuf_mem = pushbuf;
DRM_INFO("Allocating FIFO number %d\n", channel);
/* Allocate space for per-channel fixed notifier memory */
ret = nouveau_notifier_init_channel(chan);
if (ret) {
nouveau_fifo_free(chan);
return ret;
}
/* Setup channel's default objects */
ret = nouveau_gpuobj_channel_init(chan, vram_handle, tt_handle);
if (ret) {
nouveau_fifo_free(chan);
return ret;
}
/* Create a dma object for the push buffer */
ret = nouveau_fifo_pushbuf_ctxdma_init(chan);
if (ret) {
nouveau_fifo_free(chan);
return ret;
}
nouveau_wait_for_idle(dev);
/* disable the fifo caches */
NV_WRITE(NV03_PFIFO_CACHES, 0x00000000);
NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUSH, NV_READ(NV04_PFIFO_CACHE1_DMA_PUSH)&(~0x1));
NV_WRITE(NV03_PFIFO_CACHE1_PUSH0, 0x00000000);
NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000000);
/* Create a graphics context for new channel */
ret = engine->graph.create_context(chan);
if (ret) {
nouveau_fifo_free(chan);
return ret;
}
/* Construct inital RAMFC for new channel */
ret = engine->fifo.create_context(chan);
if (ret) {
nouveau_fifo_free(chan);
return ret;
}
/* setup channel's default get/put values */
if (dev_priv->card_type < NV_50) {
NV_WRITE(NV03_FIFO_REGS_DMAPUT(channel), chan->pushbuf_base);
NV_WRITE(NV03_FIFO_REGS_DMAGET(channel), chan->pushbuf_base);
} else {
NV_WRITE(NV50_FIFO_REGS_DMAPUT(channel), chan->pushbuf_base);
NV_WRITE(NV50_FIFO_REGS_DMAGET(channel), chan->pushbuf_base);
}
/* If this is the first channel, setup PFIFO ourselves. For any
* other case, the GPU will handle this when it switches contexts.
*/
if (dev_priv->fifo_alloc_count == 1) {
ret = engine->fifo.load_context(chan);
if (ret) {
nouveau_fifo_free(chan);
return ret;
}
ret = engine->graph.load_context(chan);
if (ret) {
nouveau_fifo_free(chan);
return ret;
}
}
NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUSH,
NV_READ(NV04_PFIFO_CACHE1_DMA_PUSH) | 1);
NV_WRITE(NV03_PFIFO_CACHE1_PUSH0, 0x00000001);
NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000001);
NV_WRITE(NV04_PFIFO_CACHE1_PULL1, 0x00000001);
/* reenable the fifo caches */
NV_WRITE(NV03_PFIFO_CACHES, 1);
DRM_INFO("%s: initialised FIFO %d\n", __func__, channel);
*chan_ret = chan;
return 0;
}
/* stops a fifo */
void nouveau_fifo_free(struct nouveau_channel *chan)
{
struct drm_device *dev = chan->dev;
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nouveau_engine *engine = &dev_priv->Engine;
DRM_INFO("%s: freeing fifo %d\n", __func__, chan->id);
/* disable the fifo caches */
NV_WRITE(NV03_PFIFO_CACHES, 0x00000000);
NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUSH, NV_READ(NV04_PFIFO_CACHE1_DMA_PUSH)&(~0x1));
NV_WRITE(NV03_PFIFO_CACHE1_PUSH0, 0x00000000);
NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000000);
/* stop the fifo, otherwise it could be running and
* it will crash when removing gpu objects */
if (dev_priv->card_type < NV_50) {
NV_WRITE(NV03_FIFO_REGS_DMAPUT(chan->id), chan->pushbuf_base);
NV_WRITE(NV03_FIFO_REGS_DMAGET(chan->id), chan->pushbuf_base);
} else {
NV_WRITE(NV50_FIFO_REGS_DMAPUT(chan->id), chan->pushbuf_base);
NV_WRITE(NV50_FIFO_REGS_DMAGET(chan->id), chan->pushbuf_base);
}
// FIXME XXX needs more code
engine->fifo.destroy_context(chan);
/* Cleanup PGRAPH state */
engine->graph.destroy_context(chan);
/* reenable the fifo caches */
NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUSH,
NV_READ(NV04_PFIFO_CACHE1_DMA_PUSH) | 1);
NV_WRITE(NV03_PFIFO_CACHE1_PUSH0, 0x00000001);
NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000001);
NV_WRITE(NV03_PFIFO_CACHES, 0x00000001);
/* Deallocate push buffer */
nouveau_gpuobj_ref_del(dev, &chan->pushbuf);
if (chan->pushbuf_mem) {
nouveau_mem_free(dev, chan->pushbuf_mem);
chan->pushbuf_mem = NULL;
}
/* Destroy objects belonging to the channel */
nouveau_gpuobj_channel_takedown(chan);
nouveau_notifier_takedown_channel(chan);
dev_priv->fifos[chan->id] = NULL;
dev_priv->fifo_alloc_count--;
drm_free(chan, sizeof(*chan), DRM_MEM_DRIVER);
}
/* cleanups all the fifos from file_priv */
void nouveau_fifo_cleanup(struct drm_device *dev, struct drm_file *file_priv)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
int i;
DRM_DEBUG("clearing FIFO enables from file_priv\n");
for(i = 0; i < nouveau_fifo_number(dev); i++) {
struct nouveau_channel *chan = dev_priv->fifos[i];
if (chan && chan->file_priv == file_priv)
nouveau_fifo_free(chan);
}
}
int
nouveau_fifo_owner(struct drm_device *dev, struct drm_file *file_priv,
int channel)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
if (channel >= nouveau_fifo_number(dev))
return 0;
if (dev_priv->fifos[channel] == NULL)
return 0;
return (dev_priv->fifos[channel]->file_priv == file_priv);
}
/***********************************
* ioctls wrapping the functions
***********************************/
static int nouveau_ioctl_fifo_alloc(struct drm_device *dev, void *data,
struct drm_file *file_priv)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct drm_nouveau_channel_alloc *init = data;
struct drm_map_list *entry;
struct nouveau_channel *chan;
struct mem_block *pushbuf;
int res;
NOUVEAU_CHECK_INITIALISED_WITH_RETURN;
if (init->fb_ctxdma_handle == ~0 || init->tt_ctxdma_handle == ~0)
return -EINVAL;
pushbuf = nouveau_fifo_user_pushbuf_alloc(dev);
if (!pushbuf)
return -ENOMEM;
res = nouveau_fifo_alloc(dev, &chan, file_priv, pushbuf,
init->fb_ctxdma_handle,
init->tt_ctxdma_handle);
if (res)
return res;
init->channel = chan->id;
init->put_base = chan->pushbuf_base;
/* make the fifo available to user space */
/* first, the fifo control regs */
init->ctrl = dev_priv->mmio->offset;
if (dev_priv->card_type < NV_50) {
init->ctrl += NV03_FIFO_REGS(init->channel);
init->ctrl_size = NV03_FIFO_REGS_SIZE;
} else {
init->ctrl += NV50_FIFO_REGS(init->channel);
init->ctrl_size = NV50_FIFO_REGS_SIZE;
}
res = drm_addmap(dev, init->ctrl, init->ctrl_size, _DRM_REGISTERS,
0, &chan->regs);
if (res != 0)
return res;
entry = drm_find_matching_map(dev, chan->regs);
if (!entry)
return -EINVAL;
init->ctrl = entry->user_token;
/* pass back FIFO map info to the caller */
init->cmdbuf = chan->pushbuf_mem->map_handle;
init->cmdbuf_size = chan->pushbuf_mem->size;
/* and the notifier block */
init->notifier = chan->notifier_block->map_handle;
init->notifier_size = chan->notifier_block->size;
return 0;
}
static int nouveau_ioctl_fifo_free(struct drm_device *dev, void *data,
struct drm_file *file_priv)
{
struct drm_nouveau_channel_free *cfree = data;
struct nouveau_channel *chan;
NOUVEAU_CHECK_INITIALISED_WITH_RETURN;
NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(cfree->channel, file_priv, chan);
nouveau_fifo_free(chan);
return 0;
}
/***********************************
* finally, the ioctl table
***********************************/
struct drm_ioctl_desc nouveau_ioctls[] = {
DRM_IOCTL_DEF(DRM_NOUVEAU_CARD_INIT, nouveau_ioctl_card_init, DRM_AUTH),
DRM_IOCTL_DEF(DRM_NOUVEAU_GETPARAM, nouveau_ioctl_getparam, DRM_AUTH),
DRM_IOCTL_DEF(DRM_NOUVEAU_SETPARAM, nouveau_ioctl_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
DRM_IOCTL_DEF(DRM_NOUVEAU_CHANNEL_ALLOC, nouveau_ioctl_fifo_alloc, DRM_AUTH),
DRM_IOCTL_DEF(DRM_NOUVEAU_CHANNEL_FREE, nouveau_ioctl_fifo_free, DRM_AUTH),
DRM_IOCTL_DEF(DRM_NOUVEAU_GROBJ_ALLOC, nouveau_ioctl_grobj_alloc, DRM_AUTH),
DRM_IOCTL_DEF(DRM_NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_ioctl_notifier_alloc, DRM_AUTH),
DRM_IOCTL_DEF(DRM_NOUVEAU_GPUOBJ_FREE, nouveau_ioctl_gpuobj_free, DRM_AUTH),
DRM_IOCTL_DEF(DRM_NOUVEAU_MEM_ALLOC, nouveau_ioctl_mem_alloc, DRM_AUTH),
DRM_IOCTL_DEF(DRM_NOUVEAU_MEM_FREE, nouveau_ioctl_mem_free, DRM_AUTH),
};
int nouveau_max_ioctl = DRM_ARRAY_SIZE(nouveau_ioctls);