summaryrefslogtreecommitdiff
path: root/libdrm/xf86drmRandom.c
blob: 9e1e9ee2c34940a9f85a9b39c1cf7352ec855519 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
/* xf86drmRandom.c -- "Minimal Standard" PRNG Implementation
 * Created: Mon Apr 19 08:28:13 1999 by faith@precisioninsight.com
 *
 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 * 
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 * 
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 * 
 * Authors: Rickard E. (Rik) Faith <faith@valinux.com>
 *
 * $XFree86: xc/programs/Xserver/hw/xfree86/os-support/linux/drm/xf86drmRandom.c,v 1.4 2000/06/17 00:03:34 martin Exp $
 *
 * DESCRIPTION
 *
 * This file contains a simple, straightforward implementation of the Park
 * & Miller "Minimal Standard" PRNG [PM88, PMS93], which is a Lehmer
 * multiplicative linear congruential generator (MLCG) with a period of
 * 2^31-1.
 *
 * This implementation is intended to provide a reliable, portable PRNG
 * that is suitable for testing a hash table implementation and for
 * implementing skip lists.
 *
 * FUTURE ENHANCEMENTS
 *
 * If initial seeds are not selected randomly, two instances of the PRNG
 * can be correlated.  [Knuth81, pp. 32-33] describes a shuffling technique
 * that can eliminate this problem.
 *
 * If PRNGs are used for simulation, the period of the current
 * implementation may be too short.  [LE88] discusses methods of combining
 * MLCGs to produce much longer periods, and suggests some alternative
 * values for A and M.  [LE90 and Sch92] also provide information on
 * long-period PRNGs.
 *
 * REFERENCES
 *
 * [Knuth81] Donald E. Knuth. The Art of Computer Programming.  Volume 2:
 * Seminumerical Algorithms.  Reading, Massachusetts: Addison-Wesley, 1981.
 *
 * [LE88] Pierre L'Ecuyer. "Efficient and Portable Combined Random Number
 * Generators".  CACM 31(6), June 1988, pp. 742-774.
 *
 * [LE90] Pierre L'Ecuyer. "Random Numbers for Simulation". CACM 33(10,
 * October 1990, pp. 85-97.
 *
 * [PM88] Stephen K. Park and Keith W. Miller. "Random Number Generators:
 * Good Ones are Hard to Find". CACM 31(10), October 1988, pp. 1192-1201.
 *
 * [Sch92] Bruce Schneier. "Pseudo-Ransom Sequence Generator for 32-Bit
 * CPUs".  Dr. Dobb's Journal 17(2), February 1992, pp. 34, 37-38, 40.
 *
 * [PMS93] Stephen K. Park, Keith W. Miller, and Paul K. Stockmeyer.  In
 * "Technical Correspondence: Remarks on Choosing and Implementing Random
 * Number Generators". CACM 36(7), July 1993, pp. 105-110.
 *
 */

#define RANDOM_MAIN 0

#if RANDOM_MAIN
# include <stdio.h>
# include <stdlib.h>
#else
# include "xf86drm.h"
# ifdef XFree86LOADER
#  include "xf86.h"
#  include "xf86_ansic.h"
# else
#  include <stdio.h>
#  include <stdlib.h>
# endif
#endif

#define N(x)  drm##x

#define RANDOM_MAGIC 0xfeedbeef
#define RANDOM_DEBUG 0

#if RANDOM_MAIN
#define RANDOM_ALLOC malloc
#define RANDOM_FREE  free
#else
#define RANDOM_ALLOC drmMalloc
#define RANDOM_FREE  drmFree
#endif

typedef struct RandomState {
    unsigned long magic;
    unsigned long a;
    unsigned long m;
    unsigned long q;		/* m div a */
    unsigned long r;		/* m mod a */
    unsigned long check;
    long          seed;
} RandomState;

#if RANDOM_MAIN
extern void          *N(RandomCreate)(unsigned long seed);
extern int           N(RandomDestroy)(void *state);
extern unsigned long N(Random)(void *state);
extern double        N(RandomDouble)(void *state);
#endif

void *N(RandomCreate)(unsigned long seed)
{
    RandomState  *state;

    state           = RANDOM_ALLOC(sizeof(*state));
    if (!state) return NULL;
    state->magic    = RANDOM_MAGIC;
#if 0
				/* Park & Miller, October 1988 */
    state->a        = 16807;
    state->m        = 2147483647;
    state->check    = 1043618065; /* After 10000 iterations */
#else
				/* Park, Miller, and Stockmeyer, July 1993 */
    state->a        = 48271;
    state->m        = 2147483647;
    state->check    = 399268537; /* After 10000 iterations */
#endif
    state->q        = state->m / state->a;
    state->r        = state->m % state->a;

    state->seed     = seed;
				/* Check for illegal boundary conditions,
                                   and choose closest legal value. */
    if (state->seed <= 0)        state->seed = 1;
    if (state->seed >= state->m) state->seed = state->m - 1;

    return state;
}

int N(RandomDestroy)(void *state)
{
    RANDOM_FREE(state);
    return 0;
}

unsigned long N(Random)(void *state)
{
    RandomState   *s = (RandomState *)state;
    long          hi;
    long          lo;

    hi      = s->seed / s->q;
    lo      = s->seed % s->q;
    s->seed = s->a * lo - s->r * hi;
    if (s->seed <= 0) s->seed += s->m;

    return s->seed;
}

double N(RandomDouble)(void *state)
{
    RandomState *s = (RandomState *)state;
    
    return (double)N(Random)(state)/(double)s->m;
}

#if RANDOM_MAIN
static void check_period(long seed)
{
    unsigned long count = 0;
    unsigned long initial;
    void          *state;
    
    state = N(RandomCreate)(seed);
    initial = N(Random)(state);
    ++count;
    while (initial != N(Random)(state)) {
	if (!++count) break;
    }
    printf("With seed of %10ld, period = %10lu (0x%08lx)\n",
	   seed, count, count);
    N(RandomDestroy)(state);
}

int main(void)
{
    RandomState   *state;
    int           i;
    unsigned long rand;

    state = N(RandomCreate)(1);
    for (i = 0; i < 10000; i++) {
	rand = N(Random)(state);
    }
    printf("After 10000 iterations: %lu (%lu expected): %s\n",
	   rand, state->check,
	   rand - state->check ? "*INCORRECT*" : "CORRECT");
    N(RandomDestroy)(state);

    printf("Checking periods...\n");
    check_period(1);
    check_period(2);
    check_period(31415926);
    
    return 0;
}
#endif
a> 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751 1752 1753 1754 1755 1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775 1776 1777 1778 1779 1780 1781 1782 1783 1784 1785 1786 1787 1788 1789 1790 1791 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806 1807 1808 1809 1810 1811 1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936 1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114 2115 2116 2117 2118 2119 2120 2121 2122 2123 2124 2125 2126 2127 2128 2129 2130 2131 2132 2133 2134 2135 2136 2137 2138 2139 2140 2141 2142 2143 2144 2145 2146 2147 2148 2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 2186 2187 2188 2189 2190 2191 2192 2193 2194 2195 2196 2197 2198 2199 2200 2201 2202 2203 2204 2205 2206 2207 2208 2209 2210 2211 2212 2213 2214 2215 2216 2217 2218 2219 2220 2221 2222 2223 2224 2225 2226 2227 2228 2229 2230 2231 2232 2233 2234 2235 2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251 2252 2253 2254 2255 2256 2257 2258 2259 2260 2261 2262 2263 2264 2265 2266 2267 2268 2269 2270 2271 2272 2273 2274 2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 2309 2310 2311 2312 2313 2314 2315 2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357 2358 2359 2360 2361 2362 2363 2364 2365 2366 2367 2368 2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399 2400 2401 2402 2403 2404 2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 2428 2429 2430 2431 2432 2433 2434 2435 2436 2437 2438 2439 2440 2441 2442 2443 2444 2445 2446 2447 2448 2449 2450 2451 2452 2453 2454 2455 2456 2457 2458 2459 2460 2461 2462 2463 2464 2465 2466 2467 2468 2469 2470 2471 2472 2473 2474 2475 2476 2477 2478 2479 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489 2490 2491 2492 2493 2494 2495 2496 2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507 2508 2509 2510 2511 2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529 2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540 2541 2542 2543 2544 2545 2546 2547 2548 2549 2550 2551 2552 2553 2554 2555 2556 2557
/*
 * Copyright © 2011 Red Hat All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining
 * a copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
 * USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 */
/*
 * Authors:
 *      Jérôme Glisse <jglisse@redhat.com>
 */
#ifdef HAVE_CONFIG_H
#include <config.h>
#endif
#include <stdbool.h>
#include <assert.h>
#include <errno.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sys/ioctl.h>
#include "drm.h"
#include "libdrm_macros.h"
#include "xf86drm.h"
#include "radeon_drm.h"
#include "radeon_surface.h"

#define ALIGN(value, alignment) (((value) + alignment - 1) & ~(alignment - 1))
#define MAX2(A, B)              ((A) > (B) ? (A) : (B))
#define MIN2(A, B)              ((A) < (B) ? (A) : (B))

/* keep this private */
enum radeon_family {
    CHIP_UNKNOWN,
    CHIP_R600,
    CHIP_RV610,
    CHIP_RV630,
    CHIP_RV670,
    CHIP_RV620,
    CHIP_RV635,
    CHIP_RS780,
    CHIP_RS880,
    CHIP_RV770,
    CHIP_RV730,
    CHIP_RV710,
    CHIP_RV740,
    CHIP_CEDAR,
    CHIP_REDWOOD,
    CHIP_JUNIPER,
    CHIP_CYPRESS,
    CHIP_HEMLOCK,
    CHIP_PALM,
    CHIP_SUMO,
    CHIP_SUMO2,
    CHIP_BARTS,
    CHIP_TURKS,
    CHIP_CAICOS,
    CHIP_CAYMAN,
    CHIP_ARUBA,
    CHIP_TAHITI,
    CHIP_PITCAIRN,
    CHIP_VERDE,
    CHIP_OLAND,
    CHIP_HAINAN,
    CHIP_BONAIRE,
    CHIP_KAVERI,
    CHIP_KABINI,
    CHIP_HAWAII,
    CHIP_MULLINS,
    CHIP_LAST,
};

typedef int (*hw_init_surface_t)(struct radeon_surface_manager *surf_man,
                                 struct radeon_surface *surf);
typedef int (*hw_best_surface_t)(struct radeon_surface_manager *surf_man,
                                 struct radeon_surface *surf);

struct radeon_hw_info {
    /* apply to r6, eg */
    uint32_t                        group_bytes;
    uint32_t                        num_banks;
    uint32_t                        num_pipes;
    /* apply to eg */
    uint32_t                        row_size;
    unsigned                        allow_2d;
    /* apply to si */
    uint32_t                        tile_mode_array[32];
    /* apply to cik */
    uint32_t                        macrotile_mode_array[16];
};

struct radeon_surface_manager {
    int                         fd;
    uint32_t                    device_id;
    struct radeon_hw_info       hw_info;
    unsigned                    family;
    hw_init_surface_t           surface_init;
    hw_best_surface_t           surface_best;
};

/* helper */
static int radeon_get_value(int fd, unsigned req, uint32_t *value)
{
    struct drm_radeon_info info = {};
    int r;

    *value = 0;
    info.request = req;
    info.value = (uintptr_t)value;
    r = drmCommandWriteRead(fd, DRM_RADEON_INFO, &info,
                            sizeof(struct drm_radeon_info));
    return r;
}

static int radeon_get_family(struct radeon_surface_manager *surf_man)
{
    switch (surf_man->device_id) {
#define CHIPSET(pci_id, name, fam) case pci_id: surf_man->family = CHIP_##fam; break;
#include "r600_pci_ids.h"
#undef CHIPSET
    default:
        return -EINVAL;
    }
    return 0;
}

static unsigned next_power_of_two(unsigned x)
{
   if (x <= 1)
       return 1;

   return (1 << ((sizeof(unsigned) * 8) - __builtin_clz(x - 1)));
}

static unsigned mip_minify(unsigned size, unsigned level)
{
    unsigned val;

    val = MAX2(1, size >> level);
    if (level > 0)
        val = next_power_of_two(val);
    return val;
}

static void surf_minify(struct radeon_surface *surf,
                        struct radeon_surface_level *surflevel,
                        unsigned bpe, unsigned level,
                        uint32_t xalign, uint32_t yalign, uint32_t zalign,
                        unsigned offset)
{
    surflevel->npix_x = mip_minify(surf->npix_x, level);
    surflevel->npix_y = mip_minify(surf->npix_y, level);
    surflevel->npix_z = mip_minify(surf->npix_z, level);
    surflevel->nblk_x = (surflevel->npix_x + surf->blk_w - 1) / surf->blk_w;
    surflevel->nblk_y = (surflevel->npix_y + surf->blk_h - 1) / surf->blk_h;
    surflevel->nblk_z = (surflevel->npix_z + surf->blk_d - 1) / surf->blk_d;
    if (surf->nsamples == 1 && surflevel->mode == RADEON_SURF_MODE_2D &&
        !(surf->flags & RADEON_SURF_FMASK)) {
        if (surflevel->nblk_x < xalign || surflevel->nblk_y < yalign) {
            surflevel->mode = RADEON_SURF_MODE_1D;
            return;
        }
    }
    surflevel->nblk_x  = ALIGN(surflevel->nblk_x, xalign);
    surflevel->nblk_y  = ALIGN(surflevel->nblk_y, yalign);
    surflevel->nblk_z  = ALIGN(surflevel->nblk_z, zalign);

    surflevel->offset = offset;
    surflevel->pitch_bytes = surflevel->nblk_x * bpe * surf->nsamples;
    surflevel->slice_size = surflevel->pitch_bytes * surflevel->nblk_y;

    surf->bo_size = offset + surflevel->slice_size * surflevel->nblk_z * surf->array_size;
}

/* ===========================================================================
 * r600/r700 family
 */
static int r6_init_hw_info(struct radeon_surface_manager *surf_man)
{
    uint32_t tiling_config;
    drmVersionPtr version;
    int r;

    r = radeon_get_value(surf_man->fd, RADEON_INFO_TILING_CONFIG,
                         &tiling_config);
    if (r) {
        return r;
    }

    surf_man->hw_info.allow_2d = 0;
    version = drmGetVersion(surf_man->fd);
    if (version && version->version_minor >= 14) {
        surf_man->hw_info.allow_2d = 1;
    }
    drmFreeVersion(version);

    switch ((tiling_config & 0xe) >> 1) {
    case 0:
        surf_man->hw_info.num_pipes = 1;
        break;
    case 1:
        surf_man->hw_info.num_pipes = 2;
        break;
    case 2:
        surf_man->hw_info.num_pipes = 4;
        break;
    case 3:
        surf_man->hw_info.num_pipes = 8;
        break;
    default:
        surf_man->hw_info.num_pipes = 8;
        surf_man->hw_info.allow_2d = 0;
        break;
    }

    switch ((tiling_config & 0x30) >> 4) {
    case 0:
        surf_man->hw_info.num_banks = 4;
        break;
    case 1:
        surf_man->hw_info.num_banks = 8;
        break;
    default:
        surf_man->hw_info.num_banks = 8;
        surf_man->hw_info.allow_2d = 0;
        break;
    }

    switch ((tiling_config & 0xc0) >> 6) {
    case 0:
        surf_man->hw_info.group_bytes = 256;
        break;
    case 1:
        surf_man->hw_info.group_bytes = 512;
        break;
    default:
        surf_man->hw_info.group_bytes = 256;
        surf_man->hw_info.allow_2d = 0;
        break;
    }
    return 0;
}

static int r6_surface_init_linear(struct radeon_surface_manager *surf_man,
                                  struct radeon_surface *surf,
                                  uint64_t offset, unsigned start_level)
{
    uint32_t xalign, yalign, zalign;
    unsigned i;

    /* compute alignment */
    if (!start_level) {
        surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes);
    }
    /* the 32 alignment is for scanout, cb or db but to allow texture to be
     * easily bound as such we force this alignment to all surface
     */
    xalign = MAX2(1, surf_man->hw_info.group_bytes / surf->bpe);
    yalign = 1;
    zalign = 1;
    if (surf->flags & RADEON_SURF_SCANOUT) {
        xalign = MAX2((surf->bpe == 1) ? 64 : 32, xalign);
    }

    /* build mipmap tree */
    for (i = start_level; i <= surf->last_level; i++) {
        surf->level[i].mode = RADEON_SURF_MODE_LINEAR;
        surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, offset);
        /* level0 and first mipmap need to have alignment */
        offset = surf->bo_size;
        if (i == 0) {
            offset = ALIGN(offset, surf->bo_alignment);
        }
    }
    return 0;
}

static int r6_surface_init_linear_aligned(struct radeon_surface_manager *surf_man,
                                          struct radeon_surface *surf,
                                          uint64_t offset, unsigned start_level)
{
    uint32_t xalign, yalign, zalign;
    unsigned i;

    /* compute alignment */
    if (!start_level) {
        surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes);
    }
    xalign = MAX2(64, surf_man->hw_info.group_bytes / surf->bpe);
    yalign = 1;
    zalign = 1;

    /* build mipmap tree */
    for (i = start_level; i <= surf->last_level; i++) {
        surf->level[i].mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
        surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, offset);
        /* level0 and first mipmap need to have alignment */
        offset = surf->bo_size;
        if (i == 0) {
            offset = ALIGN(offset, surf->bo_alignment);
        }
    }
    return 0;
}

static int r6_surface_init_1d(struct radeon_surface_manager *surf_man,
                              struct radeon_surface *surf,
                              uint64_t offset, unsigned start_level)
{
    uint32_t xalign, yalign, zalign, tilew;
    unsigned i;

    /* compute alignment */
    tilew = 8;
    xalign = surf_man->hw_info.group_bytes / (tilew * surf->bpe * surf->nsamples);
    xalign = MAX2(tilew, xalign);
    yalign = tilew;
    zalign = 1;
    if (surf->flags & RADEON_SURF_SCANOUT) {
        xalign = MAX2((surf->bpe == 1) ? 64 : 32, xalign);
    }
    if (!start_level) {
        surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes);
    }

    /* build mipmap tree */
    for (i = start_level; i <= surf->last_level; i++) {
        surf->level[i].mode = RADEON_SURF_MODE_1D;
        surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, offset);
        /* level0 and first mipmap need to have alignment */
        offset = surf->bo_size;
        if (i == 0) {
            offset = ALIGN(offset, surf->bo_alignment);
        }
    }
    return 0;
}

static int r6_surface_init_2d(struct radeon_surface_manager *surf_man,
                              struct radeon_surface *surf,
                              uint64_t offset, unsigned start_level)
{
    uint32_t xalign, yalign, zalign, tilew;
    unsigned i;

    /* compute alignment */
    tilew = 8;
    zalign = 1;
    xalign = (surf_man->hw_info.group_bytes * surf_man->hw_info.num_banks) /
             (tilew * surf->bpe * surf->nsamples);
    xalign = MAX2(tilew * surf_man->hw_info.num_banks, xalign);
    if (surf->flags & RADEON_SURF_FMASK)
	xalign = MAX2(128, xalign);
    yalign = tilew * surf_man->hw_info.num_pipes;
    if (surf->flags & RADEON_SURF_SCANOUT) {
        xalign = MAX2((surf->bpe == 1) ? 64 : 32, xalign);
    }
    if (!start_level) {
        surf->bo_alignment =
            MAX2(surf_man->hw_info.num_pipes *
                 surf_man->hw_info.num_banks *
                 surf->nsamples * surf->bpe * 64,
                 xalign * yalign * surf->nsamples * surf->bpe);
    }

    /* build mipmap tree */
    for (i = start_level; i <= surf->last_level; i++) {
        surf->level[i].mode = RADEON_SURF_MODE_2D;
        surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, offset);
        if (surf->level[i].mode == RADEON_SURF_MODE_1D) {
            return r6_surface_init_1d(surf_man, surf, offset, i);
        }
        /* level0 and first mipmap need to have alignment */
        offset = surf->bo_size;
        if (i == 0) {
            offset = ALIGN(offset, surf->bo_alignment);
        }
    }
    return 0;
}

static int r6_surface_init(struct radeon_surface_manager *surf_man,
                           struct radeon_surface *surf)
{
    unsigned mode;
    int r;

    /* MSAA surfaces support the 2D mode only. */
    if (surf->nsamples > 1) {
        surf->flags = RADEON_SURF_CLR(surf->flags, MODE);
        surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
    }

    /* tiling mode */
    mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK;

    if (surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) {
        /* zbuffer only support 1D or 2D tiled surface */
        switch (mode) {
        case RADEON_SURF_MODE_1D:
        case RADEON_SURF_MODE_2D:
            break;
        default:
            mode = RADEON_SURF_MODE_1D;
            surf->flags = RADEON_SURF_CLR(surf->flags, MODE);
            surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
            break;
        }
    }

    /* force 1d on kernel that can't do 2d */
    if (!surf_man->hw_info.allow_2d && mode > RADEON_SURF_MODE_1D) {
        if (surf->nsamples > 1) {
            fprintf(stderr, "radeon: Cannot use 2D tiling for an MSAA surface (%i).\n", __LINE__);
            return -EFAULT;
        }
        mode = RADEON_SURF_MODE_1D;
        surf->flags = RADEON_SURF_CLR(surf->flags, MODE);
        surf->flags |= RADEON_SURF_SET(mode, MODE);
    }

    /* check surface dimension */
    if (surf->npix_x > 8192 || surf->npix_y > 8192 || surf->npix_z > 8192) {
        return -EINVAL;
    }

    /* check mipmap last_level */
    if (surf->last_level > 14) {
        return -EINVAL;
    }

    /* check tiling mode */
    switch (mode) {
    case RADEON_SURF_MODE_LINEAR:
        r = r6_surface_init_linear(surf_man, surf, 0, 0);
        break;
    case RADEON_SURF_MODE_LINEAR_ALIGNED:
        r = r6_surface_init_linear_aligned(surf_man, surf, 0, 0);
        break;
    case RADEON_SURF_MODE_1D:
        r = r6_surface_init_1d(surf_man, surf, 0, 0);
        break;
    case RADEON_SURF_MODE_2D:
        r = r6_surface_init_2d(surf_man, surf, 0, 0);
        break;
    default:
        return -EINVAL;
    }
    return r;
}

static int r6_surface_best(struct radeon_surface_manager *surf_man,
                           struct radeon_surface *surf)
{
    /* no value to optimize for r6xx/r7xx */
    return 0;
}


/* ===========================================================================
 * evergreen family
 */
static int eg_init_hw_info(struct radeon_surface_manager *surf_man)
{
    uint32_t tiling_config;
    drmVersionPtr version;
    int r;

    r = radeon_get_value(surf_man->fd, RADEON_INFO_TILING_CONFIG,
                         &tiling_config);
    if (r) {
        return r;
    }

    surf_man->hw_info.allow_2d = 0;
    version = drmGetVersion(surf_man->fd);
    if (version && version->version_minor >= 16) {
        surf_man->hw_info.allow_2d = 1;
    }
    drmFreeVersion(version);

    switch (tiling_config & 0xf) {
    case 0:
        surf_man->hw_info.num_pipes = 1;
        break;
    case 1:
        surf_man->hw_info.num_pipes = 2;
        break;
    case 2:
        surf_man->hw_info.num_pipes = 4;
        break;
    case 3:
        surf_man->hw_info.num_pipes = 8;
        break;
    default:
        surf_man->hw_info.num_pipes = 8;
        surf_man->hw_info.allow_2d = 0;
        break;
    }

    switch ((tiling_config & 0xf0) >> 4) {
    case 0:
        surf_man->hw_info.num_banks = 4;
        break;
    case 1:
        surf_man->hw_info.num_banks = 8;
        break;
    case 2:
        surf_man->hw_info.num_banks = 16;
        break;
    default:
        surf_man->hw_info.num_banks = 8;
        surf_man->hw_info.allow_2d = 0;
        break;
    }

    switch ((tiling_config & 0xf00) >> 8) {
    case 0:
        surf_man->hw_info.group_bytes = 256;
        break;
    case 1:
        surf_man->hw_info.group_bytes = 512;
        break;
    default:
        surf_man->hw_info.group_bytes = 256;
        surf_man->hw_info.allow_2d = 0;
        break;
    }

    switch ((tiling_config & 0xf000) >> 12) {
    case 0:
        surf_man->hw_info.row_size = 1024;
        break;
    case 1:
        surf_man->hw_info.row_size = 2048;
        break;
    case 2:
        surf_man->hw_info.row_size = 4096;
        break;
    default:
        surf_man->hw_info.row_size = 4096;
        surf_man->hw_info.allow_2d = 0;
        break;
    }
    return 0;
}

static void eg_surf_minify(struct radeon_surface *surf,
                           struct radeon_surface_level *surflevel,
                           unsigned bpe,
                           unsigned level,
                           unsigned slice_pt,
                           unsigned mtilew,
                           unsigned mtileh,
                           unsigned mtileb,
                           unsigned offset)
{
    unsigned mtile_pr, mtile_ps;

    surflevel->npix_x = mip_minify(surf->npix_x, level);
    surflevel->npix_y = mip_minify(surf->npix_y, level);
    surflevel->npix_z = mip_minify(surf->npix_z, level);
    surflevel->nblk_x = (surflevel->npix_x + surf->blk_w - 1) / surf->blk_w;
    surflevel->nblk_y = (surflevel->npix_y + surf->blk_h - 1) / surf->blk_h;
    surflevel->nblk_z = (surflevel->npix_z + surf->blk_d - 1) / surf->blk_d;
    if (surf->nsamples == 1 && surflevel->mode == RADEON_SURF_MODE_2D &&
        !(surf->flags & RADEON_SURF_FMASK)) {
        if (surflevel->nblk_x < mtilew || surflevel->nblk_y < mtileh) {
            surflevel->mode = RADEON_SURF_MODE_1D;
            return;
        }
    }
    surflevel->nblk_x  = ALIGN(surflevel->nblk_x, mtilew);
    surflevel->nblk_y  = ALIGN(surflevel->nblk_y, mtileh);
    surflevel->nblk_z  = ALIGN(surflevel->nblk_z, 1);

    /* macro tile per row */
    mtile_pr = surflevel->nblk_x / mtilew;
    /* macro tile per slice */
    mtile_ps = (mtile_pr * surflevel->nblk_y) / mtileh;

    surflevel->offset = offset;
    surflevel->pitch_bytes = surflevel->nblk_x * bpe * surf->nsamples;
    surflevel->slice_size = mtile_ps * mtileb * slice_pt;

    surf->bo_size = offset + surflevel->slice_size * surflevel->nblk_z * surf->array_size;
}

static int eg_surface_init_1d(struct radeon_surface_manager *surf_man,
                              struct radeon_surface *surf,
                              struct radeon_surface_level *level,
                              unsigned bpe,
                              uint64_t offset, unsigned start_level)
{
    uint32_t xalign, yalign, zalign, tilew;
    unsigned i;

    /* compute alignment */
    tilew = 8;
    xalign = surf_man->hw_info.group_bytes / (tilew * bpe * surf->nsamples);
    xalign = MAX2(tilew, xalign);
    yalign = tilew;
    zalign = 1;
    if (surf->flags & RADEON_SURF_SCANOUT) {
        xalign = MAX2((bpe == 1) ? 64 : 32, xalign);
    }

    if (!start_level) {
        unsigned alignment = MAX2(256, surf_man->hw_info.group_bytes);
        surf->bo_alignment = MAX2(surf->bo_alignment, alignment);

        if (offset) {
            offset = ALIGN(offset, alignment);
        }
    }

    /* build mipmap tree */
    for (i = start_level; i <= surf->last_level; i++) {
        level[i].mode = RADEON_SURF_MODE_1D;
        surf_minify(surf, level+i, bpe, i, xalign, yalign, zalign, offset);
        /* level0 and first mipmap need to have alignment */
        offset = surf->bo_size;
        if (i == 0) {
            offset = ALIGN(offset, surf->bo_alignment);
        }
    }
    return 0;
}

static int eg_surface_init_2d(struct radeon_surface_manager *surf_man,
                              struct radeon_surface *surf,
                              struct radeon_surface_level *level,
                              unsigned bpe, unsigned tile_split,
                              uint64_t offset, unsigned start_level)
{
    unsigned tilew, tileh, tileb;
    unsigned mtilew, mtileh, mtileb;
    unsigned slice_pt;
    unsigned i;

    /* compute tile values */
    tilew = 8;
    tileh = 8;
    tileb = tilew * tileh * bpe * surf->nsamples;
    /* slices per tile */
    slice_pt = 1;
    if (tileb > tile_split && tile_split) {
        slice_pt = tileb / tile_split;
    }
    tileb = tileb / slice_pt;

    /* macro tile width & height */
    mtilew = (tilew * surf->bankw * surf_man->hw_info.num_pipes) * surf->mtilea;
    mtileh = (tileh * surf->bankh * surf_man->hw_info.num_banks) / surf->mtilea;
    /* macro tile bytes */
    mtileb = (mtilew / tilew) * (mtileh / tileh) * tileb;

    if (!start_level) {
        unsigned alignment = MAX2(256, mtileb);
        surf->bo_alignment = MAX2(surf->bo_alignment, alignment);

        if (offset) {
            offset = ALIGN(offset, alignment);
        }
    }

    /* build mipmap tree */
    for (i = start_level; i <= surf->last_level; i++) {
        level[i].mode = RADEON_SURF_MODE_2D;
        eg_surf_minify(surf, level+i, bpe, i, slice_pt, mtilew, mtileh, mtileb, offset);
        if (level[i].mode == RADEON_SURF_MODE_1D) {
            return eg_surface_init_1d(surf_man, surf, level, bpe, offset, i);
        }
        /* level0 and first mipmap need to have alignment */
        offset = surf->bo_size;
        if (i == 0) {
            offset = ALIGN(offset, surf->bo_alignment);
        }
    }
    return 0;
}

static int eg_surface_sanity(struct radeon_surface_manager *surf_man,
                             struct radeon_surface *surf,
                             unsigned mode)
{
    unsigned tileb;

    /* check surface dimension */
    if (surf->npix_x > 16384 || surf->npix_y > 16384 || surf->npix_z > 16384) {
        return -EINVAL;
    }

    /* check mipmap last_level */
    if (surf->last_level > 15) {
        return -EINVAL;
    }

    /* force 1d on kernel that can't do 2d */
    if (!surf_man->hw_info.allow_2d && mode > RADEON_SURF_MODE_1D) {
        if (surf->nsamples > 1) {
            fprintf(stderr, "radeon: Cannot use 2D tiling for an MSAA surface (%i).\n", __LINE__);
            return -EFAULT;
        }
        mode = RADEON_SURF_MODE_1D;
        surf->flags = RADEON_SURF_CLR(surf->flags, MODE);
        surf->flags |= RADEON_SURF_SET(mode, MODE);
    }

    /* check tile split */
    if (mode == RADEON_SURF_MODE_2D) {
        switch (surf->tile_split) {
        case 64:
        case 128:
        case 256:
        case 512:
        case 1024:
        case 2048:
        case 4096:
            break;
        default:
            return -EINVAL;
        }
        switch (surf->mtilea) {
        case 1:
        case 2:
        case 4:
        case 8:
            break;
        default:
            return -EINVAL;
        }
        /* check aspect ratio */
        if (surf_man->hw_info.num_banks < surf->mtilea) {
            return -EINVAL;
        }
        /* check bank width */
        switch (surf->bankw) {
        case 1:
        case 2:
        case 4:
        case 8:
            break;
        default:
            return -EINVAL;
        }
        /* check bank height */
        switch (surf->bankh) {
        case 1:
        case 2:
        case 4:
        case 8:
            break;
        default:
            return -EINVAL;
        }
        tileb = MIN2(surf->tile_split, 64 * surf->bpe * surf->nsamples);
        if ((tileb * surf->bankh * surf->bankw) < surf_man->hw_info.group_bytes) {
            return -EINVAL;
        }
    }

    return 0;
}

static int eg_surface_init_1d_miptrees(struct radeon_surface_manager *surf_man,
                                       struct radeon_surface *surf)
{
    unsigned zs_flags = RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER;
    int r, is_depth_stencil = (surf->flags & zs_flags) == zs_flags;
    /* Old libdrm_macros.headers didn't have stencil_level in it. This prevents crashes. */
    struct radeon_surface_level tmp[RADEON_SURF_MAX_LEVEL];
    struct radeon_surface_level *stencil_level =
        (surf->flags & RADEON_SURF_HAS_SBUFFER_MIPTREE) ? surf->stencil_level : tmp;

    r = eg_surface_init_1d(surf_man, surf, surf->level, surf->bpe, 0, 0);
    if (r)
        return r;

    if (is_depth_stencil) {
        r = eg_surface_init_1d(surf_man, surf, stencil_level, 1,
                               surf->bo_size, 0);
        surf->stencil_offset = stencil_level[0].offset;
    }
    return r;
}

static int eg_surface_init_2d_miptrees(struct radeon_surface_manager *surf_man,
                                       struct radeon_surface *surf)
{
    unsigned zs_flags = RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER;
    int r, is_depth_stencil = (surf->flags & zs_flags) == zs_flags;
    /* Old libdrm_macros.headers didn't have stencil_level in it. This prevents crashes. */
    struct radeon_surface_level tmp[RADEON_SURF_MAX_LEVEL];
    struct radeon_surface_level *stencil_level =
        (surf->flags & RADEON_SURF_HAS_SBUFFER_MIPTREE) ? surf->stencil_level : tmp;

    r = eg_surface_init_2d(surf_man, surf, surf->level, surf->bpe,
                           surf->tile_split, 0, 0);
    if (r)
        return r;

    if (is_depth_stencil) {
        r = eg_surface_init_2d(surf_man, surf, stencil_level, 1,
                               surf->stencil_tile_split, surf->bo_size, 0);
        surf->stencil_offset = stencil_level[0].offset;
    }
    return r;
}

static int eg_surface_init(struct radeon_surface_manager *surf_man,
                           struct radeon_surface *surf)
{
    unsigned mode;
    int r;

    /* MSAA surfaces support the 2D mode only. */
    if (surf->nsamples > 1) {
        surf->flags = RADEON_SURF_CLR(surf->flags, MODE);
        surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
    }

    /* tiling mode */
    mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK;

    if (surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) {
        /* zbuffer only support 1D or 2D tiled surface */
        switch (mode) {
        case RADEON_SURF_MODE_1D:
        case RADEON_SURF_MODE_2D:
            break;
        default:
            mode = RADEON_SURF_MODE_1D;
            surf->flags = RADEON_SURF_CLR(surf->flags, MODE);
            surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
            break;
        }
    }

    r = eg_surface_sanity(surf_man, surf, mode);
    if (r) {
        return r;
    }

    surf->stencil_offset = 0;
    surf->bo_alignment = 0;

    /* check tiling mode */
    switch (mode) {
    case RADEON_SURF_MODE_LINEAR:
        r = r6_surface_init_linear(surf_man, surf, 0, 0);
        break;
    case RADEON_SURF_MODE_LINEAR_ALIGNED:
        r = r6_surface_init_linear_aligned(surf_man, surf, 0, 0);
        break;
    case RADEON_SURF_MODE_1D:
        r = eg_surface_init_1d_miptrees(surf_man, surf);
        break;
    case RADEON_SURF_MODE_2D:
        r = eg_surface_init_2d_miptrees(surf_man, surf);
        break;
    default:
        return -EINVAL;
    }
    return r;
}

static unsigned log2_int(unsigned x)
{
    unsigned l;

    if (x < 2) {
        return 0;
    }
    for (l = 2; ; l++) {
        if ((unsigned)(1 << l) > x) {
            return l - 1;
        }
    }
    return 0;
}

/* compute best tile_split, bankw, bankh, mtilea
 * depending on surface
 */
static int eg_surface_best(struct radeon_surface_manager *surf_man,
                           struct radeon_surface *surf)
{
    unsigned mode, tileb, h_over_w;
    int r;

    /* tiling mode */
    mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK;

    /* set some default value to avoid sanity check choking on them */
    surf->tile_split = 1024;
    surf->bankw = 1;
    surf->bankh = 1;
    surf->mtilea = surf_man->hw_info.num_banks;
    tileb = MIN2(surf->tile_split, 64 * surf->bpe * surf->nsamples);
    for (; surf->bankh <= 8; surf->bankh *= 2) {
        if ((tileb * surf->bankh * surf->bankw) >= surf_man->hw_info.group_bytes) {
            break;
        }
    }
    if (surf->mtilea > 8) {
        surf->mtilea = 8;
    }

    r = eg_surface_sanity(surf_man, surf, mode);
    if (r) {
        return r;
    }

    if (mode != RADEON_SURF_MODE_2D) {
        /* nothing to do for non 2D tiled surface */
        return 0;
    }

    /* Tweak TILE_SPLIT for performance here. */
    if (surf->nsamples > 1) {
        if (surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) {
            switch (surf->nsamples) {
            case 2:
                surf->tile_split = 128;
                break;
            case 4:
                surf->tile_split = 128;
                break;
            case 8:
                surf->tile_split = 256;
                break;
            case 16: /* cayman only */
                surf->tile_split = 512;
                break;
            default:
                fprintf(stderr, "radeon: Wrong number of samples %i (%i)\n",
                        surf->nsamples, __LINE__);
                return -EINVAL;
            }
            surf->stencil_tile_split = 64;
        } else {
            /* tile split must be >= 256 for colorbuffer surfaces */
            surf->tile_split = MAX2(surf->nsamples * surf->bpe * 64, 256);
            if (surf->tile_split > 4096)
                surf->tile_split = 4096;
        }
    } else {
        /* set tile split to row size */
        surf->tile_split = surf_man->hw_info.row_size;
        surf->stencil_tile_split = surf_man->hw_info.row_size / 2;
    }

    /* bankw or bankh greater than 1 increase alignment requirement, not
     * sure if it's worth using smaller bankw & bankh to stick with 2D
     * tiling on small surface rather than falling back to 1D tiling.
     * Use recommanded value based on tile size for now.
     *
     * fmask buffer has different optimal value figure them out once we
     * use it.
     */
    if (surf->flags & RADEON_SURF_SBUFFER) {
        /* assume 1 bytes for stencil, we optimize for stencil as stencil
         * and depth shares surface values
         */
        tileb = MIN2(surf->tile_split, 64 * surf->nsamples);
    } else {
        tileb = MIN2(surf->tile_split, 64 * surf->bpe * surf->nsamples);
    }

    /* use bankw of 1 to minimize width alignment, might be interesting to
     * increase it for large surface
     */
    surf->bankw = 1;
    switch (tileb) {
    case 64:
        surf->bankh = 4;
        break;
    case 128:
    case 256:
        surf->bankh = 2;
        break;
    default:
        surf->bankh = 1;
        break;
    }
    /* double check the constraint */
    for (; surf->bankh <= 8; surf->bankh *= 2) {
        if ((tileb * surf->bankh * surf->bankw) >= surf_man->hw_info.group_bytes) {
            break;
        }
    }

    h_over_w = (((surf->bankh * surf_man->hw_info.num_banks) << 16) /
                (surf->bankw * surf_man->hw_info.num_pipes)) >> 16;
    surf->mtilea = 1 << (log2_int(h_over_w) >> 1);

    return 0;
}


/* ===========================================================================
 * Southern Islands family
 */
#define SI__GB_TILE_MODE__PIPE_CONFIG(x)        (((x) >> 6) & 0x1f)
#define     SI__PIPE_CONFIG__ADDR_SURF_P2               0
#define     SI__PIPE_CONFIG__ADDR_SURF_P4_8x16          4
#define     SI__PIPE_CONFIG__ADDR_SURF_P4_16x16         5
#define     SI__PIPE_CONFIG__ADDR_SURF_P4_16x32         6
#define     SI__PIPE_CONFIG__ADDR_SURF_P4_32x32         7
#define     SI__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16    8
#define     SI__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16    9
#define     SI__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16    10
#define     SI__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16   11
#define     SI__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16   12
#define     SI__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32   13
#define     SI__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32   14
#define SI__GB_TILE_MODE__TILE_SPLIT(x)         (((x) >> 11) & 0x7)
#define     SI__TILE_SPLIT__64B                         0
#define     SI__TILE_SPLIT__128B                        1
#define     SI__TILE_SPLIT__256B                        2
#define     SI__TILE_SPLIT__512B                        3
#define     SI__TILE_SPLIT__1024B                       4
#define     SI__TILE_SPLIT__2048B                       5
#define     SI__TILE_SPLIT__4096B                       6
#define SI__GB_TILE_MODE__BANK_WIDTH(x)         (((x) >> 14) & 0x3)
#define     SI__BANK_WIDTH__1                           0
#define     SI__BANK_WIDTH__2                           1
#define     SI__BANK_WIDTH__4                           2
#define     SI__BANK_WIDTH__8                           3
#define SI__GB_TILE_MODE__BANK_HEIGHT(x)        (((x) >> 16) & 0x3)
#define     SI__BANK_HEIGHT__1                          0
#define     SI__BANK_HEIGHT__2                          1
#define     SI__BANK_HEIGHT__4                          2
#define     SI__BANK_HEIGHT__8                          3
#define SI__GB_TILE_MODE__MACRO_TILE_ASPECT(x)  (((x) >> 18) & 0x3)
#define     SI__MACRO_TILE_ASPECT__1                    0
#define     SI__MACRO_TILE_ASPECT__2                    1
#define     SI__MACRO_TILE_ASPECT__4                    2
#define     SI__MACRO_TILE_ASPECT__8                    3
#define SI__GB_TILE_MODE__NUM_BANKS(x)          (((x) >> 20) & 0x3)
#define     SI__NUM_BANKS__2_BANK                       0
#define     SI__NUM_BANKS__4_BANK                       1
#define     SI__NUM_BANKS__8_BANK                       2
#define     SI__NUM_BANKS__16_BANK                      3


static void si_gb_tile_mode(uint32_t gb_tile_mode,
                            unsigned *num_pipes,
                            unsigned *num_banks,
                            uint32_t *macro_tile_aspect,
                            uint32_t *bank_w,
                            uint32_t *bank_h,
                            uint32_t *tile_split)
{
    if (num_pipes) {
        switch (SI__GB_TILE_MODE__PIPE_CONFIG(gb_tile_mode)) {
        case SI__PIPE_CONFIG__ADDR_SURF_P2:
        default:
            *num_pipes = 2;
            break;
        case SI__PIPE_CONFIG__ADDR_SURF_P4_8x16:
        case SI__PIPE_CONFIG__ADDR_SURF_P4_16x16:
        case SI__PIPE_CONFIG__ADDR_SURF_P4_16x32:
        case SI__PIPE_CONFIG__ADDR_SURF_P4_32x32:
            *num_pipes = 4;
            break;
        case SI__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16:
        case SI__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16:
        case SI__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16:
        case SI__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16:
        case SI__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16:
        case SI__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32:
        case SI__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32:
            *num_pipes = 8;
            break;
        }
    }
    if (num_banks) {
        switch (SI__GB_TILE_MODE__NUM_BANKS(gb_tile_mode)) {
        default:
        case SI__NUM_BANKS__2_BANK:
            *num_banks = 2;
            break;
        case SI__NUM_BANKS__4_BANK:
            *num_banks = 4;
            break;
        case SI__NUM_BANKS__8_BANK:
            *num_banks = 8;
            break;
        case SI__NUM_BANKS__16_BANK:
            *num_banks = 16;
            break;
        }
    }
    if (macro_tile_aspect) {
        switch (SI__GB_TILE_MODE__MACRO_TILE_ASPECT(gb_tile_mode)) {
        default:
        case SI__MACRO_TILE_ASPECT__1:
            *macro_tile_aspect = 1;
            break;
        case SI__MACRO_TILE_ASPECT__2:
            *macro_tile_aspect = 2;
            break;
        case SI__MACRO_TILE_ASPECT__4:
            *macro_tile_aspect = 4;
            break;
        case SI__MACRO_TILE_ASPECT__8:
            *macro_tile_aspect = 8;
            break;
        }
    }
    if (bank_w) {
        switch (SI__GB_TILE_MODE__BANK_WIDTH(gb_tile_mode)) {
        default:
        case SI__BANK_WIDTH__1:
            *bank_w = 1;
            break;
        case SI__BANK_WIDTH__2:
            *bank_w = 2;
            break;
        case SI__BANK_WIDTH__4:
            *bank_w = 4;
            break;
        case SI__BANK_WIDTH__8:
            *bank_w = 8;
            break;
        }
    }
    if (bank_h) {
        switch (SI__GB_TILE_MODE__BANK_HEIGHT(gb_tile_mode)) {
        default:
        case SI__BANK_HEIGHT__1:
            *bank_h = 1;
            break;
        case SI__BANK_HEIGHT__2:
            *bank_h = 2;
            break;
        case SI__BANK_HEIGHT__4:
            *bank_h = 4;
            break;
        case SI__BANK_HEIGHT__8:
            *bank_h = 8;
            break;
        }
    }
    if (tile_split) {
        switch (SI__GB_TILE_MODE__TILE_SPLIT(gb_tile_mode)) {
        default:
        case SI__TILE_SPLIT__64B:
            *tile_split = 64;
            break;
        case SI__TILE_SPLIT__128B:
            *tile_split = 128;
            break;
        case SI__TILE_SPLIT__256B:
            *tile_split = 256;
            break;
        case SI__TILE_SPLIT__512B:
            *tile_split = 512;
            break;
        case SI__TILE_SPLIT__1024B:
            *tile_split = 1024;
            break;
        case SI__TILE_SPLIT__2048B:
            *tile_split = 2048;
            break;
        case SI__TILE_SPLIT__4096B:
            *tile_split = 4096;
            break;
        }
    }
}

static int si_init_hw_info(struct radeon_surface_manager *surf_man)
{
    uint32_t tiling_config;
    drmVersionPtr version;
    int r;

    r = radeon_get_value(surf_man->fd, RADEON_INFO_TILING_CONFIG,
                         &tiling_config);
    if (r) {
        return r;
    }

    surf_man->hw_info.allow_2d = 0;
    version = drmGetVersion(surf_man->fd);
    if (version && version->version_minor >= 33) {
        if (!radeon_get_value(surf_man->fd, RADEON_INFO_SI_TILE_MODE_ARRAY, surf_man->hw_info.tile_mode_array)) {
            surf_man->hw_info.allow_2d = 1;
        }
    }
    drmFreeVersion(version);

    switch (tiling_config & 0xf) {
    case 0:
        surf_man->hw_info.num_pipes = 1;
        break;
    case 1:
        surf_man->hw_info.num_pipes = 2;
        break;
    case 2:
        surf_man->hw_info.num_pipes = 4;
        break;
    case 3:
        surf_man->hw_info.num_pipes = 8;
        break;
    default:
        surf_man->hw_info.num_pipes = 8;
        surf_man->hw_info.allow_2d = 0;
        break;
    }

    switch ((tiling_config & 0xf0) >> 4) {
    case 0:
        surf_man->hw_info.num_banks = 4;
        break;
    case 1:
        surf_man->hw_info.num_banks = 8;
        break;
    case 2:
        surf_man->hw_info.num_banks = 16;
        break;
    default:
        surf_man->hw_info.num_banks = 8;
        surf_man->hw_info.allow_2d = 0;
        break;
    }

    switch ((tiling_config & 0xf00) >> 8) {
    case 0:
        surf_man->hw_info.group_bytes = 256;
        break;
    case 1:
        surf_man->hw_info.group_bytes = 512;
        break;
    default:
        surf_man->hw_info.group_bytes = 256;
        surf_man->hw_info.allow_2d = 0;
        break;
    }

    switch ((tiling_config & 0xf000) >> 12) {
    case 0:
        surf_man->hw_info.row_size = 1024;
        break;
    case 1:
        surf_man->hw_info.row_size = 2048;
        break;
    case 2:
        surf_man->hw_info.row_size = 4096;
        break;
    default:
        surf_man->hw_info.row_size = 4096;
        surf_man->hw_info.allow_2d = 0;
        break;
    }
    return 0;
}

static int si_surface_sanity(struct radeon_surface_manager *surf_man,
                             struct radeon_surface *surf,
                             unsigned mode, unsigned *tile_mode, unsigned *stencil_tile_mode)
{
    uint32_t gb_tile_mode;

    /* check surface dimension */
    if (surf->npix_x > 16384 || surf->npix_y > 16384 || surf->npix_z > 16384) {
        return -EINVAL;
    }

    /* check mipmap last_level */
    if (surf->last_level > 15) {
        return -EINVAL;
    }

    /* force 1d on kernel that can't do 2d */
    if (mode > RADEON_SURF_MODE_1D &&
        (!surf_man->hw_info.allow_2d || !(surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX))) {
        if (surf->nsamples > 1) {
            fprintf(stderr, "radeon: Cannot use 1D tiling for an MSAA surface (%i).\n", __LINE__);
            return -EFAULT;
        }
        mode = RADEON_SURF_MODE_1D;
        surf->flags = RADEON_SURF_CLR(surf->flags, MODE);
        surf->flags |= RADEON_SURF_SET(mode, MODE);
    }

    if (surf->nsamples > 1 && mode != RADEON_SURF_MODE_2D) {
        return -EINVAL;
    }

    if (!surf->tile_split) {
        /* default value */
        surf->mtilea = 1;
        surf->bankw = 1;
        surf->bankh = 1;
        surf->tile_split = 64;
        surf->stencil_tile_split = 64;
    }

    switch (mode) {
    case RADEON_SURF_MODE_2D:
        if (surf->flags & RADEON_SURF_SBUFFER) {
            switch (surf->nsamples) {
            case 1:
                *stencil_tile_mode = SI_TILE_MODE_DEPTH_STENCIL_2D;
                break;
            case 2:
                *stencil_tile_mode = SI_TILE_MODE_DEPTH_STENCIL_2D_2AA;
                break;
            case 4:
                *stencil_tile_mode = SI_TILE_MODE_DEPTH_STENCIL_2D_4AA;
                break;
            case 8:
                *stencil_tile_mode = SI_TILE_MODE_DEPTH_STENCIL_2D_8AA;
                break;
            default:
                return -EINVAL;
            }
            /* retrieve tiling mode value */
            gb_tile_mode = surf_man->hw_info.tile_mode_array[*stencil_tile_mode];
            si_gb_tile_mode(gb_tile_mode, NULL, NULL, NULL, NULL, NULL, &surf->stencil_tile_split);
        }
        if (surf->flags & RADEON_SURF_ZBUFFER) {
            switch (surf->nsamples) {
            case 1:
                *tile_mode = SI_TILE_MODE_DEPTH_STENCIL_2D;
                break;
            case 2:
                *tile_mode = SI_TILE_MODE_DEPTH_STENCIL_2D_2AA;
                break;
            case 4:
                *tile_mode = SI_TILE_MODE_DEPTH_STENCIL_2D_4AA;
                break;
            case 8:
                *tile_mode = SI_TILE_MODE_DEPTH_STENCIL_2D_8AA;
                break;
            default:
                return -EINVAL;
            }
        } else if (surf->flags & RADEON_SURF_SCANOUT) {
            switch (surf->bpe) {
            case 2:
                *tile_mode = SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP;
                break;
            case 4:
                *tile_mode = SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP;
                break;
            default:
                return -EINVAL;
            }
        } else {
            switch (surf->bpe) {
            case 1:
                *tile_mode = SI_TILE_MODE_COLOR_2D_8BPP;
                break;
            case 2:
                *tile_mode = SI_TILE_MODE_COLOR_2D_16BPP;
                break;
            case 4:
                *tile_mode = SI_TILE_MODE_COLOR_2D_32BPP;
                break;
            case 8:
            case 16:
                *tile_mode = SI_TILE_MODE_COLOR_2D_64BPP;
                break;
            default:
                return -EINVAL;
            }
        }
        /* retrieve tiling mode value */
        gb_tile_mode = surf_man->hw_info.tile_mode_array[*tile_mode];
        si_gb_tile_mode(gb_tile_mode, NULL, NULL, &surf->mtilea, &surf->bankw, &surf->bankh, &surf->tile_split);
        break;
    case RADEON_SURF_MODE_1D:
        if (surf->flags & RADEON_SURF_SBUFFER) {
            *stencil_tile_mode = SI_TILE_MODE_DEPTH_STENCIL_1D;
        }
        if (surf->flags & RADEON_SURF_ZBUFFER) {
            *tile_mode = SI_TILE_MODE_DEPTH_STENCIL_1D;
        } else if (surf->flags & RADEON_SURF_SCANOUT) {
            *tile_mode = SI_TILE_MODE_COLOR_1D_SCANOUT;
        } else {
            *tile_mode = SI_TILE_MODE_COLOR_1D;
        }
        break;
    case RADEON_SURF_MODE_LINEAR_ALIGNED:
    default:
        *tile_mode = SI_TILE_MODE_COLOR_LINEAR_ALIGNED;
    }

    return 0;
}

static void si_surf_minify(struct radeon_surface *surf,
                           struct radeon_surface_level *surflevel,
                           unsigned bpe, unsigned level,
                           uint32_t xalign, uint32_t yalign, uint32_t zalign,
                           uint32_t slice_align, unsigned offset)
{
    if (level == 0) {
        surflevel->npix_x = surf->npix_x;
    } else {
        surflevel->npix_x = mip_minify(next_power_of_two(surf->npix_x), level);
    }
    surflevel->npix_y = mip_minify(surf->npix_y, level);
    surflevel->npix_z = mip_minify(surf->npix_z, level);

    if (level == 0 && surf->last_level > 0) {
        surflevel->nblk_x = (next_power_of_two(surflevel->npix_x) + surf->blk_w - 1) / surf->blk_w;
        surflevel->nblk_y = (next_power_of_two(surflevel->npix_y) + surf->blk_h - 1) / surf->blk_h;
        surflevel->nblk_z = (next_power_of_two(surflevel->npix_z) + surf->blk_d - 1) / surf->blk_d;
    } else {
        surflevel->nblk_x = (surflevel->npix_x + surf->blk_w - 1) / surf->blk_w;