| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2007-03-13 | r300: Renamed the CACHE_CTLSTAT values to include UNKNOWN in the name; not | Oliver McFadden | |
| enough information is known about them to be sure as to what the values mean. | |||
| 2007-03-13 | Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline | Nian Wu | |
| 2007-03-13 | Add defines for the values written to R300_RB3D_ZCACHE_CTLSTAT. | Oliver McFadden | |
| Note that just like the values written to R300_RB3D_DSTCACHE_CTLSTAT these values are really unknown; ideally more reverse engineering should be done to determine what these values mean and when they should be set. | |||
| 2007-03-13 | nouveau: make sure cmdbuf object gets destroyed | Ben Skeggs | |
| 2007-03-13 | nouveau: associate all created objects with a channel + cleanups | Ben Skeggs | |
| 2007-03-13 | nouveau: s/fifo/channel/ | Ben Skeggs | |
| 2007-03-13 | Corrected values written to R300_RB3D_DSTCACHE_CTLSTAT to either | Oliver McFadden | |
| R300_RB3D_DSTCACHE_02 or R300_RB3D_DSTCACHE_0A, rather than hexadecimal values. | |||
| 2007-03-13 | Guess another unknown register used for R300 pacification. | Oliver McFadden | |
| 2007-03-12 | Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline | Nian Wu | |
| 2007-03-11 | nouveau: PUT,GET, not 2xPUT | Patrice Mandin | |
| 2007-03-07 | Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline | Nian Wu | |
| 2007-03-07 | Add via CX700. | Thomas Hellstrom | |
| 2007-03-05 | Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline | Nian Wu | |
| 2007-03-04 | radeon: make PCI GART aperture size variable, but making table size variable | Dave Airlie | |
| This is precursor to getting a TTM backend for this stuff, and also allows the PCI table to be allocated at fb 0 | |||
| 2007-03-04 | ati: make pcigart code able to handle variable size PCI GART aperture | Dave Airlie | |
| This code doesn't enable a variable aperture it just modifies the codebase to allow me fix it up later | |||
| 2007-03-01 | Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline | Nian Wu | |
| 2007-02-28 | nouveau: intrusive drm interface changes | Ben Skeggs | |
| graphics objects: - No longer takes flags/dmaobj parameters, requires some major changes to the ddx to setup the object through the FIFO. This change is likely to cause breakages on some cards (tested on NV05,NV28,NV35, NV40 and NV4E). dma objects: - now takes a "class" parameter, not really used yet but we may need it at some point. - parameters are checked, so clients can't randomly create DMA objects pointing at whatever they feel like. misc: - Added FB_SIZE/AGP_SIZE getparams - Read PFIFO_INTR in PFIFO irq handler, not PMC_INTR - Dump PGRAPH trap info on PGRAPH_INTR_NOTIFY if NSOURCE isn't NOTIFICATION_PENDING. | |||
| 2007-02-25 | Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline | Nian Wu | |
| 2007-02-25 | drm: remove unnecessary NULL checks, and fix some indents.. | Jakob Bornecrantz | |
| 2007-02-16 | Simple fence object sample driver for via, based on idling the GPU. | Thomas Hellstrom | |
| Buffer object driver for via. Some changes to buffer object driver callbacks. Improve fence flushing. | |||
| 2007-02-15 | Initial support for fence object classes. | Thomas Hellstrom | |
| (Fence objects belonging to different command submission mechanisms). | |||
| 2007-02-14 | Merge branch 'ttm-vram-0-1-branch' | Thomas Hellstrom | |
| 2007-02-14 | Remove an intel-specific hack and replace it with a fence driver callback. | Thomas Hellstrom | |
| 2007-02-14 | nouveau: fix the build on big endian (thanks CyberFoxx) | Stephane Marchesin | |
| 2007-02-14 | nouveau: fix memory initialization with multiple cards. | B. Rathmann | |
| 2007-02-13 | Bugzilla Bug #9457 | Thomas Hellstrom | |
| Add refcounting of user waiters to the DRM hardware lock, so that we can use the DRM_LOCK_CONT flag more conservatively. Also add a kernel waiter refcount that if nonzero transfers the lock for the kernel context, when it is released. This is useful when waiting for idle and can be used for very simple fence object driver implementations for the new memory manager. It also resolves the AIGLX startup deadlock for the sis and the via drivers. i810, i830 still require that the hardware lock is really taken so the deadlock remains for those two. I'm not sure about ffb. Anyone familiar with that code? | |||
| 2007-02-13 | i915: Add 965GM pci id update | Wang Zhenyu | |
| 2007-02-12 | Update flags and comments. | Thomas Hellstrom | |
| 2007-02-11 | Sync r300_reg.h from mesa driver. #10210 | Aapo Tahkola | |
| 2007-03-10 | Merge branch 'i915-pageflip' | Michel Dänzer | |
| 2007-03-10 | i915: Only wait for pending flips before asynchronous flips again. | Michel Dänzer | |
| 2007-03-09 | i915: Do not wait for pending flips on both pipes at the same time. | Michel Dänzer | |
| The MI_WAIT_FOR_EVENT instruction does not support waiting for several events at once, so this should fix the lockups with page flipping when both pipes are enabled. | |||
| 2007-03-07 | nouveau: remove a hack that's not needed since the last interface change. | Ben Skeggs | |
| 2007-03-07 | nouveau: ack PFIFO interrupts at PFIFO, not PMC. | Ben Skeggs | |
| 2007-02-28 | i915: Eliminate dev_priv->current_page. | Michel Dänzer | |
| Always use dev_priv->sarea_priv->pf_current_page directly. This allows clients to modify it as well while they hold the HW lock, e.g. in order to sync pages between pipes. | |||
| 2007-02-28 | i915: Only clean up page flipping when the last client goes away, not any one. | Michel Dänzer | |
| 2007-02-28 | i915: Don't emit waits for pending flips before emitting synchronous flips. | Michel Dänzer | |
| The assumption is that synchronous flips are not isolated usually, and waiting for all of them could result in stalling the pipeline for long periods of time. Also use i915_emit_mi_flush() instead of an old-fashioned way to achieve the same effect. | |||
| 2007-02-28 | i915: Fix test for synchronous flip affecting both pipes. | Michel Dänzer | |
| 2007-02-22 | i915: Add support for scheduled buffer swaps to be done as flips. | Michel Dänzer | |
| Unfortunately, emitting asynchronous flips during vertical blank results in tearing. So we have to wait for the previous vertical blank and emit a synchronous flip. | |||
| 2007-02-22 | Add DRM_VBLANK_FLIP. | Michel Dänzer | |
| Used to request that a scheduled buffer swap be done as a flip instead of a blit. | |||
| 2007-02-19 | i915: Improved page flipping support, including triple buffering. | Michel Dänzer | |
| Pages are tracked independently on each pipe. Bump the minor version for 3D clients to know page flipping is usable, and bump driver date. | |||
| 2007-02-19 | i915: Page flipping enhancements. | Michel Dänzer | |
| Leave it to the client to wait for the flip to complete when necessary, but wait for a previous flip to complete before emitting another one. This should help avoid unnecessary stalling of the ring due to pending flips. Call i915_do_cleanup_pageflip() unconditionally in preclose. | |||
| 2007-02-19 | i915: Unify breadcrumb emission. | Michel Dänzer | |
| 2007-02-09 | I915 accelerated blit copy functional. | Thomas Hellstrom | |
| Fixed - to System memory copies are implemented by flipping in a cache-coherent TTM, blitting to it, and then flipping it out. | |||
| 2007-02-07 | Warning fix: correct type of i915_mmio argument. | Eric Anholt | |
| 2007-02-07 | Define __iomem for systems without it. | Eric Anholt | |
| 2007-02-07 | Add chip family flags to i915 driver, and fix a missing '"' in mach64 ID list. | Eric Anholt | |
| 2007-02-07 | Checkpoint commit. | Thomas Hellstrom | |
| Flag handling and memory type selection cleanup. glxgears won't start. | |||
| 2007-02-06 | Implement a policy for selecting memory types. | Thomas Hellstrom | |
| 2007-02-06 | nouveau: more work on the nv04 context switch code. | Stephane Marchesin | |
 |
index : renesas/drm.git | |
| libdrm, cloned from git://anongit.freedesktop.org/mesa/drm | Laurent Pinchart |
| summaryrefslogtreecommitdiff |
path: root/shared-core