diff options
| author | Dave Airlie <airlied@linux.ie> | 2007-03-04 18:13:34 +1100 |
|---|---|---|
| committer | Dave Airlie <airlied@linux.ie> | 2007-03-04 18:16:29 +1100 |
| commit | c9178c3d01f6f38a33f9624c620d290cb9036964 (patch) | |
| tree | 115ff3c53b8ab88f6eae0523e2674a1101bc82b2 /shared-core | |
| parent | 72caa48c82e4334d3292185dbadf758d2dd14c16 (diff) | |
ati: make pcigart code able to handle variable size PCI GART aperture
This code doesn't enable a variable aperture it just modifies the codebase
to allow me fix it up later
Diffstat (limited to 'shared-core')
| -rw-r--r-- | shared-core/r128_cce.c | 1 | ||||
| -rw-r--r-- | shared-core/r128_drv.h | 2 | ||||
| -rw-r--r-- | shared-core/radeon_cp.c | 3 |
3 files changed, 5 insertions, 1 deletions
diff --git a/shared-core/r128_cce.c b/shared-core/r128_cce.c index f9a9eb32..62859d5a 100644 --- a/shared-core/r128_cce.c +++ b/shared-core/r128_cce.c @@ -560,6 +560,7 @@ static int r128_do_init_cce(drm_device_t * dev, drm_r128_init_t * init) if (dev_priv->is_pci) { #endif dev_priv->gart_info.gart_table_location = DRM_ATI_GART_MAIN; + dev_priv->gart_info.table_size = R128_PCIGART_TABLE_SIZE; dev_priv->gart_info.addr = NULL; dev_priv->gart_info.bus_addr = 0; dev_priv->gart_info.is_pcie = 0; diff --git a/shared-core/r128_drv.h b/shared-core/r128_drv.h index f1efb49d..90868356 100644 --- a/shared-core/r128_drv.h +++ b/shared-core/r128_drv.h @@ -383,6 +383,8 @@ extern long r128_compat_ioctl(struct file *filp, unsigned int cmd, #define R128_PERFORMANCE_BOXES 0 +#define R128_PCIGART_TABLE_SIZE 32768 + #define R128_READ(reg) DRM_READ32( dev_priv->mmio, (reg) ) #define R128_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) ) #define R128_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) ) diff --git a/shared-core/radeon_cp.c b/shared-core/radeon_cp.c index 0fa6535d..976b9fbd 100644 --- a/shared-core/radeon_cp.c +++ b/shared-core/radeon_cp.c @@ -1622,6 +1622,7 @@ static int radeon_do_init_cp(drm_device_t * dev, drm_radeon_init_t * init) } else #endif { + dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE; /* if we have an offset set from userspace */ if (dev_priv->pcigart_offset) { dev_priv->gart_info.bus_addr = @@ -1629,7 +1630,7 @@ static int radeon_do_init_cp(drm_device_t * dev, drm_radeon_init_t * init) dev_priv->gart_info.mapping.offset = dev_priv->gart_info.bus_addr; dev_priv->gart_info.mapping.size = - RADEON_PCIGART_TABLE_SIZE; + dev_priv->gart_info.table_size; drm_core_ioremap(&dev_priv->gart_info.mapping, dev); dev_priv->gart_info.addr = |