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2007-07-18nouveau: Make nouveau_wait_for_idle() read PTIMER.Pekka Paalanen
Following my nv28 kmmio dumps, nouveau_wait_for_idle() is modified to read PTIMER and NV03_PMC_ENABLE. Also a timeout based on PTIMER value is added, so wait_for_idle() cannot stall indefinitely (unless PTIMER is halted). The timeout was selected as 1 giga-ticks, which for me is 1s.
2007-07-18nouveau: Add read() method to Engine.timer.Pekka Paalanen
This is not called from anywhere, yet.
2007-07-18nouveau: Add bitfield names for NSOURCE and NSTATUS.Pekka Paalanen
Name strings and pretty-printing in nouveau_graph_dump_trap_info().
2007-07-18nouveau: Replace 0x00400104 and 0x00400108 with names.Pekka Paalanen
NV03_PGRAPH_NSTATUS and NV03_PGRAPH_NSOURCE. The prefix NV03 is chosen because nv10reg.h had no versioned prefix, and the code using these registers does not check card_type.
2007-07-18fix some missing whitespace/tabDave Airlie
2007-07-18drm: remove drm_u64_t, replace with uint64_t everwhereDave Airlie
This might break something, stdint.h inclusion in drm.h maybe required but I'm not sure yet what platforms have it what ones don't.
2007-07-17nouveau: Destroy PGRAPH context table on PGRAPH takedownBen Skeggs
2007-07-17nouveau: G8x PCIEGARTBen Skeggs
Actually a NV04-NV50 ttm backend for both PCI and PCIEGART, but PCIGART support for G8X using the current mm has been hacked on top of it.
2007-07-16Correct errors in the usage of pci_map_page.Ian Romanick
With these changes the driver no longer instantly hard-locks a 6600LE on a PowerPC G5. I haven't tested any 3D apps yet.
2007-07-16drm: remove drm_buf_tDave Airlie
2007-07-16drm: detypedef ttm/bo/fence codeDave Airlie
2007-07-16drm: remove hashtab/sman and object typedefsDave Airlie
2007-07-16drm: remove drmP.h internal typedefsDave Airlie
2007-07-16drm: remove ttm userspace typedefsDave Airlie
2007-07-16drm: detypedef drm.h and fixup all problemsDave Airlie
2007-07-16drm: remove typedefs in drm.h to their own sectionDave Airlie
2007-07-16Merge branch 'drm-ttm-cleanup-branch'Dave Airlie
2007-07-14nouveau: nv10 and nv11/15 are differentPatrice Mandin
2007-07-13applied patch from Ian Romanick fixing PCI DMA object creation codeArthur Huillet
2007-07-13now attempting to create PCI object only when there is a pci_heapArthur Huillet
2007-07-13nouveau: nuke internal typedefs, and drm_device_t use.Ben Skeggs
2007-07-13nouveau: unbreak AGPBen Skeggs
2007-07-12nouveau: mem_alloc() returns offsets, not absolute addresses now.Ben Skeggs
2007-07-12nouveau: nuke left over debug messageBen Skeggs
2007-07-12nouveau: separate region_offset into map_handle and offset.Ben Skeggs
2007-07-12fixed object creation code to not Oops on 64bits, worked around memalloc not ↵Arthur Huillet
working on 64bit for PCIGART
2007-07-11NV50 will not attempt to use PCIGART nowArthur Huillet
2007-07-11fixed bug that prevented PCIE cards from actually using PCIGART - NV50 will ↵Arthur Huillet
probably still have a problem
2007-07-11nouveau/nv50: G80 fixes.Ben Skeggs
Again, no hardware, so no idea if it'll even work yet. I understand how the PRAMIN setup works now, un-hardcoding stuff will come "RealSoonNow(tm)".
2007-07-11nouveau: Some checks on userspace object handles.Ben Skeggs
2007-07-11Merge branch 'master' into cleanupDave Airlie
Conflicts: libdrm/xf86drm.c linux-core/drm_bo.c linux-core/drm_fence.c
2007-07-11Added support for PCIGART for PCI(E) cards. Bumped DRM interface patchlevel.Arthur Huillet
2007-07-09nouveau: Allocate mappable VRAM for notifiers..Ben Skeggs
2007-07-09nouveau: Don't be so strict on <NV50Ben Skeggs
2007-07-09nouveau: Avoid oopsBen Skeggs
Turns out lastclose() gets called even if firstopen() has never been...
2007-07-09nouveau/nv50: Initial channel/object supportBen Skeggs
Should be OK on G84 for a single channel, multiple channels *almost* work. Untested on G80.
2007-07-09nouveau: enable reporting for all PFIFO/PGRAPH irqsBen Skeggs
2007-07-09nouveau: rewrite gpu object codeBen Skeggs
Allows multiple references to a single object, needed to support PCI(E)GART scatter-gather DMA objects which would quickly fill PRAMIN if each channel had its own. Handle per-channel private instmem areas. This is needed to support NV50, but might be something we want to do on earlier chipsets at some point? Everything that touches PRAMIN is a GPU object.
2007-07-03One more spinlock initializer cleanup.Michel Dänzer
2007-06-29nouveau: small RAMFC cleanupsBen Skeggs
2007-06-28nouveau: Hack around possible Xv blit adaptor breakageBen Skeggs
2007-06-28nouveau/nv10: Fix earlier NV1x chipsBen Skeggs
Can't use nv04 code for them, since an extra field was inserted into RAMFC after DMA_PUT/GET.
2007-06-28nouveau: never touch PRAMIN with NV_WRITE, cleanup RAMHT code a bitBen Skeggs
2007-06-28nouveau: simplify PRAMIN accessBen Skeggs
2007-06-28nouveau: name some regsBen Skeggs
2007-06-28nouveau/nv50: skeletal backendBen Skeggs
2007-06-28nouveau: Nuke DMA_OBJECT_INIT ioctl (bumps interface to 0.0.7)Ben Skeggs
For various reasons, this ioctl was a bad idea. At channel creation we now automatically create DMA objects covering available VRAM and GART memory, where the client used to do this themselves. However, there is still a need to be able to create DMA objects pointing at specific areas of memory (ie. notifiers). Each channel is now allocated a small amount of memory from which a client can suballocate things (such as notifiers), and have a DMA object created which covers the suballocated area. The NOTIFIER_ALLOC ioctl exposes this functionality.
2007-06-28nouveau/nv04: Set NV_PFIFO_CACHE1_PUSH1 correctly + small tweaksBen Skeggs
2007-06-26More 64-bit padding.Thomas Hellstrom
2007-06-26Add support SiS based XGI chips to SiS DRM.Ian Romanick
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