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authorBen Skeggs <skeggsb@gmail.com>2007-06-28 04:23:17 +1000
committerBen Skeggs <skeggsb@gmail.com>2007-06-28 04:23:17 +1000
commit2dd85772aa4e134730f294d77b4ff030a175a4ab (patch)
tree5cad4c6fd8e350aa3e8de6e3933027b40fbd7278 /shared-core
parent68ecf61647e9ec16d59cc8f50550d11478eb3118 (diff)
nouveau/nv10: Fix earlier NV1x chips
Can't use nv04 code for them, since an extra field was inserted into RAMFC after DMA_PUT/GET.
Diffstat (limited to 'shared-core')
-rw-r--r--shared-core/nouveau_state.c7
-rw-r--r--shared-core/nv10_fifo.c57
2 files changed, 34 insertions, 30 deletions
diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c
index 94d8081c..fa773d28 100644
--- a/shared-core/nouveau_state.c
+++ b/shared-core/nouveau_state.c
@@ -129,17 +129,10 @@ static int nouveau_init_engine_ptrs(drm_device_t *dev)
engine->graph.save_context = nv10_graph_save_context;
engine->fifo.init = nouveau_fifo_init;
engine->fifo.takedown = nouveau_stub_takedown;
- if (dev_priv->chipset < 0x17) {
- engine->fifo.create_context = nv04_fifo_create_context;
- engine->fifo.destroy_context = nv04_fifo_destroy_context;
- engine->fifo.load_context = nv04_fifo_load_context;
- engine->fifo.save_context = nv04_fifo_save_context;
- } else {
engine->fifo.create_context = nv10_fifo_create_context;
engine->fifo.destroy_context = nv10_fifo_destroy_context;
engine->fifo.load_context = nv10_fifo_load_context;
engine->fifo.save_context = nv10_fifo_save_context;
- }
break;
case 0x20:
engine->mc.init = nv04_mc_init;
diff --git a/shared-core/nv10_fifo.c b/shared-core/nv10_fifo.c
index 710a47f7..b84971de 100644
--- a/shared-core/nv10_fifo.c
+++ b/shared-core/nv10_fifo.c
@@ -30,20 +30,20 @@
#define RAMFC_WR(offset, val) NV_WI32(fifoctx + NV10_RAMFC_##offset, (val))
#define RAMFC_RD(offset) NV_RI32(fifoctx + NV10_RAMFC_##offset)
-#define NV10_FIFO_CONTEXT_SIZE 64
+#define NV10_RAMFC(c) (dev_priv->ramfc_offset + NV10_RAMFC__SIZE)
+#define NV10_RAMFC__SIZE ((dev_priv->chipset) >= 0x17 ? 64 : 32)
int
nv10_fifo_create_context(drm_device_t *dev, int channel)
{
drm_nouveau_private_t *dev_priv = dev->dev_private;
struct nouveau_fifo *chan = &dev_priv->fifos[channel];
- uint32_t fifoctx, pushbuf;
+ uint32_t fifoctx = NV10_RAMFC(channel), pushbuf;
int i;
pushbuf = nouveau_chip_instance_get(dev, chan->cmdbuf_obj->instance);
- fifoctx = dev_priv->ramfc_offset + channel*64;
- for (i=0; i<NV10_FIFO_CONTEXT_SIZE;i+=4)
+ for (i=0; i<NV10_RAMFC__SIZE; i+=4)
NV_WI32(fifoctx + i, 0);
/* Fill entries that are seen filled in dumps of nvidia driver just
@@ -67,11 +67,10 @@ void
nv10_fifo_destroy_context(drm_device_t *dev, int channel)
{
drm_nouveau_private_t *dev_priv = dev->dev_private;
- uint32_t fifoctx;
+ uint32_t fifoctx = NV10_RAMFC(channel);
int i;
- fifoctx = dev_priv->ramfc_offset + channel*64;
- for (i=0; i<NV10_FIFO_CONTEXT_SIZE;i+=4)
+ for (i=0; i<NV10_RAMFC__SIZE; i+=4)
NV_WI32(fifoctx + i, 0);
}
@@ -79,11 +78,9 @@ int
nv10_fifo_load_context(drm_device_t *dev, int channel)
{
drm_nouveau_private_t *dev_priv = dev->dev_private;
- uint32_t fifoctx;
+ uint32_t fifoctx = NV10_RAMFC(channel);
uint32_t tmp;
- fifoctx = dev_priv->ramfc_offset + channel*64;
-
NV_WRITE(NV03_PFIFO_CACHE1_PUSH1 , 0x00000100 | channel);
NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET , RAMFC_RD(DMA_GET));
@@ -98,11 +95,19 @@ nv10_fifo_load_context(drm_device_t *dev, int channel)
NV_WRITE(NV04_PFIFO_CACHE1_DMA_FETCH , RAMFC_RD(DMA_FETCH));
NV_WRITE(NV04_PFIFO_CACHE1_ENGINE , RAMFC_RD(ENGINE));
NV_WRITE(NV04_PFIFO_CACHE1_PULL1 , RAMFC_RD(PULL1_ENGINE));
- NV_WRITE(NV10_PFIFO_CACHE1_ACQUIRE_VALUE , RAMFC_RD(ACQUIRE_VALUE));
- NV_WRITE(NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP, RAMFC_RD(ACQUIRE_TIMESTAMP));
- NV_WRITE(NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT , RAMFC_RD(ACQUIRE_TIMEOUT));
- NV_WRITE(NV10_PFIFO_CACHE1_SEMAPHORE , RAMFC_RD(SEMAPHORE));
- NV_WRITE(NV10_PFIFO_CACHE1_DMA_SUBROUTINE , RAMFC_RD(DMA_SUBROUTINE));
+
+ if (dev_priv->chipset >= 0x17) {
+ NV_WRITE(NV10_PFIFO_CACHE1_ACQUIRE_VALUE,
+ RAMFC_RD(ACQUIRE_VALUE));
+ NV_WRITE(NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP,
+ RAMFC_RD(ACQUIRE_TIMESTAMP));
+ NV_WRITE(NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT,
+ RAMFC_RD(ACQUIRE_TIMEOUT));
+ NV_WRITE(NV10_PFIFO_CACHE1_SEMAPHORE,
+ RAMFC_RD(SEMAPHORE));
+ NV_WRITE(NV10_PFIFO_CACHE1_DMA_SUBROUTINE,
+ RAMFC_RD(DMA_SUBROUTINE));
+ }
/* Reset NV04_PFIFO_CACHE1_DMA_CTL_AT_INFO to INVALID */
tmp = NV_READ(NV04_PFIFO_CACHE1_DMA_CTL) & ~(1<<31);
@@ -115,11 +120,9 @@ int
nv10_fifo_save_context(drm_device_t *dev, int channel)
{
drm_nouveau_private_t *dev_priv = dev->dev_private;
- uint32_t fifoctx;
+ uint32_t fifoctx = NV10_RAMFC(channel);
uint32_t tmp;
- fifoctx = dev_priv->ramfc_offset + channel*64;
-
RAMFC_WR(DMA_PUT , NV_READ(NV04_PFIFO_CACHE1_DMA_PUT));
RAMFC_WR(DMA_GET , NV_READ(NV04_PFIFO_CACHE1_DMA_GET));
RAMFC_WR(REF_CNT , NV_READ(NV10_PFIFO_CACHE1_REF_CNT));
@@ -132,11 +135,19 @@ nv10_fifo_save_context(drm_device_t *dev, int channel)
RAMFC_WR(DMA_FETCH , NV_READ(NV04_PFIFO_CACHE1_DMA_FETCH));
RAMFC_WR(ENGINE , NV_READ(NV04_PFIFO_CACHE1_ENGINE));
RAMFC_WR(PULL1_ENGINE , NV_READ(NV04_PFIFO_CACHE1_PULL1));
- RAMFC_WR(ACQUIRE_VALUE , NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_VALUE));
- RAMFC_WR(ACQUIRE_TIMESTAMP, NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP));
- RAMFC_WR(ACQUIRE_TIMEOUT , NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT));
- RAMFC_WR(SEMAPHORE , NV_READ(NV10_PFIFO_CACHE1_SEMAPHORE));
- RAMFC_WR(DMA_SUBROUTINE , NV_READ(NV04_PFIFO_CACHE1_DMA_GET));
+
+ if (dev_priv->chipset >= 0x17) {
+ RAMFC_WR(ACQUIRE_VALUE,
+ NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_VALUE));
+ RAMFC_WR(ACQUIRE_TIMESTAMP,
+ NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP));
+ RAMFC_WR(ACQUIRE_TIMEOUT,
+ NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT));
+ RAMFC_WR(SEMAPHORE,
+ NV_READ(NV10_PFIFO_CACHE1_SEMAPHORE));
+ RAMFC_WR(DMA_SUBROUTINE,
+ NV_READ(NV04_PFIFO_CACHE1_DMA_GET));
+ }
return 0;
}