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2007-04-29radeon: Don't mess up page flipping when a file descriptor is closed.Michel Dänzer
There can still be other contexts that may use page flipping later on, so don't just unilaterally 'clean it up', which could lead to the wrong page being displayed, e.g. when running 3D apps with a GLX compositing manager such as compiz using page flipping.
2007-04-28move i915 to new drm_wait_on functionDave Airlie
2007-04-28remove DRM_GETSAREA and replace with drm_getsarea functionDave Airlie
2007-04-26Revert "bug 7092 : add pci ids for mach64 in Dell poweredge 4200"George Sapountzis
This reverts commit 255f3e6f76dfd267a14765dd1293229184298d89. Rage IIc does not have a vertex setup engine.
2007-04-26freebsd: remove stray apperance of IN_MODULE.George Sapountzis
The xserver no longer uses the libc-wrapper.
2007-04-26Add new buffer object type for kernel allocations that don't initially have ↵Jesse Barnes
a user mapping. (cherry picked from commit 2e21779992bd5026d8ec4dea52466377dbe5a0ed)
2007-04-23nouveau: fix wacky pci idStephane Marchesin
2007-04-17via: Make sure we flush write-combining using a follow-up read.Thomas Hellstrom
2007-04-10nouveau: nv10 per channel init from ddxMatthieu Castet
2007-04-09rs480: Renamed some unknown registers. See dri-devel list.Oliver McFadden
2007-04-09nouveau: NV46 supportBen Skeggs
2007-04-09radeon: bump version for IGPGART supportDave Airlie
2007-04-09radeon: add support for reverse engineered xpress200mDave Airlie
The IGPGART setup code was traced using mmio-trace on fglrx by myself and Phillip Ezolt <phillipezolt@gmail.com> on dri-devel. This code doesn't let the 3D driver work properly as the card has no vertex shader support. Thanks to Matthew Garrett + Ubuntu for providing me some hardware to do this work on.
2007-04-06i915: use breadcrumb macro everywhereDave Airlie
2007-04-06nouveau: make a note about a bit that breaks some cardsBen Skeggs
2007-04-06nouveau: Power up all card units by default on startup.Ben Skeggs
2007-04-03Make sure we ack irqs before we read a breadcrumb so thatThomas Hellstrom
breadcrumb updates that occur _AFTER_ we've read the breadcrumb really generates a new IRQ.
2007-04-02r300: Synchronize the register header file again.Oliver McFadden
It's a good idea to keep these synchronized; even though the DRM doesn't use all the defines, maintaining two different copies is prone to errors when the diff gets bigger.
2007-04-01nouveau: fix usage of PGRAPH_CTX_CONTROL on nv20+Matthieu Castet
http://gitweb.freedesktop.org/?p=mesa/drm.git;a=commitdiff;h=17985f07d68322519919a7f629a6d2d9bf3916ed could have broken some nvxx_graph code : it rename NV03_PGRAPH_CTX_CONTROL to NV10_PGRAPH_CTX_CONTROL, but forgot to update it in nvxx_graph file. Also when migrating init stuff in http://gitweb.freedesktop.org/?p=mesa/drm.git;a=commitdiff;h=674cefd4fe4b537a20a10edcb4ec5df55facca8e, NV04_PGRAPH_CTX_CONTROL is used everywhere but the old ddx code use NV_PGRAPH_CTX_CONTROL_NV04 or NV_PGRAPH_CTX_CONTROL.
2007-04-01nouveau : nv10 ctx switch fixMatthieu Castet
restoring NV10_PGRAPH_CTX_SWITCH1 now works
2007-04-01nouveau : set the correct PGRAPH_CTX_CONTROL registerMatthieu Castet
"5a072f32 (Stephane Marchesin 2007-02-03 04:57:06 +0100" broke nv10 ctx switch by setting wrong PGRAPH_CTX_CONTROL reg
2007-03-30Merge branch 'crestline-qa', adding support for the 965GM chipset.Eric Anholt
2007-03-29nouveau: fix nv04 context switches.Stephane Marchesin
2007-03-27drm/i915: set the bo up at firstopen time not after DMA initDave Airlie
This is required to use TTM to allocate the ring buffer.
2007-03-27Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestlineNian Wu
2007-03-26nouveau: move card initialisation into the drmBen Skeggs
The PGRAPH init for the various cards will need cleaning up at some point, a lot of the values written there are per-context state left over from the all the hardcoding done in the ddx. It's possible some cards get broken by this commit, let me know. Tested on: NV5, NV18, NV28, NV35, NV40, NV4E
2007-03-23Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestlineNian Wu
2007-03-23nouveau: rework nouveau_fifo_alloc() so the drm can create internal FIFOsBen Skeggs
2007-03-23nouveau: remove unused cruftBen Skeggs
2007-03-21Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestlineNian Wu
2007-03-21nouveau: support multiple channels per client (breaks drm interface)Ben Skeggs
2007-03-19Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestlineNian Wu
2007-03-19more whitespace issuesDave Airlie
2007-03-19whitespace cleanup pending a kernel mergeDave Airlie
2007-03-14Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestlineNian Wu
2007-03-13r300: Renamed the CACHE_CTLSTAT values to include UNKNOWN in the name; notOliver McFadden
enough information is known about them to be sure as to what the values mean.
2007-03-13Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestlineNian Wu
2007-03-13Add defines for the values written to R300_RB3D_ZCACHE_CTLSTAT.Oliver McFadden
Note that just like the values written to R300_RB3D_DSTCACHE_CTLSTAT these values are really unknown; ideally more reverse engineering should be done to determine what these values mean and when they should be set.
2007-03-13nouveau: make sure cmdbuf object gets destroyedBen Skeggs
2007-03-13nouveau: associate all created objects with a channel + cleanupsBen Skeggs
2007-03-13nouveau: s/fifo/channel/Ben Skeggs
2007-03-13Corrected values written to R300_RB3D_DSTCACHE_CTLSTAT to eitherOliver McFadden
R300_RB3D_DSTCACHE_02 or R300_RB3D_DSTCACHE_0A, rather than hexadecimal values.
2007-03-13Guess another unknown register used for R300 pacification.Oliver McFadden
2007-03-12Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestlineNian Wu
2007-03-11nouveau: PUT,GET, not 2xPUTPatrice Mandin
2007-03-07Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestlineNian Wu
2007-03-07Add via CX700.Thomas Hellstrom
2007-03-05Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestlineNian Wu
2007-03-04radeon: make PCI GART aperture size variable, but making table size variableDave Airlie
This is precursor to getting a TTM backend for this stuff, and also allows the PCI table to be allocated at fb 0
2007-03-04ati: make pcigart code able to handle variable size PCI GART apertureDave Airlie
This code doesn't enable a variable aperture it just modifies the codebase to allow me fix it up later
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