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AgeCommit message (Expand)Author
2007-02-02Disable AGP DMA for chips with the new 3D engine.Thomas Hellstrom
2007-01-31memory manager: Make device driver aware of different memory types.Thomas Hellstrom
2007-01-28nouveau: determine chipset type at startup, instead of every time we use it.Ben Skeggs
2007-01-26make works ctx switch on nv10.Matthieu Castet
2007-01-26nouveau: oops, wrong indexing in nv17 regsPatrice Mandin
2007-01-26nouveau: read gpu type oncePatrice Mandin
2007-01-26nouveau: only save/restore nv17 regs on nv17,18 hwPatrice Mandin
2007-01-26nouveau: add extra pgraph registersPatrice Mandin
2007-01-26nouveau: add some nv10 pgraph definesPatrice Mandin
2007-01-25nouveau: simplify and fix BIG_ENDIAN flagsPatrice Mandin
2007-01-25nouveau: nv4c default contextBen Skeggs
2007-01-25nouveau: always print nsource/nstatus regs on PGRAPH errorsBen Skeggs
2007-01-24vblank interrupt fixZou Nan hai
2007-01-19nouveau: fix getparam from 32-bit client on 64-bit kernelBen Skeggs
2007-01-19nouveau: re-add 6150 Go pciid (0x0244)Ben Skeggs
2007-01-18nouveau: cleanup nv30_graph.cJeremy Kolb
2007-01-18nouveau: Remove write to CTX_SIZE. This gives us proper nv3x PGRAPH switching.Jeremy Kolb
2007-01-18add missing quadro idDave Jones
2007-01-17nouveau: Try to get nv35 pgraph switching working. Doesn't quite yet.Jeremy Kolb
2007-01-14nouveau: opps nv20 ctx ramin size was wrongMatthieu Castet
2007-01-13nouveau: opps restored the wrong channelMatthieu Castet
2007-01-13nouveau: nv20 graph ctx switch.Matthieu Castet
2007-01-13nouveau: first step to make graph ctx worksMatthieu Castet
2007-01-13nouveau: add and indent pgraph regsMatthieu Castet
2007-01-13nouveau: Oops, fix the nv04 RAMFC_DMA_FETCH value.Stephane Marchesin
2007-01-12nouveau : remove useless init : we clear RAMIN beforeMatthieu Castet
2007-01-12Delay for a usec while spinning waiting for ring buffer space.Haihao Xiang
2007-01-12nouveau: get nv30 context switching to work.Jeremy Kolb
2007-01-11radeon: Fix u32 overflows when determining AGP base address in card space.Michel Dänzer
2007-01-09novueau: try resource 3 if resource 2 is 0 lengthDave Airlie
2007-01-08nouveau: fix nv4a context size.Stephane Marchesin
2007-01-08nouveau: nv4a context support.Stephane Marchesin
2007-01-08Merge branch 'master' of git+ssh://marcheu@git.freedesktop.org/git/mesa/drmStephane Marchesin
2007-01-08nouveau: oopsBen Skeggs
2007-01-08nouveau: nv43 context stuffBen Skeggs
2007-01-08nouveau: fix a stupid bug from me.Stephane Marchesin
2007-01-08nouveau: avoid allocating vram that's used as instance memory.Ben Skeggs
2007-01-08nouveau: map pci resource 2 on >=nv40Ben Skeggs
2007-01-06Revert i915 drm driver name to i915; miniglx doesn't work otherwiseKeith Packard
2007-01-06Bump i915 minor for ARB_OC ioctlWang Zhenyu
2007-01-06i915: ARB_Occlusion_query(MMIO ioctl) support.Zou Nan hai
2007-01-06nouveau: get c51 doing glxgears without the binary driver's help.Ben Skeggs
2007-01-06nouveau: Use PMC_BOOT_0 to determine which ctx_voodoo to load.Ben Skeggs
2007-01-05nouveau: oops, we don't need OS_HAS_MTRR actually.Stephane Marchesin
2007-01-05Merge branch 'master' of git+ssh://marcheu@git.freedesktop.org/git/mesa/drmStephane Marchesin
2007-01-05nouveau: Add an mtrr over the whole FBStephane Marchesin
2007-01-05Merge branch 'master' of git+ssh://matc@git.freedesktop.org/git/mesa/drm/Matthieu Castet
2007-01-05Add basic pgraph context for nv10.Matthieu Castet
2007-01-05Cleanup the nv04 fifo code a bit.Stephane Marchesin
2007-01-02i915: Fix a DRM_ERROR that should be DRM_DEBUG.Michel Dänzer
generated by cgit v1.2.3 (git 2.25.1) at 2025-09-01 10:42:23 +0000
lass="hl ppc">#define MACH64_UPLOAD_CONTEXT 0x00ff #define MACH64_UPLOAD_ALL 0x1fff /* DMA buffer size */ #define MACH64_BUFFER_SIZE 16384 /* Max number of swaps allowed on the ring * before the client must wait */ #define MACH64_MAX_QUEUED_FRAMES 3U /* Byte offsets for host blit buffer data */ #define MACH64_HOSTDATA_BLIT_OFFSET 104 /* Keep these small for testing. */ #define MACH64_NR_SAREA_CLIPRECTS 8 #define MACH64_CARD_HEAP 0 #define MACH64_AGP_HEAP 1 #define MACH64_NR_TEX_HEAPS 2 #define MACH64_NR_TEX_REGIONS 64 #define MACH64_LOG_TEX_GRANULARITY 16 #define MACH64_TEX_MAXLEVELS 1 #define MACH64_NR_CONTEXT_REGS 15 #define MACH64_NR_TEXTURE_REGS 4 #endif /* __MACH64_SAREA_DEFINES__ */ typedef struct { unsigned int dst_off_pitch; unsigned int z_off_pitch; unsigned int z_cntl; unsigned int alpha_tst_cntl; unsigned int scale_3d_cntl; unsigned int sc_left_right; unsigned int sc_top_bottom; unsigned int dp_fog_clr; unsigned int dp_write_mask; unsigned int dp_pix_width; unsigned int dp_mix; unsigned int dp_src; unsigned int clr_cmp_cntl; unsigned int gui_traj_cntl; unsigned int setup_cntl; unsigned int tex_size_pitch; unsigned int tex_cntl; unsigned int secondary_tex_off; unsigned int tex_offset; } drm_mach64_context_regs_t; typedef struct drm_mach64_sarea { /* The channel for communication of state information to the kernel * on firing a vertex dma buffer. */ drm_mach64_context_regs_t context_state; unsigned int dirty; unsigned int vertsize; /* The current cliprects, or a subset thereof. */ struct drm_clip_rect boxes[MACH64_NR_SAREA_CLIPRECTS]; unsigned int nbox; /* Counters for client-side throttling of rendering clients. */ unsigned int frames_queued; /* Texture memory LRU. */ struct drm_tex_region tex_list[MACH64_NR_TEX_HEAPS][MACH64_NR_TEX_REGIONS + 1]; unsigned int tex_age[MACH64_NR_TEX_HEAPS]; int ctx_owner; } drm_mach64_sarea_t; /* WARNING: If you change any of these defines, make sure to change the * defines in the Xserver file (mach64_common.h) */ /* Mach64 specific ioctls * The device specific ioctl range is 0x40 to 0x79. */ #define DRM_MACH64_INIT 0x00 #define DRM_MACH64_IDLE 0x01 #define DRM_MACH64_RESET 0x02 #define DRM_MACH64_SWAP 0x03 #define DRM_MACH64_CLEAR 0x04 #define DRM_MACH64_VERTEX 0x05 #define DRM_MACH64_BLIT 0x06 #define DRM_MACH64_FLUSH 0x07 #define DRM_MACH64_GETPARAM 0x08 #define DRM_IOCTL_MACH64_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_INIT, drm_mach64_init_t) #define DRM_IOCTL_MACH64_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_MACH64_IDLE ) #define DRM_IOCTL_MACH64_RESET DRM_IO( DRM_COMMAND_BASE + DRM_MACH64_RESET ) #define DRM_IOCTL_MACH64_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_MACH64_SWAP ) #define DRM_IOCTL_MACH64_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_CLEAR, drm_mach64_clear_t) #define DRM_IOCTL_MACH64_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_VERTEX, drm_mach64_vertex_t) #define DRM_IOCTL_MACH64_BLIT DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_BLIT, drm_mach64_blit_t) #define DRM_IOCTL_MACH64_FLUSH DRM_IO( DRM_COMMAND_BASE + DRM_MACH64_FLUSH ) #define DRM_IOCTL_MACH64_GETPARAM DRM_IOWR( DRM_COMMAND_BASE + DRM_MACH64_GETPARAM, drm_mach64_getparam_t) /* Buffer flags for clears */ #define MACH64_FRONT 0x1 #define MACH64_BACK 0x2 #define MACH64_DEPTH 0x4 /* Primitive types for vertex buffers */ #define MACH64_PRIM_POINTS 0x00000000 #define MACH64_PRIM_LINES 0x00000001 #define MACH64_PRIM_LINE_LOOP 0x00000002 #define MACH64_PRIM_LINE_STRIP 0x00000003 #define MACH64_PRIM_TRIANGLES 0x00000004 #define MACH64_PRIM_TRIANGLE_STRIP 0x00000005 #define MACH64_PRIM_TRIANGLE_FAN 0x00000006 #define MACH64_PRIM_QUADS 0x00000007 #define MACH64_PRIM_QUAD_STRIP 0x00000008 #define MACH64_PRIM_POLYGON 0x00000009 typedef enum _drm_mach64_dma_mode_t { MACH64_MODE_DMA_ASYNC, MACH64_MODE_DMA_SYNC, MACH64_MODE_MMIO } drm_mach64_dma_mode_t; typedef struct drm_mach64_init { enum { DRM_MACH64_INIT_DMA = 0x01, DRM_MACH64_CLEANUP_DMA = 0x02 } func; unsigned long sarea_priv_offset; int is_pci; drm_mach64_dma_mode_t dma_mode; unsigned int fb_bpp; unsigned int front_offset, front_pitch; unsigned int back_offset, back_pitch; unsigned int depth_bpp; unsigned int depth_offset, depth_pitch; unsigned long fb_offset; unsigned long mmio_offset; unsigned long ring_offset; unsigned long buffers_offset; unsigned long agp_textures_offset; } drm_mach64_init_t; typedef struct drm_mach64_clear { unsigned int flags; int x, y, w, h; unsigned int clear_color; unsigned int clear_depth; } drm_mach64_clear_t; typedef struct drm_mach64_vertex { int prim; void *buf; /* Address of vertex buffer */ unsigned long used; /* Number of bytes in buffer */ int discard; /* Client finished with buffer? */ } drm_mach64_vertex_t; typedef struct drm_mach64_blit { void *buf; int pitch; int offset; int format; unsigned short x, y; unsigned short width, height; } drm_mach64_blit_t; typedef struct drm_mach64_getparam { enum { MACH64_PARAM_FRAMES_QUEUED = 0x01, MACH64_PARAM_IRQ_NR = 0x02 } param; void *value; } drm_mach64_getparam_t; #endif
generated by cgit v1.2.3 (git 2.25.1) at 2025-09-01 10:42:22 +0000