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authorJeremy Kolb <jkolb@brandeis.edu>2007-01-18 21:39:09 -0500
committerJeremy Kolb <jkolb@brandeis.edu>2007-01-18 21:40:21 -0500
commitab72a7714e4e9b87cc93887d1978f1c533255566 (patch)
tree4b95e8bb8fa070e91450767db5c8d8a7841777db /shared-core
parentbd0418cb01232d7529ecb0f515aa9b6d6804a3ac (diff)
nouveau: Remove write to CTX_SIZE. This gives us proper nv3x PGRAPH switching.
Diffstat (limited to 'shared-core')
-rw-r--r--shared-core/nouveau_fifo.c5
1 files changed, 0 insertions, 5 deletions
diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c
index 8ea0564d..e80ba766 100644
--- a/shared-core/nouveau_fifo.c
+++ b/shared-core/nouveau_fifo.c
@@ -368,12 +368,7 @@ static void nouveau_nv30_context_init(drm_device_t *dev,
RAMFC_WR(ACQUIRE_TIMESTAMP, NV_READ(NV_PFIFO_CACH1_ACQUIRE_TIMESTAMP));
RAMFC_WR(ACQUIRE_TIMEOUT, NV_READ(NV_PFIFO_CACH1_ACQUIRE_TIMEOUT));
RAMFC_WR(SEMAPHORE, NV_READ(NV_PFIFO_CACH1_SEMAPHORE));
- NV_WRITE(NV_PGRAPH_CHANNEL_CTX_SIZE, grctx_inst); /* Misnomer. Really a ptr to the grctx */
- /*
- * TODO: We need to put this somewhere...
- */
- /*INSTANCE_WR(dev_priv->ctx_table, init->channel, grctx_inst);*/
RAMFC_WR(DMA_SUBROUTINE, init->put_base);
}