| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2007-02-06 | nouveau: more work on the nv04 context switch code. | Stephane Marchesin | |
| 2007-02-03 | nouveau: and of course, I was missing the last nv04 piece. | Stephane Marchesin | |
| 2007-02-03 | nouveau: plugin the nv04 graph init function. | Stephane Marchesin | |
| 2007-02-03 | nouveau: cleanup the nv04 pgraph save/restore mechanism. | Stephane Marchesin | |
| 2007-02-03 | nouveau: fix nv04 graph routines for new register names. | Stephane Marchesin | |
| 2007-02-03 | nouveau: rename registers to their proper names. | Stephane Marchesin | |
| 2007-02-03 | nouveau: add NV04 registers required for PGRAPH context switching. | Stephane Marchesin | |
| 2007-02-02 | nouveau: nv ctx switch opps the size of array was wrong | Matthieu Castet | |
| 2007-02-02 | nouveau: nv10 ctx switch, some regs are nv17+ only | Matthieu Castet | |
| 2007-02-02 | via: Try to improve command-buffer chaining. | Thomas Hellstrom | |
| Bump driver date and patchlevel. | |||
| 2007-02-02 | Disable AGP DMA for chips with the new 3D engine. | Thomas Hellstrom | |
| 2007-01-28 | nouveau: determine chipset type at startup, instead of every time we use it. | Ben Skeggs | |
| 2007-01-26 | make works ctx switch on nv10. | Matthieu Castet | |
| 2007-01-26 | nouveau: oops, wrong indexing in nv17 regs | Patrice Mandin | |
| 2007-01-26 | nouveau: read gpu type once | Patrice Mandin | |
| 2007-01-26 | nouveau: only save/restore nv17 regs on nv17,18 hw | Patrice Mandin | |
| 2007-01-26 | nouveau: add extra pgraph registers | Patrice Mandin | |
| 2007-01-26 | nouveau: add some nv10 pgraph defines | Patrice Mandin | |
| 2007-01-25 | nouveau: simplify and fix BIG_ENDIAN flags | Patrice Mandin | |
| 2007-01-25 | nouveau: nv4c default context | Ben Skeggs | |
| 2007-01-25 | nouveau: always print nsource/nstatus regs on PGRAPH errors | Ben Skeggs | |
| 2007-01-24 | vblank interrupt fix | Zou Nan hai | |
| 2007-01-19 | nouveau: fix getparam from 32-bit client on 64-bit kernel | Ben Skeggs | |
| 2007-01-19 | nouveau: re-add 6150 Go pciid (0x0244) | Ben Skeggs | |
| 2007-01-18 | nouveau: cleanup nv30_graph.c | Jeremy Kolb | |
| 2007-01-18 | nouveau: Remove write to CTX_SIZE. This gives us proper nv3x PGRAPH switching. | Jeremy Kolb | |
| 2007-01-18 | add missing quadro id | Dave Jones | |
| 2007-01-17 | nouveau: Try to get nv35 pgraph switching working. Doesn't quite yet. | Jeremy Kolb | |
| Hook into nv20 pgraph switching functions (they're identical for nv3x). Actually call nv30_pgraph_context_init so the ctx_table is allocated. Thanks to Carlos Martin for the help. | |||
| 2007-01-14 | nouveau: opps nv20 ctx ramin size was wrong | Matthieu Castet | |
| 2007-01-13 | nouveau: opps restored the wrong channel | Matthieu Castet | |
| 2007-01-13 | nouveau: nv20 graph ctx switch. | Matthieu Castet | |
| Untested... | |||
| 2007-01-13 | nouveau: first step to make graph ctx works | Matthieu Castet | |
| It is still not working, but now we could use some 3D commands without needed to run nvidia blob before. | |||
| 2007-01-13 | nouveau: add and indent pgraph regs | Matthieu Castet | |
| 2007-01-13 | nouveau: Oops, fix the nv04 RAMFC_DMA_FETCH value. | Stephane Marchesin | |
| 2007-01-12 | nouveau : remove useless init : we clear RAMIN before | Matthieu Castet | |
| 2007-01-12 | Delay for a usec while spinning waiting for ring buffer space. | Haihao Xiang | |
| This means the loop will wait up to ~10ms for ring buffer space to become available, rather than just however long it takes to check the space 10000 times. This matches other drivers' behavior when waiting for ring buffer/fifo space. | |||
| 2007-01-12 | nouveau: get nv30 context switching to work. | Jeremy Kolb | |
| * Pulled in some registers from nv10reg.h. Needed for context switching. * Filled in nv30 graphics context (based on nv40_graph.c). * Figure out nv30 context table, set up on context creation. Allows the cards automatic switching to work. | |||
| 2007-01-11 | radeon: Fix u32 overflows when determining AGP base address in card space. | Michel Dänzer | |
| The overflows could lead to the AGP aperture overlapping the framebuffer area in the card's address space when the latter is located at the very end of the 32 bit address space, which would result in a freeze on X server startup, probably because the card read commands from the framebuffer instead of from AGP. See http://bugs.debian.org/cgi-bin/bugreport.cgi?bug=392915 . | |||
| 2007-01-09 | novueau: try resource 3 if resource 2 is 0 length | Dave Airlie | |
| This happens on my NV43 PPC | |||
| 2007-01-08 | nouveau: fix nv4a context size. | Stephane Marchesin | |
| 2007-01-08 | nouveau: nv4a context support. | Stephane Marchesin | |
| 2007-01-08 | Merge branch 'master' of git+ssh://marcheu@git.freedesktop.org/git/mesa/drm | Stephane Marchesin | |
| 2007-01-08 | nouveau: oops | Ben Skeggs | |
| 2007-01-08 | nouveau: nv43 context stuff | Ben Skeggs | |
| 2007-01-08 | nouveau: fix a stupid bug from me. | Stephane Marchesin | |
| 2007-01-08 | nouveau: avoid allocating vram that's used as instance memory. | Ben Skeggs | |
| 2007-01-08 | nouveau: map pci resource 2 on >=nv40 | Ben Skeggs | |
| 2007-01-06 | Revert i915 drm driver name to i915; miniglx doesn't work otherwise | Keith Packard | |
| Yes, this driver supports the new memory manager, that is indicated by the version number being >= 1.7. | |||
| 2007-01-06 | Bump i915 minor for ARB_OC ioctl | Wang Zhenyu | |
| 2007-01-06 | i915: ARB_Occlusion_query(MMIO ioctl) support. | Zou Nan hai | |
| This adds a new ioctl for passing counter information from the chip back to applications, these counters include the data needed to perform OC. | |||
 |
index : renesas/drm.git | |
| libdrm, cloned from git://anongit.freedesktop.org/mesa/drm | Laurent Pinchart |
| summaryrefslogtreecommitdiff |
path: root/shared-core