| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2007-04-06 | nouveau: Power up all card units by default on startup. | Ben Skeggs | |
| 2007-04-03 | Make sure we ack irqs before we read a breadcrumb so that | Thomas Hellstrom | |
| breadcrumb updates that occur _AFTER_ we've read the breadcrumb really generates a new IRQ. | |||
| 2007-04-02 | r300: Synchronize the register header file again. | Oliver McFadden | |
| It's a good idea to keep these synchronized; even though the DRM doesn't use all the defines, maintaining two different copies is prone to errors when the diff gets bigger. | |||
| 2007-04-01 | nouveau: fix usage of PGRAPH_CTX_CONTROL on nv20+ | Matthieu Castet | |
| http://gitweb.freedesktop.org/?p=mesa/drm.git;a=commitdiff;h=17985f07d68322519919a7f629a6d2d9bf3916ed could have broken some nvxx_graph code : it rename NV03_PGRAPH_CTX_CONTROL to NV10_PGRAPH_CTX_CONTROL, but forgot to update it in nvxx_graph file. Also when migrating init stuff in http://gitweb.freedesktop.org/?p=mesa/drm.git;a=commitdiff;h=674cefd4fe4b537a20a10edcb4ec5df55facca8e, NV04_PGRAPH_CTX_CONTROL is used everywhere but the old ddx code use NV_PGRAPH_CTX_CONTROL_NV04 or NV_PGRAPH_CTX_CONTROL. | |||
| 2007-04-01 | nouveau : nv10 ctx switch fix | Matthieu Castet | |
| restoring NV10_PGRAPH_CTX_SWITCH1 now works | |||
| 2007-04-01 | nouveau : set the correct PGRAPH_CTX_CONTROL register | Matthieu Castet | |
| "5a072f32 (Stephane Marchesin 2007-02-03 04:57:06 +0100" broke nv10 ctx switch by setting wrong PGRAPH_CTX_CONTROL reg | |||
| 2007-03-30 | Merge branch 'crestline-qa', adding support for the 965GM chipset. | Eric Anholt | |
| 2007-03-29 | nouveau: fix nv04 context switches. | Stephane Marchesin | |
| 2007-03-27 | drm/i915: set the bo up at firstopen time not after DMA init | Dave Airlie | |
| This is required to use TTM to allocate the ring buffer. | |||
| 2007-03-27 | Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline | Nian Wu | |
| 2007-03-26 | nouveau: move card initialisation into the drm | Ben Skeggs | |
| The PGRAPH init for the various cards will need cleaning up at some point, a lot of the values written there are per-context state left over from the all the hardcoding done in the ddx. It's possible some cards get broken by this commit, let me know. Tested on: NV5, NV18, NV28, NV35, NV40, NV4E | |||
| 2007-03-23 | Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline | Nian Wu | |
| 2007-03-23 | nouveau: rework nouveau_fifo_alloc() so the drm can create internal FIFOs | Ben Skeggs | |
| 2007-03-23 | nouveau: remove unused cruft | Ben Skeggs | |
| 2007-03-21 | Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline | Nian Wu | |
| 2007-03-21 | nouveau: support multiple channels per client (breaks drm interface) | Ben Skeggs | |
| 2007-03-19 | Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline | Nian Wu | |
| 2007-03-19 | more whitespace issues | Dave Airlie | |
| 2007-03-19 | whitespace cleanup pending a kernel merge | Dave Airlie | |
| 2007-03-14 | Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline | Nian Wu | |
| 2007-03-13 | r300: Renamed the CACHE_CTLSTAT values to include UNKNOWN in the name; not | Oliver McFadden | |
| enough information is known about them to be sure as to what the values mean. | |||
| 2007-03-13 | Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline | Nian Wu | |
| 2007-03-13 | Add defines for the values written to R300_RB3D_ZCACHE_CTLSTAT. | Oliver McFadden | |
| Note that just like the values written to R300_RB3D_DSTCACHE_CTLSTAT these values are really unknown; ideally more reverse engineering should be done to determine what these values mean and when they should be set. | |||
| 2007-03-13 | nouveau: make sure cmdbuf object gets destroyed | Ben Skeggs | |
| 2007-03-13 | nouveau: associate all created objects with a channel + cleanups | Ben Skeggs | |
| 2007-03-13 | nouveau: s/fifo/channel/ | Ben Skeggs | |
| 2007-03-13 | Corrected values written to R300_RB3D_DSTCACHE_CTLSTAT to either | Oliver McFadden | |
| R300_RB3D_DSTCACHE_02 or R300_RB3D_DSTCACHE_0A, rather than hexadecimal values. | |||
| 2007-03-13 | Guess another unknown register used for R300 pacification. | Oliver McFadden | |
| 2007-03-12 | Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline | Nian Wu | |
| 2007-03-11 | nouveau: PUT,GET, not 2xPUT | Patrice Mandin | |
| 2007-03-07 | Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline | Nian Wu | |
| 2007-03-07 | Add via CX700. | Thomas Hellstrom | |
| 2007-03-05 | Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline | Nian Wu | |
| 2007-03-04 | radeon: make PCI GART aperture size variable, but making table size variable | Dave Airlie | |
| This is precursor to getting a TTM backend for this stuff, and also allows the PCI table to be allocated at fb 0 | |||
| 2007-03-04 | ati: make pcigart code able to handle variable size PCI GART aperture | Dave Airlie | |
| This code doesn't enable a variable aperture it just modifies the codebase to allow me fix it up later | |||
| 2007-03-01 | Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline | Nian Wu | |
| 2007-02-28 | nouveau: intrusive drm interface changes | Ben Skeggs | |
| graphics objects: - No longer takes flags/dmaobj parameters, requires some major changes to the ddx to setup the object through the FIFO. This change is likely to cause breakages on some cards (tested on NV05,NV28,NV35, NV40 and NV4E). dma objects: - now takes a "class" parameter, not really used yet but we may need it at some point. - parameters are checked, so clients can't randomly create DMA objects pointing at whatever they feel like. misc: - Added FB_SIZE/AGP_SIZE getparams - Read PFIFO_INTR in PFIFO irq handler, not PMC_INTR - Dump PGRAPH trap info on PGRAPH_INTR_NOTIFY if NSOURCE isn't NOTIFICATION_PENDING. | |||
| 2007-02-25 | Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline | Nian Wu | |
| 2007-02-25 | drm: remove unnecessary NULL checks, and fix some indents.. | Jakob Bornecrantz | |
| 2007-02-16 | Simple fence object sample driver for via, based on idling the GPU. | Thomas Hellstrom | |
| Buffer object driver for via. Some changes to buffer object driver callbacks. Improve fence flushing. | |||
| 2007-02-15 | Initial support for fence object classes. | Thomas Hellstrom | |
| (Fence objects belonging to different command submission mechanisms). | |||
| 2007-02-14 | Merge branch 'ttm-vram-0-1-branch' | Thomas Hellstrom | |
| 2007-02-14 | Remove an intel-specific hack and replace it with a fence driver callback. | Thomas Hellstrom | |
| 2007-02-14 | nouveau: fix the build on big endian (thanks CyberFoxx) | Stephane Marchesin | |
| 2007-02-14 | nouveau: fix memory initialization with multiple cards. | B. Rathmann | |
| 2007-02-13 | Bugzilla Bug #9457 | Thomas Hellstrom | |
| Add refcounting of user waiters to the DRM hardware lock, so that we can use the DRM_LOCK_CONT flag more conservatively. Also add a kernel waiter refcount that if nonzero transfers the lock for the kernel context, when it is released. This is useful when waiting for idle and can be used for very simple fence object driver implementations for the new memory manager. It also resolves the AIGLX startup deadlock for the sis and the via drivers. i810, i830 still require that the hardware lock is really taken so the deadlock remains for those two. I'm not sure about ffb. Anyone familiar with that code? | |||
| 2007-02-13 | i915: Add 965GM pci id update | Wang Zhenyu | |
| 2007-02-12 | Update flags and comments. | Thomas Hellstrom | |
| 2007-02-11 | Sync r300_reg.h from mesa driver. #10210 | Aapo Tahkola | |
| 2007-03-10 | Merge branch 'i915-pageflip' | Michel Dänzer | |
 |
index : renesas/drm.git | |
| libdrm, cloned from git://anongit.freedesktop.org/mesa/drm | Laurent Pinchart |
| summaryrefslogtreecommitdiff |
path: root/shared-core